ASoC: wcd934x-dsp-cntl: fix the reset sequence

Currently, whenever the codec DSP is reset, the CPAR hardware block
is not reset. This causes failure to boot DSP in good state. Update
CPAR reset sequence to ensure CPAR is put to reset when not in use.

CRs-fixed: 1091032
Change-Id: I77fea396fda6ee0eaaf0c68b11cf90f268ac1481
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
This commit is contained in:
Bhalchandra Gajare 2016-12-06 17:30:36 -08:00 committed by Gerrit - the friendly Code Review server
parent 5f30ee1cc5
commit 224cef9688

View file

@ -401,6 +401,8 @@ static int wcd_cntl_clocks_enable(struct wcd_dsp_cntl *cntl)
__func__, ret);
goto done;
}
/* Pull CPAR out of reset */
snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x04, 0x00);
/* Configure and Enable CPE FLL clock */
ret = wcd_cntl_cpe_fll_ctrl(cntl, true);
@ -422,6 +424,7 @@ err_cpe_clk:
if (cntl->cdc_cb && cntl->cdc_cb->cdc_clk_en)
cntl->cdc_cb->cdc_clk_en(codec, false);
snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x04, 0x04);
WCD_CNTL_MUTEX_UNLOCK(codec, cntl->clk_mutex);
return ret;
}
@ -458,6 +461,9 @@ static int wcd_cntl_clocks_disable(struct wcd_dsp_cntl *cntl)
ret = -EINVAL;
cntl->is_clk_enabled = false;
/* Put CPAR in reset */
snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x04, 0x04);
done:
WCD_CNTL_MUTEX_UNLOCK(codec, cntl->clk_mutex);
return ret;
@ -469,9 +475,9 @@ static void wcd_cntl_cpar_ctrl(struct wcd_dsp_cntl *cntl,
struct snd_soc_codec *codec = cntl->codec;
if (enable)
snd_soc_write(codec, WCD934X_CPE_SS_CPAR_CTL, 0x03);
snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x03, 0x03);
else
snd_soc_write(codec, WCD934X_CPE_SS_CPAR_CTL, 0x00);
snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x03, 0x00);
}
static int wcd_cntl_enable_memory(struct wcd_dsp_cntl *cntl,