ASoC: wcd934x-dsp-cntl: fix the reset sequence
Currently, whenever the codec DSP is reset, the CPAR hardware block is not reset. This causes failure to boot DSP in good state. Update CPAR reset sequence to ensure CPAR is put to reset when not in use. CRs-fixed: 1091032 Change-Id: I77fea396fda6ee0eaaf0c68b11cf90f268ac1481 Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
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5f30ee1cc5
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1 changed files with 8 additions and 2 deletions
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@ -401,6 +401,8 @@ static int wcd_cntl_clocks_enable(struct wcd_dsp_cntl *cntl)
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__func__, ret);
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goto done;
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}
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/* Pull CPAR out of reset */
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snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x04, 0x00);
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/* Configure and Enable CPE FLL clock */
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ret = wcd_cntl_cpe_fll_ctrl(cntl, true);
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@ -422,6 +424,7 @@ err_cpe_clk:
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if (cntl->cdc_cb && cntl->cdc_cb->cdc_clk_en)
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cntl->cdc_cb->cdc_clk_en(codec, false);
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snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x04, 0x04);
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WCD_CNTL_MUTEX_UNLOCK(codec, cntl->clk_mutex);
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return ret;
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}
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@ -458,6 +461,9 @@ static int wcd_cntl_clocks_disable(struct wcd_dsp_cntl *cntl)
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ret = -EINVAL;
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cntl->is_clk_enabled = false;
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/* Put CPAR in reset */
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snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x04, 0x04);
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done:
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WCD_CNTL_MUTEX_UNLOCK(codec, cntl->clk_mutex);
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return ret;
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@ -469,9 +475,9 @@ static void wcd_cntl_cpar_ctrl(struct wcd_dsp_cntl *cntl,
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struct snd_soc_codec *codec = cntl->codec;
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if (enable)
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snd_soc_write(codec, WCD934X_CPE_SS_CPAR_CTL, 0x03);
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snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x03, 0x03);
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else
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snd_soc_write(codec, WCD934X_CPE_SS_CPAR_CTL, 0x00);
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snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x03, 0x00);
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}
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static int wcd_cntl_enable_memory(struct wcd_dsp_cntl *cntl,
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