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ARM: dts: msm: Enable LMH DCVSh driver for sdm660

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Enable LMH DCVSh driver for sdm660. It adds information about
the interrupt generated by the LMH DCVSh block for sdm660.

Change-Id: I6cd07ef4825aaa57cf3d58ea239c9fbc05c4e442
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
This commit is contained in:
Manaf Meethalavalappu Pallikunhi 2017-01-12 22:37:39 +05:30
parent 2dc96b1cbb
commit 2468799b76
1 changed files with 20 additions and 0 deletions
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20
arch/arm/boot/dts/qcom/sdm660.dtsi
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@ -52,6 +52,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
qcom,ea = <&ea0>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
@ -77,6 +78,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
qcom,ea = <&ea1>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
@ -96,6 +98,7 @@
reg = <0x0 0x2>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
qcom,ea = <&ea2>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
@ -115,6 +118,7 @@
reg = <0x0 0x3>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
qcom,ea = <&ea3>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
@ -134,6 +138,7 @@
reg = <0x0 0x100>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile1>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
qcom,ea = <&ea4>;
efficiency = <1536>;
next-level-cache = <&L2_1>;
@ -157,6 +162,7 @@
reg = <0x0 0x101>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile2>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
qcom,ea = <&ea5>;
efficiency = <1536>;
next-level-cache = <&L2_1>;
@ -176,6 +182,7 @@
reg = <0x0 0x102>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile3>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
qcom,ea = <&ea6>;
efficiency = <1536>;
next-level-cache = <&L2_1>;
@ -195,6 +202,7 @@
reg = <0x0 0x103>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile4>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
qcom,ea = <&ea7>;
efficiency = <1536>;
next-level-cache = <&L2_1>;
@ -2331,6 +2339,18 @@
status = "ok";
};
&clock_cpu {
lmh_dcvs0: qcom,limits-dcvs@0 {
compatible = "qcom,msm-hw-limits";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
};
lmh_dcvs1: qcom,limits-dcvs@1 {
compatible = "qcom,msm-hw-limits";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
};
};
#include "msm-arm-smmu-660.dtsi"
#include "msm-arm-smmu-impl-defs-660.dtsi"
#include "sdm660-common.dtsi"