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Merge "ARM: dts: msm: Add sdhc1 support for msmfalcon"

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Linux Build Service Account 2016-10-19 19:11:50 -07:00 • committed by Gerrit - the friendly Code Review server
commit 24aeef9a54
4 changed files with 137 additions and 0 deletions
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64
arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi
View file

@ -48,5 +48,69 @@
output-low;
};
};
/* SDC pin type */
sdc1_clk_on: sdc1_clk_on {
config {
pins = "sdc1_clk";
bias-disable; /* NO pull */
drive-strength = <16>; /* 16 MA */
};
};
sdc1_clk_off: sdc1_clk_off {
config {
pins = "sdc1_clk";
bias-disable; /* NO pull */
drive-strength = <2>; /* 2 MA */
};
};
sdc1_cmd_on: sdc1_cmd_on {
config {
pins = "sdc1_cmd";
bias-pull-up; /* pull up */
drive-strength = <10>; /* 10 MA */
};
};
sdc1_cmd_off: sdc1_cmd_off {
config {
pins = "sdc1_cmd";
num-grp-pins = <1>;
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
sdc1_data_on: sdc1_data_on {
config {
pins = "sdc1_data";
bias-pull-up; /* pull up */
drive-strength = <10>; /* 10 MA */
};
};
sdc1_data_off: sdc1_data_off {
config {
pins = "sdc1_data";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
sdc1_rclk_on: sdc1_rclk_on {
config {
pins = "sdc1_rclk";
bias-pull-down; /* pull down */
};
};
sdc1_rclk_off: sdc1_rclk_off {
config {
pins = "sdc1_rclk";
bias-pull-down; /* pull down */
};
};
};
};

26
arch/arm/boot/dts/qcom/msmfalcon-rumi.dts
View file

@ -27,3 +27,29 @@
pinctrl-names = "default";
pinctrl-0 = <&uart_console_active>;
};
&sdhc_1 {
/* device core power supply */
vdd-supply = <&pmfalcon_l4b>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <200 570000>;
/* device communication power supply */
vdd-io-supply = <&pmfalcon_l8a>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <200 325000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
qcom,clk-rates = <400000 20000000 25000000 50000000 192000000
384000000>;
qcom,nonremovable;
qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
status = "ok";
};

26
arch/arm/boot/dts/qcom/msmfalcon-sim.dts
View file

@ -27,3 +27,29 @@
pinctrl-names = "default";
pinctrl-0 = <&uart_console_active>;
};
&sdhc_1 {
/* device core power supply */
vdd-supply = <&pmfalcon_l4b>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <200 570000>;
/* device communication power supply */
vdd-io-supply = <&pmfalcon_l8a>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <200 325000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
qcom,clk-rates = <400000 20000000 25000000 50000000 192000000
384000000>;
qcom,nonremovable;
qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
status = "ok";
};

21
arch/arm/boot/dts/qcom/msmfalcon.dtsi
View file

@ -26,6 +26,7 @@
aliases {
serial0 = &uartblsp1dm1;
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
};
chosen {
@ -403,6 +404,26 @@
#reset-cells = <1>;
};
sdhc_1: sdhci@c0c4000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>;
reg-names = "hc_mem", "cmdq_mem";
interrupts = <0 129 0>, <0 227 0>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,bus-width = <8>;
qcom,large-address-bus;
qcom,devfreq,freq-table = <50000000 200000000>;
clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
<&clock_gcc GCC_SDCC1_APPS_CLK>;
clock-names = "iface_clk", "core_clk";
status = "disabled";
};
qcom,ipc-spinlock@1f40000 {
compatible = "qcom,ipc-spinlock-sfpb";
reg = <0x1f40000 0x8000>;