ASoC: sdw-codec: Add support for MSM soundwire codec
In MSM based integrated codec, soundwire codec is added at HW level which supports wsa speaker using soundwire bus interface. Add respective driver support for MSM based soundwire codec. Change-Id: Ibe4abdbe15a6246b9abcf45402c22764b82699c2 Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
This commit is contained in:
Laxminath Kasam
parent
fe90883022
commit
2581137b0b
13 changed files with 2926 additions and 31 deletions
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@ -504,6 +504,41 @@ msm8x16_wcd_codec@f000{
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qcom,dig-cdc-base-addr = <0xc0f0000>;
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};
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MSM based Soundwire audio codec
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Required properties:
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- compatible = "qcom,msm-sdw-codec";
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- reg: Specifies the soundwire codec base address for MSM digital
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soundwire core registers.
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- interrupts: Specifies the soundwire master interrupt number to Apps processor.
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- interrupt-names: Specify the interrupt name from soundwire master.
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- swr_master: This node is added as a child of MSM soundwire codec
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and uses already existing driver soundwire master.
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And there is/are subchild node(s) under soundwire master
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which is also existing driver WSA881x that represents
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soundwire slave devices.
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Example:
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msm_sdw_codec: qcom,msm-sdw-codec@152c1000 {
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compatible = "qcom,msm-sdw-codec";
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reg = <0x152c1000 0x0>;
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interrupts = <0 161 0>;
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interrupt-names = "swr_master_irq";
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swr_master {
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compatible = "qcom,swr-wcd";
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#address-cells = <2>;
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#size-cells = <0>;
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wsa881x_1: wsa881x@20170212 {
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compatible = "qcom,wsa881x";
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reg = <0x00 0x20170212>;
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qcom,spkr-sd-n-gpio = <&tlmm 80 0>;
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};
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};
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};
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Tasha audio CODEC in I2C mode
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- compatible = "qcom,tasha-i2c-pgd";
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@ -995,5 +995,6 @@ config SND_SOC_MSM_HDMI_CODEC_RX
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supports hdmi panel.
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source "sound/soc/codecs/msm8x16/Kconfig"
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source "sound/soc/codecs/msm_sdw/Kconfig"
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endmenu
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@ -426,3 +426,4 @@ obj-$(CONFIG_SND_SOC_MSM_STUB) += snd-soc-msm-stub.o
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obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o
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obj-$(CONFIG_SND_SOC_TPA6130A2) += snd-soc-tpa6130a2.o
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obj-y += msm8x16/
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obj-y += msm_sdw/
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6
sound/soc/codecs/msm_sdw/Kconfig
Normal file
6
sound/soc/codecs/msm_sdw/Kconfig
Normal file
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@ -0,0 +1,6 @@
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config SND_SOC_MSM_SDW
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tristate "MSM Internal soundwire codec"
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help
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MSM-based soundwire codec core driver
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supported along with internal digital
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codec core.
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3
sound/soc/codecs/msm_sdw/Makefile
Normal file
3
sound/soc/codecs/msm_sdw/Makefile
Normal file
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@ -0,0 +1,3 @@
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snd-soc-msm-sdw-objs := msm_sdw_cdc.o msm_sdw_regmap.o msm-sdw-tables.o msm_sdw_cdc_utils.o
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obj-$(CONFIG_SND_SOC_MSM_SDW) += snd-soc-msm-sdw.o
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ccflags-y += -I$(srctree)/sound/soc/msm
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221
sound/soc/codecs/msm_sdw/msm-sdw-tables.c
Normal file
221
sound/soc/codecs/msm_sdw/msm-sdw-tables.c
Normal file
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@ -0,0 +1,221 @@
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/types.h>
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#include "msm_sdw.h"
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const u8 msm_sdw_page_map[MSM_SDW_MAX_REGISTER] = {
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[MSM_SDW_TX9_SPKR_PROT_PATH_CTL] = 0xa,
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[MSM_SDW_TX9_SPKR_PROT_PATH_CFG0] = 0xa,
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[MSM_SDW_TX10_SPKR_PROT_PATH_CTL] = 0xa,
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[MSM_SDW_TX10_SPKR_PROT_PATH_CFG0] = 0xa,
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[MSM_SDW_TX11_SPKR_PROT_PATH_CTL] = 0xa,
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[MSM_SDW_TX11_SPKR_PROT_PATH_CFG0] = 0xa,
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[MSM_SDW_TX12_SPKR_PROT_PATH_CTL] = 0xa,
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[MSM_SDW_TX12_SPKR_PROT_PATH_CFG0] = 0xa,
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[MSM_SDW_COMPANDER7_CTL0] = 0xb,
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[MSM_SDW_COMPANDER7_CTL1] = 0xb,
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[MSM_SDW_COMPANDER7_CTL2] = 0xb,
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[MSM_SDW_COMPANDER7_CTL3] = 0xb,
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[MSM_SDW_COMPANDER7_CTL4] = 0xb,
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[MSM_SDW_COMPANDER7_CTL5] = 0xb,
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[MSM_SDW_COMPANDER7_CTL6] = 0xb,
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[MSM_SDW_COMPANDER7_CTL7] = 0xb,
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[MSM_SDW_COMPANDER8_CTL0] = 0xb,
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[MSM_SDW_COMPANDER8_CTL1] = 0xb,
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[MSM_SDW_COMPANDER8_CTL2] = 0xb,
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[MSM_SDW_COMPANDER8_CTL3] = 0xb,
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[MSM_SDW_COMPANDER8_CTL4] = 0xb,
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[MSM_SDW_COMPANDER8_CTL5] = 0xb,
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[MSM_SDW_COMPANDER8_CTL6] = 0xb,
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[MSM_SDW_COMPANDER8_CTL7] = 0xb,
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[MSM_SDW_RX7_RX_PATH_CTL] = 0xb,
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[MSM_SDW_RX7_RX_PATH_CFG0] = 0xb,
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[MSM_SDW_RX7_RX_PATH_CFG1] = 0xb,
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[MSM_SDW_RX7_RX_PATH_CFG2] = 0xb,
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[MSM_SDW_RX7_RX_VOL_CTL] = 0xb,
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[MSM_SDW_RX7_RX_PATH_MIX_CTL] = 0xb,
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[MSM_SDW_RX7_RX_PATH_MIX_CFG] = 0xb,
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[MSM_SDW_RX7_RX_VOL_MIX_CTL] = 0xb,
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[MSM_SDW_RX7_RX_PATH_SEC0] = 0xb,
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[MSM_SDW_RX7_RX_PATH_SEC1] = 0xb,
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[MSM_SDW_RX7_RX_PATH_SEC2] = 0xb,
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[MSM_SDW_RX7_RX_PATH_SEC3] = 0xb,
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[MSM_SDW_RX7_RX_PATH_SEC5] = 0xb,
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[MSM_SDW_RX7_RX_PATH_SEC6] = 0xb,
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[MSM_SDW_RX7_RX_PATH_SEC7] = 0xb,
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[MSM_SDW_RX7_RX_PATH_MIX_SEC0] = 0xb,
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[MSM_SDW_RX7_RX_PATH_MIX_SEC1] = 0xb,
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[MSM_SDW_RX8_RX_PATH_CTL] = 0xb,
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[MSM_SDW_RX8_RX_PATH_CFG0] = 0xb,
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[MSM_SDW_RX8_RX_PATH_CFG1] = 0xb,
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[MSM_SDW_RX8_RX_PATH_CFG2] = 0xb,
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[MSM_SDW_RX8_RX_VOL_CTL] = 0xb,
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[MSM_SDW_RX8_RX_PATH_MIX_CTL] = 0xb,
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[MSM_SDW_RX8_RX_PATH_MIX_CFG] = 0xb,
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[MSM_SDW_RX8_RX_VOL_MIX_CTL] = 0xb,
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[MSM_SDW_RX8_RX_PATH_SEC0] = 0xb,
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[MSM_SDW_RX8_RX_PATH_SEC1] = 0xb,
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[MSM_SDW_RX8_RX_PATH_SEC2] = 0xb,
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[MSM_SDW_RX8_RX_PATH_SEC3] = 0xb,
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[MSM_SDW_RX8_RX_PATH_SEC5] = 0xb,
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[MSM_SDW_RX8_RX_PATH_SEC6] = 0xb,
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[MSM_SDW_RX8_RX_PATH_SEC7] = 0xb,
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[MSM_SDW_RX8_RX_PATH_MIX_SEC0] = 0xb,
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[MSM_SDW_RX8_RX_PATH_MIX_SEC1] = 0xb,
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[MSM_SDW_BOOST0_BOOST_PATH_CTL] = 0xc,
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[MSM_SDW_BOOST0_BOOST_CTL] = 0xc,
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[MSM_SDW_BOOST0_BOOST_CFG1] = 0xc,
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[MSM_SDW_BOOST0_BOOST_CFG2] = 0xc,
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[MSM_SDW_BOOST1_BOOST_PATH_CTL] = 0xc,
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[MSM_SDW_BOOST1_BOOST_CTL] = 0xc,
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[MSM_SDW_BOOST1_BOOST_CFG1] = 0xc,
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[MSM_SDW_BOOST1_BOOST_CFG2] = 0xc,
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[MSM_SDW_AHB_BRIDGE_WR_DATA_0] = 0xc,
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[MSM_SDW_AHB_BRIDGE_WR_DATA_1] = 0xc,
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[MSM_SDW_AHB_BRIDGE_WR_DATA_2] = 0xc,
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[MSM_SDW_AHB_BRIDGE_WR_DATA_3] = 0xc,
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[MSM_SDW_AHB_BRIDGE_WR_ADDR_0] = 0xc,
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[MSM_SDW_AHB_BRIDGE_WR_ADDR_1] = 0xc,
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[MSM_SDW_AHB_BRIDGE_WR_ADDR_2] = 0xc,
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[MSM_SDW_AHB_BRIDGE_WR_ADDR_3] = 0xc,
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[MSM_SDW_AHB_BRIDGE_RD_ADDR_0] = 0xc,
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[MSM_SDW_AHB_BRIDGE_RD_ADDR_1] = 0xc,
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[MSM_SDW_AHB_BRIDGE_RD_ADDR_2] = 0xc,
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[MSM_SDW_AHB_BRIDGE_RD_ADDR_3] = 0xc,
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[MSM_SDW_AHB_BRIDGE_RD_DATA_0] = 0xc,
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[MSM_SDW_AHB_BRIDGE_RD_DATA_1] = 0xc,
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[MSM_SDW_AHB_BRIDGE_RD_DATA_2] = 0xc,
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[MSM_SDW_AHB_BRIDGE_RD_DATA_3] = 0xc,
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[MSM_SDW_AHB_BRIDGE_ACCESS_CFG] = 0xc,
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[MSM_SDW_AHB_BRIDGE_ACCESS_STATUS] = 0xc,
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[MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL] = 0xd,
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[MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL] = 0xd,
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[MSM_SDW_CLK_RST_CTRL_SWR_CONTROL] = 0xd,
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[MSM_SDW_TOP_TOP_CFG0] = 0xd,
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[MSM_SDW_TOP_TOP_CFG1] = 0xd,
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[MSM_SDW_TOP_RX_I2S_CTL] = 0xd,
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[MSM_SDW_TOP_TX_I2S_CTL] = 0xd,
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[MSM_SDW_TOP_RX7_PATH_INPUT0_MUX] = 0xd,
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[MSM_SDW_TOP_RX7_PATH_INPUT1_MUX] = 0xd,
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[MSM_SDW_TOP_RX8_PATH_INPUT0_MUX] = 0xd,
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[MSM_SDW_TOP_RX8_PATH_INPUT1_MUX] = 0xd,
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[MSM_SDW_TOP_FREQ_MCLK] = 0xd,
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[MSM_SDW_TOP_DEBUG_BUS_SEL] = 0xd,
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[MSM_SDW_TOP_DEBUG_EN] = 0xd,
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[MSM_SDW_TOP_I2S_RESET] = 0xd,
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[MSM_SDW_TOP_BLOCKS_RESET] = 0xd,
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};
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const u8 msm_sdw_reg_readable[MSM_SDW_MAX_REGISTER] = {
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[MSM_SDW_PAGE_REGISTER] = 1,
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[MSM_SDW_TX9_SPKR_PROT_PATH_CTL] = 1,
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[MSM_SDW_TX9_SPKR_PROT_PATH_CFG0] = 1,
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[MSM_SDW_TX10_SPKR_PROT_PATH_CTL] = 1,
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[MSM_SDW_TX10_SPKR_PROT_PATH_CFG0] = 1,
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[MSM_SDW_TX11_SPKR_PROT_PATH_CTL] = 1,
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[MSM_SDW_TX11_SPKR_PROT_PATH_CFG0] = 1,
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[MSM_SDW_TX12_SPKR_PROT_PATH_CTL] = 1,
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[MSM_SDW_TX12_SPKR_PROT_PATH_CFG0] = 1,
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[MSM_SDW_COMPANDER7_CTL0] = 1,
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[MSM_SDW_COMPANDER7_CTL1] = 1,
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[MSM_SDW_COMPANDER7_CTL2] = 1,
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[MSM_SDW_COMPANDER7_CTL3] = 1,
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[MSM_SDW_COMPANDER7_CTL4] = 1,
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[MSM_SDW_COMPANDER7_CTL5] = 1,
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[MSM_SDW_COMPANDER7_CTL6] = 1,
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[MSM_SDW_COMPANDER7_CTL7] = 1,
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[MSM_SDW_COMPANDER8_CTL0] = 1,
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[MSM_SDW_COMPANDER8_CTL1] = 1,
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[MSM_SDW_COMPANDER8_CTL2] = 1,
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[MSM_SDW_COMPANDER8_CTL3] = 1,
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[MSM_SDW_COMPANDER8_CTL4] = 1,
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[MSM_SDW_COMPANDER8_CTL5] = 1,
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[MSM_SDW_COMPANDER8_CTL6] = 1,
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[MSM_SDW_COMPANDER8_CTL7] = 1,
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[MSM_SDW_RX7_RX_PATH_CTL] = 1,
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[MSM_SDW_RX7_RX_PATH_CFG0] = 1,
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[MSM_SDW_RX7_RX_PATH_CFG1] = 1,
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[MSM_SDW_RX7_RX_PATH_CFG2] = 1,
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[MSM_SDW_RX7_RX_VOL_CTL] = 1,
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[MSM_SDW_RX7_RX_PATH_MIX_CTL] = 1,
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[MSM_SDW_RX7_RX_PATH_MIX_CFG] = 1,
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[MSM_SDW_RX7_RX_VOL_MIX_CTL] = 1,
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[MSM_SDW_RX7_RX_PATH_SEC0] = 1,
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[MSM_SDW_RX7_RX_PATH_SEC1] = 1,
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[MSM_SDW_RX7_RX_PATH_SEC2] = 1,
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[MSM_SDW_RX7_RX_PATH_SEC3] = 1,
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[MSM_SDW_RX7_RX_PATH_SEC5] = 1,
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[MSM_SDW_RX7_RX_PATH_SEC6] = 1,
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[MSM_SDW_RX7_RX_PATH_SEC7] = 1,
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[MSM_SDW_RX7_RX_PATH_MIX_SEC0] = 1,
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[MSM_SDW_RX7_RX_PATH_MIX_SEC1] = 1,
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[MSM_SDW_RX8_RX_PATH_CTL] = 1,
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[MSM_SDW_RX8_RX_PATH_CFG0] = 1,
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[MSM_SDW_RX8_RX_PATH_CFG1] = 1,
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[MSM_SDW_RX8_RX_PATH_CFG2] = 1,
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[MSM_SDW_RX8_RX_VOL_CTL] = 1,
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[MSM_SDW_RX8_RX_PATH_MIX_CTL] = 1,
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[MSM_SDW_RX8_RX_PATH_MIX_CFG] = 1,
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[MSM_SDW_RX8_RX_VOL_MIX_CTL] = 1,
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[MSM_SDW_RX8_RX_PATH_SEC0] = 1,
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[MSM_SDW_RX8_RX_PATH_SEC1] = 1,
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[MSM_SDW_RX8_RX_PATH_SEC2] = 1,
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[MSM_SDW_RX8_RX_PATH_SEC3] = 1,
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[MSM_SDW_RX8_RX_PATH_SEC5] = 1,
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[MSM_SDW_RX8_RX_PATH_SEC6] = 1,
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[MSM_SDW_RX8_RX_PATH_SEC7] = 1,
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[MSM_SDW_RX8_RX_PATH_MIX_SEC0] = 1,
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[MSM_SDW_RX8_RX_PATH_MIX_SEC1] = 1,
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[MSM_SDW_BOOST0_BOOST_PATH_CTL] = 1,
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[MSM_SDW_BOOST0_BOOST_CTL] = 1,
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[MSM_SDW_BOOST0_BOOST_CFG1] = 1,
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[MSM_SDW_BOOST0_BOOST_CFG2] = 1,
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[MSM_SDW_BOOST1_BOOST_PATH_CTL] = 1,
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[MSM_SDW_BOOST1_BOOST_CTL] = 1,
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[MSM_SDW_BOOST1_BOOST_CFG1] = 1,
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[MSM_SDW_BOOST1_BOOST_CFG2] = 1,
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[MSM_SDW_AHB_BRIDGE_WR_DATA_0] = 1,
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[MSM_SDW_AHB_BRIDGE_WR_DATA_1] = 1,
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[MSM_SDW_AHB_BRIDGE_WR_DATA_2] = 1,
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[MSM_SDW_AHB_BRIDGE_WR_DATA_3] = 1,
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[MSM_SDW_AHB_BRIDGE_WR_ADDR_0] = 1,
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[MSM_SDW_AHB_BRIDGE_WR_ADDR_1] = 1,
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[MSM_SDW_AHB_BRIDGE_WR_ADDR_2] = 1,
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[MSM_SDW_AHB_BRIDGE_WR_ADDR_3] = 1,
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[MSM_SDW_AHB_BRIDGE_RD_ADDR_0] = 1,
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[MSM_SDW_AHB_BRIDGE_RD_ADDR_1] = 1,
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[MSM_SDW_AHB_BRIDGE_RD_ADDR_2] = 1,
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[MSM_SDW_AHB_BRIDGE_RD_ADDR_3] = 1,
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[MSM_SDW_AHB_BRIDGE_RD_DATA_0] = 1,
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[MSM_SDW_AHB_BRIDGE_RD_DATA_1] = 1,
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[MSM_SDW_AHB_BRIDGE_RD_DATA_2] = 1,
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[MSM_SDW_AHB_BRIDGE_RD_DATA_3] = 1,
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[MSM_SDW_AHB_BRIDGE_ACCESS_CFG] = 1,
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[MSM_SDW_AHB_BRIDGE_ACCESS_STATUS] = 1,
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[MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL] = 1,
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[MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL] = 1,
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[MSM_SDW_CLK_RST_CTRL_SWR_CONTROL] = 1,
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[MSM_SDW_TOP_TOP_CFG0] = 1,
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[MSM_SDW_TOP_TOP_CFG1] = 1,
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[MSM_SDW_TOP_RX_I2S_CTL] = 1,
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[MSM_SDW_TOP_TX_I2S_CTL] = 1,
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[MSM_SDW_TOP_RX7_PATH_INPUT0_MUX] = 1,
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[MSM_SDW_TOP_RX7_PATH_INPUT1_MUX] = 1,
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[MSM_SDW_TOP_RX8_PATH_INPUT0_MUX] = 1,
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[MSM_SDW_TOP_RX8_PATH_INPUT1_MUX] = 1,
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[MSM_SDW_TOP_FREQ_MCLK] = 1,
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[MSM_SDW_TOP_DEBUG_BUS_SEL] = 1,
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[MSM_SDW_TOP_DEBUG_EN] = 1,
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[MSM_SDW_TOP_I2S_RESET] = 1,
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[MSM_SDW_TOP_BLOCKS_RESET] = 1,
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};
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166
sound/soc/codecs/msm_sdw/msm_sdw.h
Normal file
166
sound/soc/codecs/msm_sdw/msm_sdw.h
Normal file
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@ -0,0 +1,166 @@
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef MSM_SDW_H
|
||||
#define MSM_SDW_H
|
||||
|
||||
#include <sound/soc.h>
|
||||
#include <sound/q6afe-v2.h>
|
||||
#include "msm_sdw_registers.h"
|
||||
|
||||
#define MSM_SDW_MAX_REGISTER 0x400
|
||||
|
||||
extern const struct regmap_config msm_sdw_regmap_config;
|
||||
extern const u8 msm_sdw_page_map[MSM_SDW_MAX_REGISTER];
|
||||
extern const u8 msm_sdw_reg_readable[MSM_SDW_MAX_REGISTER];
|
||||
|
||||
enum {
|
||||
MSM_SDW_RX4 = 0,
|
||||
MSM_SDW_RX5,
|
||||
MSM_SDW_RX_MAX,
|
||||
};
|
||||
|
||||
enum {
|
||||
MSM_SDW_TX0 = 0,
|
||||
MSM_SDW_TX1,
|
||||
MSM_SDW_TX_MAX,
|
||||
};
|
||||
|
||||
enum {
|
||||
COMP1, /* SPK_L */
|
||||
COMP2, /* SPK_R */
|
||||
COMP_MAX
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure used to update codec
|
||||
* register defaults after reset
|
||||
*/
|
||||
struct msm_sdw_reg_mask_val {
|
||||
u16 reg;
|
||||
u8 mask;
|
||||
u8 val;
|
||||
};
|
||||
|
||||
/*
|
||||
* Selects compander and smart boost settings
|
||||
* for a given speaker mode
|
||||
*/
|
||||
enum {
|
||||
SPKR_MODE_DEFAULT,
|
||||
SPKR_MODE_1, /* COMP Gain = 12dB, Smartboost Max = 5.5V */
|
||||
};
|
||||
|
||||
/* Rx path gain offsets */
|
||||
enum {
|
||||
RX_GAIN_OFFSET_M1P5_DB,
|
||||
RX_GAIN_OFFSET_0_DB,
|
||||
};
|
||||
|
||||
struct msm_sdw_reg_val {
|
||||
unsigned short reg; /* register address */
|
||||
u8 *buf; /* buffer to be written to reg. addr */
|
||||
int bytes; /* number of bytes to be written */
|
||||
};
|
||||
|
||||
/* Hold instance to soundwire platform device */
|
||||
struct msm_sdw_ctrl_data {
|
||||
struct platform_device *sdw_pdev;
|
||||
};
|
||||
|
||||
struct wcd_sdw_ctrl_platform_data {
|
||||
void *handle; /* holds codec private data */
|
||||
int (*read)(void *handle, int reg);
|
||||
int (*write)(void *handle, int reg, int val);
|
||||
int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
|
||||
int (*clk)(void *handle, bool enable);
|
||||
int (*handle_irq)(void *handle,
|
||||
irqreturn_t (*swrm_irq_handler)(int irq,
|
||||
void *data),
|
||||
void *swrm_handle,
|
||||
int action);
|
||||
};
|
||||
|
||||
struct msm_sdw_priv {
|
||||
struct device *dev;
|
||||
struct mutex io_lock;
|
||||
|
||||
int (*read_dev)(struct msm_sdw_priv *msm_sdw, unsigned short reg,
|
||||
int bytes, void *dest);
|
||||
int (*write_dev)(struct msm_sdw_priv *msm_sdw, unsigned short reg,
|
||||
int bytes, void *src);
|
||||
int (*multi_reg_write)(struct msm_sdw_priv *msm_sdw, const void *data,
|
||||
size_t count);
|
||||
struct snd_soc_codec *codec;
|
||||
/* SoundWire data structure */
|
||||
struct msm_sdw_ctrl_data *sdw_ctrl_data;
|
||||
int nr;
|
||||
|
||||
/* compander */
|
||||
int comp_enabled[COMP_MAX];
|
||||
int ear_spkr_gain;
|
||||
|
||||
/* to track the status */
|
||||
unsigned long status_mask;
|
||||
|
||||
struct work_struct msm_sdw_add_child_devices_work;
|
||||
struct wcd_sdw_ctrl_platform_data sdw_plat_data;
|
||||
|
||||
unsigned int vi_feed_value;
|
||||
|
||||
struct mutex sdw_read_lock;
|
||||
struct mutex sdw_write_lock;
|
||||
struct mutex sdw_clk_lock;
|
||||
int sdw_clk_users;
|
||||
|
||||
int sdw_irq;
|
||||
int int_mclk1_rsc_ref;
|
||||
bool int_mclk1_enabled;
|
||||
bool sdw_npl_clk_enabled;
|
||||
struct mutex cdc_int_mclk1_mutex;
|
||||
struct mutex sdw_npl_clk_mutex;
|
||||
struct delayed_work disable_int_mclk1_work;
|
||||
struct afe_clk_set sdw_cdc_core_clk;
|
||||
struct afe_clk_set sdw_npl_clk;
|
||||
struct notifier_block service_nb;
|
||||
int (*sdw_cdc_gpio_fn)(bool enable, struct snd_soc_codec *codec);
|
||||
bool dev_up;
|
||||
|
||||
int spkr_gain_offset;
|
||||
int spkr_mode;
|
||||
struct mutex codec_mutex;
|
||||
int rx_4_count;
|
||||
int rx_5_count;
|
||||
u32 mclk_rate;
|
||||
struct regmap *regmap;
|
||||
|
||||
bool prev_pg_valid;
|
||||
u8 prev_pg;
|
||||
u32 sdw_base_addr;
|
||||
char __iomem *sdw_base;
|
||||
u32 version;
|
||||
|
||||
/* Entry for version info */
|
||||
struct snd_info_entry *entry;
|
||||
struct snd_info_entry *version_entry;
|
||||
};
|
||||
|
||||
extern int msm_sdw_set_spkr_mode(struct snd_soc_codec *codec, int mode);
|
||||
extern int msm_sdw_set_spkr_gain_offset(struct snd_soc_codec *codec,
|
||||
int offset);
|
||||
extern void msm_sdw_gpio_cb(
|
||||
int (*sdw_cdc_gpio_fn)(bool enable, struct snd_soc_codec *codec),
|
||||
struct snd_soc_codec *codec);
|
||||
extern struct regmap *msm_sdw_regmap_init(struct device *dev,
|
||||
const struct regmap_config *config);
|
||||
extern int msm_sdw_codec_info_create_codec_entry(struct snd_info_entry *,
|
||||
struct snd_soc_codec *);
|
||||
#endif
|
||||
1920
sound/soc/codecs/msm_sdw/msm_sdw_cdc.c
Normal file
1920
sound/soc/codecs/msm_sdw/msm_sdw_cdc.c
Normal file
File diff suppressed because it is too large
Load diff
211
sound/soc/codecs/msm_sdw/msm_sdw_cdc_utils.c
Normal file
211
sound/soc/codecs/msm_sdw/msm_sdw_cdc_utils.c
Normal file
|
|
@ -0,0 +1,211 @@
|
|||
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/regmap.h>
|
||||
#include "msm_sdw.h"
|
||||
|
||||
#define REG_BYTES 2
|
||||
#define VAL_BYTES 1
|
||||
/*
|
||||
* Page Register Address that APP Proc uses to
|
||||
* access WCD9335 Codec registers is identified
|
||||
* as 0x00
|
||||
*/
|
||||
#define PAGE_REG_ADDR 0x00
|
||||
|
||||
/*
|
||||
* msm_sdw_page_write:
|
||||
* Retrieve page number from register and
|
||||
* write that page number to the page address.
|
||||
* Called under io_lock acquisition.
|
||||
*
|
||||
* @msm_sdw: pointer to msm_sdw
|
||||
* @reg: Register address from which page number is retrieved
|
||||
*
|
||||
* Returns 0 for success and negative error code for failure.
|
||||
*/
|
||||
int msm_sdw_page_write(struct msm_sdw_priv *msm_sdw, unsigned short reg)
|
||||
{
|
||||
int ret = 0;
|
||||
u8 pg_num, prev_pg_num;
|
||||
|
||||
pg_num = msm_sdw_page_map[reg];
|
||||
if (msm_sdw->prev_pg_valid) {
|
||||
prev_pg_num = msm_sdw->prev_pg;
|
||||
if (prev_pg_num != pg_num) {
|
||||
ret = msm_sdw->write_dev(msm_sdw, PAGE_REG_ADDR, 1,
|
||||
(void *) &pg_num);
|
||||
if (ret < 0) {
|
||||
dev_err(msm_sdw->dev,
|
||||
"page write error, pg_num: 0x%x\n",
|
||||
pg_num);
|
||||
} else {
|
||||
msm_sdw->prev_pg = pg_num;
|
||||
dev_dbg(msm_sdw->dev,
|
||||
"%s: Page 0x%x Write to 0x00\n",
|
||||
__func__, pg_num);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
ret = msm_sdw->write_dev(msm_sdw, PAGE_REG_ADDR, 1,
|
||||
(void *) &pg_num);
|
||||
if (ret < 0) {
|
||||
dev_err(msm_sdw->dev,
|
||||
"page write error, pg_num: 0x%x\n", pg_num);
|
||||
} else {
|
||||
msm_sdw->prev_pg = pg_num;
|
||||
msm_sdw->prev_pg_valid = true;
|
||||
dev_dbg(msm_sdw->dev, "%s: Page 0x%x Write to 0x00\n",
|
||||
__func__, pg_num);
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(msm_sdw_page_write);
|
||||
|
||||
static int regmap_bus_read(void *context, const void *reg, size_t reg_size,
|
||||
void *val, size_t val_size)
|
||||
{
|
||||
struct device *dev = context;
|
||||
struct msm_sdw_priv *msm_sdw = dev_get_drvdata(dev);
|
||||
unsigned short c_reg;
|
||||
int ret, i;
|
||||
|
||||
if (!msm_sdw) {
|
||||
dev_err(dev, "%s: msm_sdw is NULL\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (!reg || !val) {
|
||||
dev_err(dev, "%s: reg or val is NULL\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (reg_size != REG_BYTES) {
|
||||
dev_err(dev, "%s: register size %zd bytes, not supported\n",
|
||||
__func__, reg_size);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (!msm_sdw->dev_up) {
|
||||
dev_dbg_ratelimited(dev, "%s: No read allowed. dev_up = %d\n",
|
||||
__func__, msm_sdw->dev_up);
|
||||
return 0;
|
||||
}
|
||||
|
||||
mutex_lock(&msm_sdw->io_lock);
|
||||
c_reg = *(u16 *)reg;
|
||||
ret = msm_sdw_page_write(msm_sdw, c_reg);
|
||||
if (ret)
|
||||
goto err;
|
||||
ret = msm_sdw->read_dev(msm_sdw, c_reg, val_size, val);
|
||||
if (ret < 0)
|
||||
dev_err(dev, "%s: Codec read failed (%d), reg: 0x%x, size:%zd\n",
|
||||
__func__, ret, c_reg, val_size);
|
||||
else {
|
||||
for (i = 0; i < val_size; i++)
|
||||
dev_dbg(dev, "%s: Read 0x%02x from 0x%x\n",
|
||||
__func__, ((u8 *)val)[i], c_reg + i);
|
||||
}
|
||||
err:
|
||||
mutex_unlock(&msm_sdw->io_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int regmap_bus_gather_write(void *context,
|
||||
const void *reg, size_t reg_size,
|
||||
const void *val, size_t val_size)
|
||||
{
|
||||
struct device *dev = context;
|
||||
struct msm_sdw_priv *msm_sdw = dev_get_drvdata(dev);
|
||||
unsigned short c_reg;
|
||||
int ret, i;
|
||||
|
||||
if (!msm_sdw) {
|
||||
dev_err(dev, "%s: msm_sdw is NULL\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (!reg || !val) {
|
||||
dev_err(dev, "%s: reg or val is NULL\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (reg_size != REG_BYTES) {
|
||||
dev_err(dev, "%s: register size %zd bytes, not supported\n",
|
||||
__func__, reg_size);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (!msm_sdw->dev_up) {
|
||||
dev_dbg_ratelimited(dev, "%s: No write allowed. dev_up = %d\n",
|
||||
__func__, msm_sdw->dev_up);
|
||||
return 0;
|
||||
}
|
||||
|
||||
mutex_lock(&msm_sdw->io_lock);
|
||||
c_reg = *(u16 *)reg;
|
||||
ret = msm_sdw_page_write(msm_sdw, c_reg);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
for (i = 0; i < val_size; i++)
|
||||
dev_dbg(dev, "Write %02x to 0x%x\n", ((u8 *)val)[i],
|
||||
c_reg + i*4);
|
||||
|
||||
ret = msm_sdw->write_dev(msm_sdw, c_reg, val_size, (void *) val);
|
||||
if (ret < 0)
|
||||
dev_err(dev,
|
||||
"%s: Codec write failed (%d), reg:0x%x, size:%zd\n",
|
||||
__func__, ret, c_reg, val_size);
|
||||
|
||||
err:
|
||||
mutex_unlock(&msm_sdw->io_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int regmap_bus_write(void *context, const void *data, size_t count)
|
||||
{
|
||||
struct device *dev = context;
|
||||
struct msm_sdw_priv *msm_sdw = dev_get_drvdata(dev);
|
||||
|
||||
if (!msm_sdw)
|
||||
return -EINVAL;
|
||||
|
||||
WARN_ON(count < REG_BYTES);
|
||||
|
||||
return regmap_bus_gather_write(context, data, REG_BYTES,
|
||||
data + REG_BYTES,
|
||||
count - REG_BYTES);
|
||||
|
||||
}
|
||||
|
||||
static struct regmap_bus regmap_bus_config = {
|
||||
.write = regmap_bus_write,
|
||||
.gather_write = regmap_bus_gather_write,
|
||||
.read = regmap_bus_read,
|
||||
.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
|
||||
.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
|
||||
};
|
||||
|
||||
/*
|
||||
* msm_sdw_regmap_init:
|
||||
* Initialize msm_sdw register map
|
||||
*
|
||||
* @dev: pointer to wcd device
|
||||
* @config: pointer to register map config
|
||||
*
|
||||
* Returns pointer to regmap structure for success
|
||||
* or NULL in case of failure.
|
||||
*/
|
||||
struct regmap *msm_sdw_regmap_init(struct device *dev,
|
||||
const struct regmap_config *config)
|
||||
{
|
||||
return devm_regmap_init(dev, ®map_bus_config, dev, config);
|
||||
}
|
||||
EXPORT_SYMBOL(msm_sdw_regmap_init);
|
||||
126
sound/soc/codecs/msm_sdw/msm_sdw_registers.h
Normal file
126
sound/soc/codecs/msm_sdw/msm_sdw_registers.h
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef MSM_SDW_REGISTERS_H
|
||||
#define MSM_SDW_REGISTERS_H
|
||||
|
||||
#define MSM_SDW_PAGE_REGISTER 0x0000
|
||||
|
||||
/* Page-A Registers */
|
||||
#define MSM_SDW_TX9_SPKR_PROT_PATH_CTL 0x0308
|
||||
#define MSM_SDW_TX9_SPKR_PROT_PATH_CFG0 0x030c
|
||||
#define MSM_SDW_TX10_SPKR_PROT_PATH_CTL 0x0318
|
||||
#define MSM_SDW_TX10_SPKR_PROT_PATH_CFG0 0x031c
|
||||
#define MSM_SDW_TX11_SPKR_PROT_PATH_CTL 0x0328
|
||||
#define MSM_SDW_TX11_SPKR_PROT_PATH_CFG0 0x032c
|
||||
#define MSM_SDW_TX12_SPKR_PROT_PATH_CTL 0x0338
|
||||
#define MSM_SDW_TX12_SPKR_PROT_PATH_CFG0 0x033c
|
||||
|
||||
/* Page-B Registers */
|
||||
#define MSM_SDW_COMPANDER7_CTL0 0x0024
|
||||
#define MSM_SDW_COMPANDER7_CTL1 0x0028
|
||||
#define MSM_SDW_COMPANDER7_CTL2 0x002c
|
||||
#define MSM_SDW_COMPANDER7_CTL3 0x0030
|
||||
#define MSM_SDW_COMPANDER7_CTL4 0x0034
|
||||
#define MSM_SDW_COMPANDER7_CTL5 0x0038
|
||||
#define MSM_SDW_COMPANDER7_CTL6 0x003c
|
||||
#define MSM_SDW_COMPANDER7_CTL7 0x0040
|
||||
#define MSM_SDW_COMPANDER8_CTL0 0x0044
|
||||
#define MSM_SDW_COMPANDER8_CTL1 0x0048
|
||||
#define MSM_SDW_COMPANDER8_CTL2 0x004c
|
||||
#define MSM_SDW_COMPANDER8_CTL3 0x0050
|
||||
#define MSM_SDW_COMPANDER8_CTL4 0x0054
|
||||
#define MSM_SDW_COMPANDER8_CTL5 0x0058
|
||||
#define MSM_SDW_COMPANDER8_CTL6 0x005c
|
||||
#define MSM_SDW_COMPANDER8_CTL7 0x0060
|
||||
#define MSM_SDW_RX7_RX_PATH_CTL 0x01a4
|
||||
#define MSM_SDW_RX7_RX_PATH_CFG0 0x01a8
|
||||
#define MSM_SDW_RX7_RX_PATH_CFG1 0x01ac
|
||||
#define MSM_SDW_RX7_RX_PATH_CFG2 0x01b0
|
||||
#define MSM_SDW_RX7_RX_VOL_CTL 0x01b4
|
||||
#define MSM_SDW_RX7_RX_PATH_MIX_CTL 0x01b8
|
||||
#define MSM_SDW_RX7_RX_PATH_MIX_CFG 0x01bc
|
||||
#define MSM_SDW_RX7_RX_VOL_MIX_CTL 0x01c0
|
||||
#define MSM_SDW_RX7_RX_PATH_SEC0 0x01c4
|
||||
#define MSM_SDW_RX7_RX_PATH_SEC1 0x01c8
|
||||
#define MSM_SDW_RX7_RX_PATH_SEC2 0x01cc
|
||||
#define MSM_SDW_RX7_RX_PATH_SEC3 0x01d0
|
||||
#define MSM_SDW_RX7_RX_PATH_SEC5 0x01d8
|
||||
#define MSM_SDW_RX7_RX_PATH_SEC6 0x01dc
|
||||
#define MSM_SDW_RX7_RX_PATH_SEC7 0x01e0
|
||||
#define MSM_SDW_RX7_RX_PATH_MIX_SEC0 0x01e4
|
||||
#define MSM_SDW_RX7_RX_PATH_MIX_SEC1 0x01e8
|
||||
#define MSM_SDW_RX8_RX_PATH_CTL 0x0384
|
||||
#define MSM_SDW_RX8_RX_PATH_CFG0 0x0388
|
||||
#define MSM_SDW_RX8_RX_PATH_CFG1 0x038c
|
||||
#define MSM_SDW_RX8_RX_PATH_CFG2 0x0390
|
||||
#define MSM_SDW_RX8_RX_VOL_CTL 0x0394
|
||||
#define MSM_SDW_RX8_RX_PATH_MIX_CTL 0x0398
|
||||
#define MSM_SDW_RX8_RX_PATH_MIX_CFG 0x039c
|
||||
#define MSM_SDW_RX8_RX_VOL_MIX_CTL 0x03a0
|
||||
#define MSM_SDW_RX8_RX_PATH_SEC0 0x03a4
|
||||
#define MSM_SDW_RX8_RX_PATH_SEC1 0x03a8
|
||||
#define MSM_SDW_RX8_RX_PATH_SEC2 0x03ac
|
||||
#define MSM_SDW_RX8_RX_PATH_SEC3 0x03b0
|
||||
#define MSM_SDW_RX8_RX_PATH_SEC5 0x03b8
|
||||
#define MSM_SDW_RX8_RX_PATH_SEC6 0x03bc
|
||||
#define MSM_SDW_RX8_RX_PATH_SEC7 0x03c0
|
||||
#define MSM_SDW_RX8_RX_PATH_MIX_SEC0 0x03c4
|
||||
#define MSM_SDW_RX8_RX_PATH_MIX_SEC1 0x03c8
|
||||
|
||||
/* Page-C Registers */
|
||||
#define MSM_SDW_BOOST0_BOOST_PATH_CTL 0x0064
|
||||
#define MSM_SDW_BOOST0_BOOST_CTL 0x0068
|
||||
#define MSM_SDW_BOOST0_BOOST_CFG1 0x006c
|
||||
#define MSM_SDW_BOOST0_BOOST_CFG2 0x0070
|
||||
#define MSM_SDW_BOOST1_BOOST_PATH_CTL 0x0084
|
||||
#define MSM_SDW_BOOST1_BOOST_CTL 0x0088
|
||||
#define MSM_SDW_BOOST1_BOOST_CFG1 0x008c
|
||||
#define MSM_SDW_BOOST1_BOOST_CFG2 0x0090
|
||||
#define MSM_SDW_AHB_BRIDGE_WR_DATA_0 0x00a4
|
||||
#define MSM_SDW_AHB_BRIDGE_WR_DATA_1 0x00a8
|
||||
#define MSM_SDW_AHB_BRIDGE_WR_DATA_2 0x00ac
|
||||
#define MSM_SDW_AHB_BRIDGE_WR_DATA_3 0x00b0
|
||||
#define MSM_SDW_AHB_BRIDGE_WR_ADDR_0 0x00b4
|
||||
#define MSM_SDW_AHB_BRIDGE_WR_ADDR_1 0x00b8
|
||||
#define MSM_SDW_AHB_BRIDGE_WR_ADDR_2 0x00bc
|
||||
#define MSM_SDW_AHB_BRIDGE_WR_ADDR_3 0x00c0
|
||||
#define MSM_SDW_AHB_BRIDGE_RD_ADDR_0 0x00c4
|
||||
#define MSM_SDW_AHB_BRIDGE_RD_ADDR_1 0x00c8
|
||||
#define MSM_SDW_AHB_BRIDGE_RD_ADDR_2 0x00cc
|
||||
#define MSM_SDW_AHB_BRIDGE_RD_ADDR_3 0x00d0
|
||||
#define MSM_SDW_AHB_BRIDGE_RD_DATA_0 0x00d4
|
||||
#define MSM_SDW_AHB_BRIDGE_RD_DATA_1 0x00d8
|
||||
#define MSM_SDW_AHB_BRIDGE_RD_DATA_2 0x00dc
|
||||
#define MSM_SDW_AHB_BRIDGE_RD_DATA_3 0x00e0
|
||||
#define MSM_SDW_AHB_BRIDGE_ACCESS_CFG 0x00e4
|
||||
#define MSM_SDW_AHB_BRIDGE_ACCESS_STATUS 0x00e8
|
||||
|
||||
/* Page-D Registers */
|
||||
#define MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL 0x0104
|
||||
#define MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL 0x0108
|
||||
#define MSM_SDW_CLK_RST_CTRL_SWR_CONTROL 0x010c
|
||||
#define MSM_SDW_TOP_TOP_CFG0 0x0204
|
||||
#define MSM_SDW_TOP_TOP_CFG1 0x0208
|
||||
#define MSM_SDW_TOP_RX_I2S_CTL 0x020c
|
||||
#define MSM_SDW_TOP_TX_I2S_CTL 0x0210
|
||||
#define MSM_SDW_TOP_I2S_CLK 0x0214
|
||||
#define MSM_SDW_TOP_RX7_PATH_INPUT0_MUX 0x0218
|
||||
#define MSM_SDW_TOP_RX7_PATH_INPUT1_MUX 0x021c
|
||||
#define MSM_SDW_TOP_RX8_PATH_INPUT0_MUX 0x0220
|
||||
#define MSM_SDW_TOP_RX8_PATH_INPUT1_MUX 0x0224
|
||||
#define MSM_SDW_TOP_FREQ_MCLK 0x0228
|
||||
#define MSM_SDW_TOP_DEBUG_BUS_SEL 0x022c
|
||||
#define MSM_SDW_TOP_DEBUG_EN 0x0230
|
||||
#define MSM_SDW_TOP_I2S_RESET 0x0234
|
||||
#define MSM_SDW_TOP_BLOCKS_RESET 0x0238
|
||||
|
||||
#endif
|
||||
155
sound/soc/codecs/msm_sdw/msm_sdw_regmap.c
Normal file
155
sound/soc/codecs/msm_sdw/msm_sdw_regmap.c
Normal file
|
|
@ -0,0 +1,155 @@
|
|||
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/regmap.h>
|
||||
#include "msm_sdw.h"
|
||||
|
||||
static const struct reg_default msm_sdw_defaults[] = {
|
||||
/* Page #10 registers */
|
||||
{ MSM_SDW_PAGE_REGISTER, 0x00 },
|
||||
{ MSM_SDW_TX9_SPKR_PROT_PATH_CTL, 0x02 },
|
||||
{ MSM_SDW_TX9_SPKR_PROT_PATH_CFG0, 0x00 },
|
||||
{ MSM_SDW_TX10_SPKR_PROT_PATH_CTL, 0x02 },
|
||||
{ MSM_SDW_TX10_SPKR_PROT_PATH_CFG0, 0x00 },
|
||||
{ MSM_SDW_TX11_SPKR_PROT_PATH_CTL, 0x02 },
|
||||
{ MSM_SDW_TX11_SPKR_PROT_PATH_CFG0, 0x00 },
|
||||
{ MSM_SDW_TX12_SPKR_PROT_PATH_CTL, 0x02 },
|
||||
{ MSM_SDW_TX12_SPKR_PROT_PATH_CFG0, 0x00 },
|
||||
/* Page #11 registers */
|
||||
{ MSM_SDW_COMPANDER7_CTL0, 0x60 },
|
||||
{ MSM_SDW_COMPANDER7_CTL1, 0xdb },
|
||||
{ MSM_SDW_COMPANDER7_CTL2, 0xff },
|
||||
{ MSM_SDW_COMPANDER7_CTL3, 0x35 },
|
||||
{ MSM_SDW_COMPANDER7_CTL4, 0xff },
|
||||
{ MSM_SDW_COMPANDER7_CTL5, 0x00 },
|
||||
{ MSM_SDW_COMPANDER7_CTL6, 0x01 },
|
||||
{ MSM_SDW_COMPANDER8_CTL0, 0x60 },
|
||||
{ MSM_SDW_COMPANDER8_CTL1, 0xdb },
|
||||
{ MSM_SDW_COMPANDER8_CTL2, 0xff },
|
||||
{ MSM_SDW_COMPANDER8_CTL3, 0x35 },
|
||||
{ MSM_SDW_COMPANDER8_CTL4, 0xff },
|
||||
{ MSM_SDW_COMPANDER8_CTL5, 0x00 },
|
||||
{ MSM_SDW_COMPANDER8_CTL6, 0x01 },
|
||||
{ MSM_SDW_RX7_RX_PATH_CTL, 0x04 },
|
||||
{ MSM_SDW_RX7_RX_PATH_CFG0, 0x00 },
|
||||
{ MSM_SDW_RX7_RX_PATH_CFG2, 0x8f },
|
||||
{ MSM_SDW_RX7_RX_VOL_CTL, 0x00 },
|
||||
{ MSM_SDW_RX7_RX_PATH_MIX_CTL, 0x04 },
|
||||
{ MSM_SDW_RX7_RX_VOL_MIX_CTL, 0x00 },
|
||||
{ MSM_SDW_RX7_RX_PATH_SEC2, 0x00 },
|
||||
{ MSM_SDW_RX7_RX_PATH_SEC3, 0x00 },
|
||||
{ MSM_SDW_RX7_RX_PATH_SEC5, 0x00 },
|
||||
{ MSM_SDW_RX7_RX_PATH_SEC6, 0x00 },
|
||||
{ MSM_SDW_RX7_RX_PATH_SEC7, 0x00 },
|
||||
{ MSM_SDW_RX7_RX_PATH_MIX_SEC1, 0x00 },
|
||||
{ MSM_SDW_RX8_RX_PATH_CTL, 0x04 },
|
||||
{ MSM_SDW_RX8_RX_PATH_CFG0, 0x00 },
|
||||
{ MSM_SDW_RX8_RX_PATH_CFG2, 0x8f },
|
||||
{ MSM_SDW_RX8_RX_VOL_CTL, 0x00 },
|
||||
{ MSM_SDW_RX8_RX_PATH_MIX_CTL, 0x04 },
|
||||
{ MSM_SDW_RX8_RX_VOL_MIX_CTL, 0x00 },
|
||||
{ MSM_SDW_RX8_RX_PATH_SEC2, 0x00 },
|
||||
{ MSM_SDW_RX8_RX_PATH_SEC3, 0x00 },
|
||||
{ MSM_SDW_RX8_RX_PATH_SEC5, 0x00 },
|
||||
{ MSM_SDW_RX8_RX_PATH_SEC6, 0x00 },
|
||||
{ MSM_SDW_RX8_RX_PATH_SEC7, 0x00 },
|
||||
{ MSM_SDW_RX8_RX_PATH_MIX_SEC1, 0x00 },
|
||||
/* Page #12 registers */
|
||||
{ MSM_SDW_BOOST0_BOOST_PATH_CTL, 0x00 },
|
||||
{ MSM_SDW_BOOST0_BOOST_CTL, 0xb2 },
|
||||
{ MSM_SDW_BOOST0_BOOST_CFG1, 0x00 },
|
||||
{ MSM_SDW_BOOST0_BOOST_CFG2, 0x00 },
|
||||
{ MSM_SDW_BOOST1_BOOST_PATH_CTL, 0x00 },
|
||||
{ MSM_SDW_BOOST1_BOOST_CTL, 0xb2 },
|
||||
{ MSM_SDW_BOOST1_BOOST_CFG1, 0x00 },
|
||||
{ MSM_SDW_BOOST1_BOOST_CFG2, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_WR_DATA_0, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_WR_DATA_1, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_WR_DATA_2, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_WR_DATA_3, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_WR_ADDR_0, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_WR_ADDR_1, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_WR_ADDR_2, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_WR_ADDR_3, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_RD_ADDR_0, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_RD_ADDR_1, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_RD_ADDR_2, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_RD_ADDR_3, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_RD_DATA_0, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_RD_DATA_1, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_RD_DATA_2, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_RD_DATA_3, 0x00 },
|
||||
{ MSM_SDW_AHB_BRIDGE_ACCESS_CFG, 0x0f },
|
||||
{ MSM_SDW_AHB_BRIDGE_ACCESS_STATUS, 0x03 },
|
||||
/* Page #13 registers */
|
||||
{ MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
|
||||
{ MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
|
||||
{ MSM_SDW_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
|
||||
{ MSM_SDW_TOP_TOP_CFG0, 0x00 },
|
||||
{ MSM_SDW_TOP_TOP_CFG1, 0x00 },
|
||||
{ MSM_SDW_TOP_RX_I2S_CTL, 0x0C },
|
||||
{ MSM_SDW_TOP_TX_I2S_CTL, 0x00 },
|
||||
{ MSM_SDW_TOP_I2S_CLK, 0x00 },
|
||||
{ MSM_SDW_TOP_RX7_PATH_INPUT0_MUX, 0x00 },
|
||||
{ MSM_SDW_TOP_RX7_PATH_INPUT1_MUX, 0x00 },
|
||||
{ MSM_SDW_TOP_RX8_PATH_INPUT0_MUX, 0x00 },
|
||||
{ MSM_SDW_TOP_RX8_PATH_INPUT1_MUX, 0x00 },
|
||||
{ MSM_SDW_TOP_FREQ_MCLK, 0x00 },
|
||||
{ MSM_SDW_TOP_DEBUG_BUS_SEL, 0x00 },
|
||||
{ MSM_SDW_TOP_DEBUG_EN, 0x00 },
|
||||
{ MSM_SDW_TOP_I2S_RESET, 0x00 },
|
||||
{ MSM_SDW_TOP_BLOCKS_RESET, 0x00 },
|
||||
};
|
||||
|
||||
static bool msm_sdw_is_readable_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
return msm_sdw_reg_readable[reg];
|
||||
}
|
||||
|
||||
static bool msm_sdw_is_volatile_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case MSM_SDW_AHB_BRIDGE_WR_DATA_0:
|
||||
case MSM_SDW_AHB_BRIDGE_WR_DATA_1:
|
||||
case MSM_SDW_AHB_BRIDGE_WR_DATA_2:
|
||||
case MSM_SDW_AHB_BRIDGE_WR_DATA_3:
|
||||
case MSM_SDW_AHB_BRIDGE_WR_ADDR_0:
|
||||
case MSM_SDW_AHB_BRIDGE_WR_ADDR_1:
|
||||
case MSM_SDW_AHB_BRIDGE_WR_ADDR_2:
|
||||
case MSM_SDW_AHB_BRIDGE_WR_ADDR_3:
|
||||
case MSM_SDW_AHB_BRIDGE_RD_DATA_0:
|
||||
case MSM_SDW_AHB_BRIDGE_RD_DATA_1:
|
||||
case MSM_SDW_AHB_BRIDGE_RD_DATA_2:
|
||||
case MSM_SDW_AHB_BRIDGE_RD_DATA_3:
|
||||
case MSM_SDW_AHB_BRIDGE_RD_ADDR_0:
|
||||
case MSM_SDW_AHB_BRIDGE_RD_ADDR_1:
|
||||
case MSM_SDW_AHB_BRIDGE_RD_ADDR_2:
|
||||
case MSM_SDW_AHB_BRIDGE_RD_ADDR_3:
|
||||
case MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL:
|
||||
case MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
const struct regmap_config msm_sdw_regmap_config = {
|
||||
.reg_bits = 16,
|
||||
.val_bits = 8,
|
||||
.reg_stride = 4,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
.reg_defaults = msm_sdw_defaults,
|
||||
.num_reg_defaults = ARRAY_SIZE(msm_sdw_defaults),
|
||||
.max_register = MSM_SDW_MAX_REGISTER,
|
||||
.volatile_reg = msm_sdw_is_volatile_register,
|
||||
.readable_reg = msm_sdw_is_readable_register,
|
||||
};
|
||||
|
|
@ -119,7 +119,7 @@ config SND_SOC_INT_CODEC
|
|||
select MSM_QDSP6_PDR
|
||||
select MSM_QDSP6_NOTIFIER
|
||||
select MSM_QDSP6V2_CODECS
|
||||
select SND_SOC_MSM_SWR
|
||||
select SND_SOC_MSM_SDW
|
||||
select SND_SOC_MSM8X16_WCD
|
||||
select QTI_PP
|
||||
select DTS_SRS_TM
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#include "msm-audio-pinctrl.h"
|
||||
#include "msmfalcon-common.h"
|
||||
#include "../codecs/msm8x16/msm8x16-wcd.h"
|
||||
#include "../codecs/msm_sdw/msm_sdw.h"
|
||||
|
||||
#define __CHIPSET__ "MSMFALCON "
|
||||
#define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
|
||||
|
|
@ -30,6 +31,9 @@
|
|||
#define WCN_CDC_SLIM_RX_CH_MAX 2
|
||||
#define WCN_CDC_SLIM_TX_CH_MAX 3
|
||||
|
||||
#define WSA8810_NAME_1 "wsa881x.20170211"
|
||||
#define WSA8810_NAME_2 "wsa881x.20170212"
|
||||
|
||||
enum {
|
||||
INT0_MI2S = 0,
|
||||
INT1_MI2S,
|
||||
|
|
@ -176,6 +180,7 @@ static int msm_int_mi2s_snd_startup(struct snd_pcm_substream *substream);
|
|||
static void msm_int_mi2s_snd_shutdown(struct snd_pcm_substream *substream);
|
||||
|
||||
static struct wcd_mbhc_config *mbhc_cfg_ptr;
|
||||
static struct snd_info_entry *msm_sdw_codec_root;
|
||||
|
||||
static int int_mi2s_get_bit_format_val(int bit_format)
|
||||
{
|
||||
|
|
@ -528,6 +533,33 @@ static int enable_spk_ext_pa(struct snd_soc_codec *codec, int enable)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int msm_config_sdw_gpio(bool enable, struct snd_soc_codec *codec)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
pr_debug("%s: %s SDW Clk/Data Gpios\n", __func__,
|
||||
enable ? "Enable" : "Disable");
|
||||
|
||||
if (enable) {
|
||||
ret = msm_gpioset_activate(CLIENT_WCD, "sdw_pin");
|
||||
if (ret) {
|
||||
pr_err("%s: gpio set cannot be activated %s\n",
|
||||
__func__, "sdw_pin");
|
||||
goto done;
|
||||
}
|
||||
} else {
|
||||
ret = msm_gpioset_suspend(CLIENT_WCD, "sdw_pin");
|
||||
if (ret) {
|
||||
pr_err("%s: gpio set cannot be de-activated %s\n",
|
||||
__func__, "sdw_pin");
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
done:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int int_mi2s_get_idx_from_beid(int32_t be_id)
|
||||
{
|
||||
int idx = 0;
|
||||
|
|
@ -893,7 +925,7 @@ static const struct snd_kcontrol_new msm_snd_controls[] = {
|
|||
msm_bt_sample_rate_put),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new msm_swr_controls[] = {
|
||||
static const struct snd_kcontrol_new msm_sdw_controls[] = {
|
||||
SOC_ENUM_EXT("INT4_MI2S_RX Format", int4_mi2s_rx_format,
|
||||
int_mi2s_bit_format_get, int_mi2s_bit_format_put),
|
||||
SOC_ENUM_EXT("INT4_MI2S_RX SampleRate", int4_mi2s_rx_sample_rate,
|
||||
|
|
@ -1098,7 +1130,7 @@ done:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int msm_swr_mi2s_snd_startup(struct snd_pcm_substream *substream)
|
||||
static int msm_sdw_mi2s_snd_startup(struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
|
||||
|
|
@ -1113,13 +1145,6 @@ static int msm_swr_mi2s_snd_startup(struct snd_pcm_substream *substream)
|
|||
__func__, ret);
|
||||
return ret;
|
||||
}
|
||||
/* Enable the codec mclk config */
|
||||
ret = msm_gpioset_activate(CLIENT_WCD, "swr_pin");
|
||||
if (ret < 0) {
|
||||
pr_err("%s: gpio set cannot be activated %sd",
|
||||
__func__, "swr_pin");
|
||||
return ret;
|
||||
}
|
||||
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS);
|
||||
if (ret < 0)
|
||||
pr_err("%s: set fmt cpu dai failed; ret=%d\n", __func__, ret);
|
||||
|
|
@ -1127,7 +1152,7 @@ static int msm_swr_mi2s_snd_startup(struct snd_pcm_substream *substream)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void msm_swr_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
|
||||
static void msm_sdw_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
|
||||
{
|
||||
int ret;
|
||||
|
||||
|
|
@ -1253,6 +1278,7 @@ static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
|
|||
struct snd_soc_dapm_context *dapm =
|
||||
snd_soc_codec_get_dapm(codec);
|
||||
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
|
||||
struct snd_soc_pcm_runtime *rtd_aux = rtd->card->rtd_aux;
|
||||
int ret = -ENOMEM;
|
||||
|
||||
pr_debug("%s(),dev_name%s\n", __func__, dev_name(cpu_dai->dev));
|
||||
|
|
@ -1285,6 +1311,17 @@ static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
|
|||
|
||||
snd_soc_dapm_sync(dapm);
|
||||
|
||||
/*
|
||||
* Send speaker configuration only for WSA8810.
|
||||
* Defalut configuration is for WSA8815.
|
||||
*/
|
||||
if (rtd_aux && rtd_aux->component)
|
||||
if (!strcmp(rtd_aux->component->name, WSA8810_NAME_1) ||
|
||||
!strcmp(rtd_aux->component->name, WSA8810_NAME_2)) {
|
||||
msm_sdw_set_spkr_mode(rtd->codec, SPKR_MODE_1);
|
||||
msm_sdw_set_spkr_gain_offset(rtd->codec,
|
||||
RX_GAIN_OFFSET_M1P5_DB);
|
||||
}
|
||||
msm8x16_wcd_spk_ext_pa_cb(enable_spk_ext_pa, codec);
|
||||
msm8x16_wcd_hph_comp_cb(msm_config_hph_compander_gpio, codec);
|
||||
|
||||
|
|
@ -1300,24 +1337,38 @@ static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int msm_swr_audrx_init(struct snd_soc_pcm_runtime *rtd)
|
||||
static int msm_sdw_audrx_init(struct snd_soc_pcm_runtime *rtd)
|
||||
{
|
||||
struct snd_soc_codec *codec = rtd->codec;
|
||||
struct snd_soc_dapm_context *dapm =
|
||||
snd_soc_codec_get_dapm(codec);
|
||||
struct snd_card *card;
|
||||
struct snd_info_entry *entry;
|
||||
|
||||
snd_soc_add_codec_controls(codec, msm_swr_controls,
|
||||
ARRAY_SIZE(msm_swr_controls));
|
||||
snd_soc_add_codec_controls(codec, msm_sdw_controls,
|
||||
ARRAY_SIZE(msm_sdw_controls));
|
||||
|
||||
snd_soc_dapm_ignore_suspend(dapm, "AIF1_SWR Playback");
|
||||
snd_soc_dapm_ignore_suspend(dapm, "VIfeed_SWR");
|
||||
snd_soc_dapm_ignore_suspend(dapm, "AIF1_SDW Playback");
|
||||
snd_soc_dapm_ignore_suspend(dapm, "VIfeed_SDW");
|
||||
snd_soc_dapm_ignore_suspend(dapm, "SPK1 OUT");
|
||||
snd_soc_dapm_ignore_suspend(dapm, "SPK2 OUT");
|
||||
snd_soc_dapm_ignore_suspend(dapm, "AIF1_SWR VI");
|
||||
snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_SWR");
|
||||
snd_soc_dapm_ignore_suspend(dapm, "AIF1_SDW VI");
|
||||
snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_SDW");
|
||||
|
||||
snd_soc_dapm_sync(dapm);
|
||||
|
||||
msm_sdw_gpio_cb(msm_config_sdw_gpio, codec);
|
||||
card = rtd->card->snd_card;
|
||||
entry = snd_register_module_info(card->module, "codecs",
|
||||
card->proc_root);
|
||||
if (!entry) {
|
||||
pr_debug("%s: Cannot create codecs module entry\n",
|
||||
__func__);
|
||||
msm_sdw_codec_root = NULL;
|
||||
goto done;
|
||||
}
|
||||
msm_sdw_codec_root = entry;
|
||||
msm_sdw_codec_info_create_codec_entry(msm_sdw_codec_root, codec);
|
||||
done:
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1540,9 +1591,9 @@ static struct snd_soc_ops msm_int_mi2s_be_ops = {
|
|||
.shutdown = msm_int_mi2s_snd_shutdown,
|
||||
};
|
||||
|
||||
static struct snd_soc_ops msm_swr_mi2s_be_ops = {
|
||||
.startup = msm_swr_mi2s_snd_startup,
|
||||
.shutdown = msm_swr_mi2s_snd_shutdown,
|
||||
static struct snd_soc_ops msm_sdw_mi2s_be_ops = {
|
||||
.startup = msm_sdw_mi2s_snd_startup,
|
||||
.shutdown = msm_sdw_mi2s_snd_shutdown,
|
||||
};
|
||||
|
||||
/* Digital audio interface glue - connects codec <---> CPU */
|
||||
|
|
@ -2118,11 +2169,11 @@ static struct snd_soc_dai_link msm_int_dai[] = {
|
|||
.stream_name = "INT5_mi2s Capture",
|
||||
.cpu_dai_name = "msm-dai-q6-mi2s.12",
|
||||
.platform_name = "msm-pcm-hostless",
|
||||
.codec_name = "msm_swr_codec",
|
||||
.codec_dai_name = "msm_swr_vifeedback",
|
||||
.codec_name = "msm_sdw_codec",
|
||||
.codec_dai_name = "msm_sdw_vifeedback",
|
||||
.be_id = MSM_BACKEND_DAI_INT5_MI2S_TX,
|
||||
.be_hw_params_fixup = int_mi2s_be_hw_params_fixup,
|
||||
.ops = &msm_swr_mi2s_be_ops,
|
||||
.ops = &msm_sdw_mi2s_be_ops,
|
||||
.no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
|
||||
.ignore_suspend = 1,
|
||||
.dpcm_capture = 1,
|
||||
|
|
@ -2219,14 +2270,14 @@ static struct snd_soc_dai_link msm_int_dai[] = {
|
|||
.stream_name = "INT4 MI2S Playback",
|
||||
.cpu_dai_name = "msm-dai-q6-mi2s.11",
|
||||
.platform_name = "msm-pcm-routing",
|
||||
.codec_name = "msm_swr_codec",
|
||||
.codec_dai_name = "msm_swr_i2s_rx1",
|
||||
.codec_name = "msm_sdw_codec",
|
||||
.codec_dai_name = "msm_sdw_i2s_rx1",
|
||||
.no_pcm = 1,
|
||||
.dpcm_playback = 1,
|
||||
.be_id = MSM_BACKEND_DAI_INT4_MI2S_RX,
|
||||
.init = &msm_swr_audrx_init,
|
||||
.init = &msm_sdw_audrx_init,
|
||||
.be_hw_params_fixup = int_mi2s_be_hw_params_fixup,
|
||||
.ops = &msm_swr_mi2s_be_ops,
|
||||
.ops = &msm_sdw_mi2s_be_ops,
|
||||
.ignore_suspend = 1,
|
||||
},
|
||||
{
|
||||
|
|
@ -2913,8 +2964,7 @@ static int msm_internal_init(struct platform_device *pdev,
|
|||
AFE_API_VERSION_I2S_CONFIG;
|
||||
pdata->digital_cdc_core_clk.clk_id =
|
||||
Q6AFE_LPASS_CLK_ID_INT_MCLK_0;
|
||||
pdata->digital_cdc_core_clk.clk_freq_in_hz =
|
||||
pdata->mclk_freq;
|
||||
pdata->digital_cdc_core_clk.clk_freq_in_hz = 0;
|
||||
pdata->digital_cdc_core_clk.clk_attri =
|
||||
Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
|
||||
pdata->digital_cdc_core_clk.clk_root =
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue