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msm: mdss: do not set sink max TMDS clock for DVI device

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DVI device does not have CEA extension blocks, we could
not get max TMDS clock from EDID.

Change-Id: I9adcb3006066c2abe6cd79c79865a4f954c1450c
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
This commit is contained in:
Yuan Zhao 2017-08-03 16:48:54 +08:00
parent 560d31410c
commit 25816b726a
1 changed files with 14 additions and 7 deletions
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21
drivers/video/fbdev/msm/mdss_hdmi_tx.c
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@ -2193,6 +2193,7 @@ static int hdmi_tx_read_sink_info(struct hdmi_tx_ctrl *hdmi_ctrl)
int status = 0;
void *data;
struct dss_io_data *io;
u32 sink_max_pclk;
if (!hdmi_ctrl) {
DEV_ERR("%s: invalid input\n", __func__);
@ -2232,16 +2233,22 @@ static int hdmi_tx_read_sink_info(struct hdmi_tx_ctrl *hdmi_ctrl)
/* parse edid if a valid edid buffer is present */
if (hdmi_ctrl->custom_edid || !hdmi_ctrl->sim_mode) {
status = hdmi_edid_parser(data);
if (status)
if (status) {
DEV_ERR("%s: edid parse failed\n", __func__);
else
} else {
/*
* Updata HDMI max supported TMDS clock, consider
* both sink and source capicity.
* Update HDMI max supported TMDS clock, consider
* both sink and source capacity. For DVI sink,
* could not get max TMDS clock from EDID, so just
* use source capacity.
*/
hdmi_edid_set_max_pclk_rate(data,
min(hdmi_edid_get_sink_caps_max_tmds_clk(data) / 1000,
hdmi_ctrl->max_pclk_khz));
sink_max_pclk =
hdmi_edid_get_sink_caps_max_tmds_clk(data);
if (sink_max_pclk != 0)
hdmi_edid_set_max_pclk_rate(data,
min(sink_max_pclk / 1000,
hdmi_ctrl->max_pclk_khz));
}
}
bail:
if (hdmi_tx_enable_power(hdmi_ctrl, HDMI_TX_DDC_PM, false))