msm: mdss: do not set sink max TMDS clock for DVI device
DVI device does not have CEA extension blocks, we could not get max TMDS clock from EDID. Change-Id: I9adcb3006066c2abe6cd79c79865a4f954c1450c Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
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560d31410c
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1 changed files with 14 additions and 7 deletions
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@ -2193,6 +2193,7 @@ static int hdmi_tx_read_sink_info(struct hdmi_tx_ctrl *hdmi_ctrl)
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int status = 0;
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int status = 0;
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void *data;
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void *data;
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struct dss_io_data *io;
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struct dss_io_data *io;
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u32 sink_max_pclk;
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if (!hdmi_ctrl) {
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if (!hdmi_ctrl) {
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DEV_ERR("%s: invalid input\n", __func__);
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DEV_ERR("%s: invalid input\n", __func__);
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@ -2232,17 +2233,23 @@ static int hdmi_tx_read_sink_info(struct hdmi_tx_ctrl *hdmi_ctrl)
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/* parse edid if a valid edid buffer is present */
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/* parse edid if a valid edid buffer is present */
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if (hdmi_ctrl->custom_edid || !hdmi_ctrl->sim_mode) {
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if (hdmi_ctrl->custom_edid || !hdmi_ctrl->sim_mode) {
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status = hdmi_edid_parser(data);
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status = hdmi_edid_parser(data);
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if (status)
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if (status) {
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DEV_ERR("%s: edid parse failed\n", __func__);
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DEV_ERR("%s: edid parse failed\n", __func__);
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else
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} else {
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/*
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/*
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* Updata HDMI max supported TMDS clock, consider
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* Update HDMI max supported TMDS clock, consider
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* both sink and source capicity.
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* both sink and source capacity. For DVI sink,
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* could not get max TMDS clock from EDID, so just
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* use source capacity.
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*/
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*/
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sink_max_pclk =
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hdmi_edid_get_sink_caps_max_tmds_clk(data);
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if (sink_max_pclk != 0)
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hdmi_edid_set_max_pclk_rate(data,
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hdmi_edid_set_max_pclk_rate(data,
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min(hdmi_edid_get_sink_caps_max_tmds_clk(data) / 1000,
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min(sink_max_pclk / 1000,
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hdmi_ctrl->max_pclk_khz));
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hdmi_ctrl->max_pclk_khz));
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}
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}
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}
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bail:
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bail:
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if (hdmi_tx_enable_power(hdmi_ctrl, HDMI_TX_DDC_PM, false))
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if (hdmi_tx_enable_power(hdmi_ctrl, HDMI_TX_DDC_PM, false))
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DEV_ERR("%s: Failed to disable ddc power\n", __func__);
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DEV_ERR("%s: Failed to disable ddc power\n", __func__);
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