diff --git a/sound/soc/msm/apq8096-auto.c b/sound/soc/msm/apq8096-auto.c
index 4bd4469d4904..d6473cccf496 100644
--- a/sound/soc/msm/apq8096-auto.c
+++ b/sound/soc/msm/apq8096-auto.c
@@ -153,6 +153,12 @@ static int msm_pri_tdm_slot_num = 8;
 static int msm_sec_tdm_slot_width = 32;
 static int msm_sec_tdm_slot_num = 8;
 
+static int msm_tert_tdm_slot_width = 32;
+static int msm_tert_tdm_slot_num = 8;
+
+static int msm_quat_tdm_slot_width = 32;
+static int msm_quat_tdm_slot_num = 8;
+
 /* EC Reference default values are set in mixer_paths.xml */
 static int msm_ec_ref_ch = 4;
 static int msm_ec_ref_bit_format = SNDRV_PCM_FORMAT_S16_LE;
@@ -232,7 +238,7 @@ enum {
 	TDM_MAX,
 };
 
-#define TDM_SLOT_OFFSET_MAX    8
+#define TDM_SLOT_OFFSET_MAX   32
 /* TDM default offset */
 static unsigned int tdm_slot_offset[TDM_MAX][TDM_SLOT_OFFSET_MAX] = {
 	/* QUAT_TDM_RX */
@@ -319,7 +325,7 @@ static unsigned int tdm_slot_offset[TDM_MAX][TDM_SLOT_OFFSET_MAX] = {
 ***************************************************************************/
 static unsigned int tdm_slot_offset_adp_mmxf[TDM_MAX][TDM_SLOT_OFFSET_MAX] = {
 	/* QUAT_TDM_RX */
-	{2, 5, 8, 11, 14, 17, 20, 23},
+	{2, 5, 8, 11, 14, 17, 20, 23, 0xFFFF},
 	{26, 0xFFFF},
 	{28, 0xFFFF},
 	{30, 0xFFFF},
@@ -337,7 +343,7 @@ static unsigned int tdm_slot_offset_adp_mmxf[TDM_MAX][TDM_SLOT_OFFSET_MAX] = {
 	{0xFFFF}, /* not used */
 	{0xFFFF}, /* not used */
 	/* TERT_TDM_RX */
-	{2, 5, 8, 11, 14, 17, 20, 23},
+	{2, 5, 8, 11, 14, 17, 20, 23, 0xFFFF},
 	{26, 0xFFFF},
 	{28, 0xFFFF},
 	{30, 0xFFFF},
@@ -395,7 +401,7 @@ static unsigned int tdm_slot_offset_adp_mmxf[TDM_MAX][TDM_SLOT_OFFSET_MAX] = {
 static unsigned int tdm_slot_offset_custom[TDM_MAX][TDM_SLOT_OFFSET_MAX] = {
 	/* QUAT_TDM_RX */
 	{0, 2, 0xFFFF},
-	{4, 6, 8, 10, 12, 14, 16, 18},
+	{4, 6, 8, 10, 12, 14, 16, 18, 0xFFFF},
 	{20, 22, 24, 26, 28, 30, 0xFFFF},
 	{0xFFFF}, /* not used */
 	{0xFFFF}, /* not used */
@@ -417,12 +423,12 @@ static unsigned int tdm_slot_offset_custom[TDM_MAX][TDM_SLOT_OFFSET_MAX] = {
 	{6, 0xFFFF},
 	{8, 0xFFFF},
 	{10, 0xFFFF},
-	{12, 14, 16, 18, 20, 22, 24, 26},
+	{12, 14, 16, 18, 20, 22, 24, 26, 0xFFFF},
 	{28, 30, 0xFFFF},
 	{0xFFFF}, /* not used */
 	/* TERT_TDM_TX */
 	{0, 2, 0xFFFF},
-	{4, 6, 8, 10, 12, 14, 16, 18},
+	{4, 6, 8, 10, 12, 14, 16, 18, 0xFFFF},
 	{20, 22, 24, 26, 28, 30, 0xFFFF},
 	{0xFFFF}, /* not used */
 	{0xFFFF}, /* not used */
@@ -480,8 +486,16 @@ static char const *hdmi_rx_sample_rate_text[] = {"KHZ_48", "KHZ_96",
 
 static const char *const auxpcm_rate_text[] = {"8000", "16000"};
 
-static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
-	"Five", "Six", "Seven", "Eight"};
+static char const *tdm_ch_text[] = {
+	"One", "Two", "Three", "Four",
+	"Five", "Six", "Seven", "Eight",
+	"Nine", "Ten", "Eleven", "Twelve",
+	"Thirteen", "Fourteen", "Fifteen", "Sixteen",
+	"Seventeen", "Eighteen", "Nineteen", "Twenty",
+	"TwentyOne", "TwentyTwo", "TwentyThree", "TwentyFour",
+	"TwentyFive", "TwentySix", "TwentySeven", "TwentyEight",
+	"TwentyNine", "Thirty", "ThirtyOne", "ThirtyTwo"
+};
 
 static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE"};
 
@@ -500,7 +514,8 @@ static const char *const mi2s_rate_text[] = {"32000", "44100", "48000"};
 static const char *const tdm_rate_text[] = {"8000", "16000", "48000"};
 
 static const char *const tdm_slot_num_text[] = {"One", "Two", "Four",
-	"Eight", "Sixteen", "Thirtytwo"};
+	"Eight", "Sixteen", "ThirtyTwo"};
+
 
 static const char *const tdm_slot_width_text[] = {"16", "24", "32"};
 
@@ -1236,6 +1251,190 @@ static int msm_sec_tdm_slot_num_put(struct snd_kcontrol *kcontrol,
 	return 0;
 }
 
+static int msm_tert_tdm_slot_width_get(struct snd_kcontrol *kcontrol,
+				    struct snd_ctl_elem_value *ucontrol)
+{
+	ucontrol->value.integer.value[0] = msm_tert_tdm_slot_width;
+	pr_debug("%s: msm_tert_tdm_slot_width = %d\n",
+			__func__, msm_tert_tdm_slot_width);
+	return 0;
+}
+
+static int msm_tert_tdm_slot_width_put(struct snd_kcontrol *kcontrol,
+				    struct snd_ctl_elem_value *ucontrol)
+{
+	switch (ucontrol->value.integer.value[0]) {
+	case 0:
+		msm_tert_tdm_slot_width = 16;
+		break;
+	case 1:
+		msm_tert_tdm_slot_width = 24;
+		break;
+	case 2:
+		msm_tert_tdm_slot_width = 32;
+		break;
+	default:
+		msm_tert_tdm_slot_width = 32;
+		break;
+	}
+	pr_debug("%s: msm_tert_tdm_slot_width= %d\n",
+		__func__, msm_tert_tdm_slot_width);
+	return 0;
+}
+
+static int msm_tert_tdm_slot_num_get(struct snd_kcontrol *kcontrol,
+				    struct snd_ctl_elem_value *ucontrol)
+{
+	switch (msm_tert_tdm_slot_num) {
+	case 1:
+		ucontrol->value.integer.value[0] = 0;
+		break;
+	case 2:
+		ucontrol->value.integer.value[0] = 1;
+		break;
+	case 4:
+		ucontrol->value.integer.value[0] = 2;
+		break;
+	case 8:
+		ucontrol->value.integer.value[0] = 3;
+		break;
+	case 16:
+		ucontrol->value.integer.value[0] = 4;
+		break;
+	case 32:
+	default:
+		ucontrol->value.integer.value[0] = 5;
+		break;
+	}
+
+	pr_debug("%s: msm_tert_tdm_slot_num = %d\n",
+		__func__, msm_tert_tdm_slot_num);
+	return 0;
+}
+
+static int msm_tert_tdm_slot_num_put(struct snd_kcontrol *kcontrol,
+				    struct snd_ctl_elem_value *ucontrol)
+{
+	switch (ucontrol->value.integer.value[0]) {
+	case 0:
+		msm_tert_tdm_slot_num = 1;
+		break;
+	case 1:
+		msm_tert_tdm_slot_num = 2;
+		break;
+	case 2:
+		msm_tert_tdm_slot_num = 4;
+		break;
+	case 3:
+		msm_tert_tdm_slot_num = 8;
+		break;
+	case 4:
+		msm_tert_tdm_slot_num = 16;
+		break;
+	case 5:
+		msm_tert_tdm_slot_num = 32;
+		break;
+	default:
+		msm_tert_tdm_slot_num = 8;
+		break;
+	}
+	pr_debug("%s: msm_tert_tdm_slot_num = %d\n",
+		__func__,  msm_tert_tdm_slot_num);
+	return 0;
+}
+
+static int msm_quat_tdm_slot_width_get(struct snd_kcontrol *kcontrol,
+				    struct snd_ctl_elem_value *ucontrol)
+{
+	ucontrol->value.integer.value[0] = msm_quat_tdm_slot_width;
+	pr_debug("%s: msm_quat_tdm_slot_width = %d\n",
+			__func__, msm_quat_tdm_slot_width);
+	return 0;
+}
+
+static int msm_quat_tdm_slot_width_put(struct snd_kcontrol *kcontrol,
+				    struct snd_ctl_elem_value *ucontrol)
+{
+	switch (ucontrol->value.integer.value[0]) {
+	case 0:
+		msm_quat_tdm_slot_width = 16;
+		break;
+	case 1:
+		msm_quat_tdm_slot_width = 24;
+		break;
+	case 2:
+		msm_quat_tdm_slot_width = 32;
+		break;
+	default:
+		msm_quat_tdm_slot_width = 32;
+		break;
+	}
+	pr_debug("%s: msm_quat_tdm_slot_width= %d\n",
+		__func__, msm_quat_tdm_slot_width);
+	return 0;
+}
+
+static int msm_quat_tdm_slot_num_get(struct snd_kcontrol *kcontrol,
+				    struct snd_ctl_elem_value *ucontrol)
+{
+	switch (msm_quat_tdm_slot_num) {
+	case 1:
+		ucontrol->value.integer.value[0] = 0;
+		break;
+	case 2:
+		ucontrol->value.integer.value[0] = 1;
+		break;
+	case 4:
+		ucontrol->value.integer.value[0] = 2;
+		break;
+	case 8:
+		ucontrol->value.integer.value[0] = 3;
+		break;
+	case 16:
+		ucontrol->value.integer.value[0] = 4;
+		break;
+	case 32:
+	default:
+		ucontrol->value.integer.value[0] = 5;
+		break;
+	}
+
+	pr_debug("%s: msm_quat_tdm_slot_num = %d\n",
+		__func__, msm_quat_tdm_slot_num);
+	return 0;
+}
+
+static int msm_quat_tdm_slot_num_put(struct snd_kcontrol *kcontrol,
+				    struct snd_ctl_elem_value *ucontrol)
+{
+	switch (ucontrol->value.integer.value[0]) {
+	case 0:
+		msm_quat_tdm_slot_num = 1;
+		break;
+	case 1:
+		msm_quat_tdm_slot_num = 2;
+		break;
+	case 2:
+		msm_quat_tdm_slot_num = 4;
+		break;
+	case 3:
+		msm_quat_tdm_slot_num = 8;
+		break;
+	case 4:
+		msm_quat_tdm_slot_num = 16;
+		break;
+	case 5:
+		msm_quat_tdm_slot_num = 32;
+		break;
+	default:
+		msm_quat_tdm_slot_num = 8;
+		break;
+	}
+	pr_debug("%s: msm_quat_tdm_slot_num = %d\n",
+		__func__,  msm_quat_tdm_slot_num);
+	return 0;
+}
+
 static int msm_tdm_slot_mapping_get(struct snd_kcontrol *kcontrol,
 				    struct snd_ctl_elem_value *ucontrol)
 {
@@ -3457,7 +3656,7 @@ static int apq8096_tdm_snd_hw_params(struct snd_pcm_substream *substream,
 
 	rate = params_rate(params);
 	channels = params_channels(params);
-	if (channels < 1 || channels > 8) {
+	if (channels < 1 || channels > 32) {
 		pr_err("%s: invalid param channels %d\n",
 			__func__, channels);
 		return -EINVAL;
@@ -3644,99 +3843,163 @@ static int apq8096_tdm_snd_hw_params(struct snd_pcm_substream *substream,
 		slot_offset = tdm_slot_offset[SECONDARY_TDM_TX_7];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_RX:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_RX_0];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_RX_1:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_RX_1];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_RX_2:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_RX_2];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_RX_3:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_RX_3];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_RX_4:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_RX_4];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_RX_5:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_RX_5];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_RX_6:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_RX_6];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_RX_7:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_RX_7];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_TX:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_TX_0];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_TX_1:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_TX_1];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_TX_2:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_TX_2];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_TX_3:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_TX_3];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_TX_4:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_TX_4];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_TX_5:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_TX_5];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_TX_6:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_TX_6];
 		break;
 	case AFE_PORT_ID_TERTIARY_TDM_TX_7:
+		slots = msm_tert_tdm_slot_num;
+		slot_width = msm_tert_tdm_slot_width;
 		slot_offset = tdm_slot_offset[TERTIARY_TDM_TX_7];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_RX:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_RX_0];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_RX_1];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_RX_2];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_RX_3];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_RX_4:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_RX_4];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_RX_5:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_RX_5];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_RX_6:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_RX_6];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_RX_7:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_RX_7];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_TX:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_TX_0];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_TX_1];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_TX_2];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_TX_3];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_TX_4:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_TX_4];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_TX_5:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_TX_5];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_TX_6:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_TX_6];
 		break;
 	case AFE_PORT_ID_QUATERNARY_TDM_TX_7:
+		slots = msm_quat_tdm_slot_num;
+		slot_width = msm_quat_tdm_slot_width;
 		slot_offset = tdm_slot_offset[QUATERNARY_TDM_TX_7];
 		break;
 	default:
@@ -3826,7 +4089,7 @@ static const struct soc_enum msm_snd_enum[] = {
 	SOC_ENUM_SINGLE_EXT(2, hdmi_rx_bit_format_text),
 	SOC_ENUM_SINGLE_EXT(8, proxy_rx_ch_text),
 	SOC_ENUM_SINGLE_EXT(3, hdmi_rx_sample_rate_text),
-	SOC_ENUM_SINGLE_EXT(8, tdm_ch_text),
+	SOC_ENUM_SINGLE_EXT(32, tdm_ch_text),
 	SOC_ENUM_SINGLE_EXT(2, tdm_bit_format_text),
 	SOC_ENUM_SINGLE_EXT(2, mi2s_bit_format_text),
 	SOC_ENUM_SINGLE_EXT(9, ec_ref_ch_text),
@@ -4038,261 +4301,273 @@ static const struct snd_kcontrol_new msm_snd_controls[] = {
 			msm_sec_tdm_slot_num_get, msm_sec_tdm_slot_num_put),
 	SOC_ENUM_EXT("SEC_TDM Slot Width", msm_snd_enum[14],
 			msm_sec_tdm_slot_width_get, msm_sec_tdm_slot_width_put),
+	SOC_ENUM_EXT("TERT_TDM Slot Number", msm_snd_enum[13],
+			msm_tert_tdm_slot_num_get,
+			msm_tert_tdm_slot_num_put),
+	SOC_ENUM_EXT("TERT_TDM Slot Width", msm_snd_enum[14],
+			msm_tert_tdm_slot_width_get,
+			msm_tert_tdm_slot_width_put),
+	SOC_ENUM_EXT("QUAT_TDM Slot Number", msm_snd_enum[13],
+			msm_quat_tdm_slot_num_get,
+			msm_quat_tdm_slot_num_put),
+	SOC_ENUM_EXT("QUAT_TDM Slot Width", msm_snd_enum[14],
+			msm_quat_tdm_slot_width_get,
+			msm_quat_tdm_slot_width_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_0 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_RX_0, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_1 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_RX_1, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_2 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_RX_2, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_3 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_RX_3, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_4 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_RX_4, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_5 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_RX_5, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_6 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_RX_6, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_7 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_RX_7, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_0 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_TX_0, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_1 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_TX_1, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_2 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_TX_2, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_3 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_TX_3, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_4 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_TX_4, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_5 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_TX_5, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_6 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_TX_6, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_7 Slot Mapping", SND_SOC_NOPM,
 		PRIMARY_TDM_TX_7, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_0 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_RX_0, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_1 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_RX_1, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_2 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_RX_2, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_3 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_RX_3, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_4 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_RX_4, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_5 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_RX_5, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_6 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_RX_6, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_7 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_RX_7, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_0 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_TX_0, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_1 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_TX_1, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_2 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_TX_2, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_3 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_TX_3, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_4 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_TX_4, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_5 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_TX_5, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_6 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_TX_6, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_7 Slot Mapping", SND_SOC_NOPM,
 		SECONDARY_TDM_TX_7, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_0 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_RX_0, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_1 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_RX_1, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_2 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_RX_2, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_3 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_RX_3, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_4 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_RX_4, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_5 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_RX_5, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_6 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_RX_6, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_7 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_RX_7, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_0 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_TX_0, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_1 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_TX_1, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_2 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_TX_2, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_3 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_TX_3, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_4 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_TX_4, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_5 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_TX_5, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_6 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_TX_6, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_7 Slot Mapping", SND_SOC_NOPM,
 		TERTIARY_TDM_TX_7, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_0 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_RX_0, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_1 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_RX_1, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_2 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_RX_2, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_3 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_RX_3, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_4 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_RX_4, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_5 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_RX_5, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_6 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_RX_6, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_7 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_RX_7, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_0 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_TX_0, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_1 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_TX_1, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_2 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_TX_2, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_3 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_TX_3, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_4 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_TX_4, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_5 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_TX_5, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_6 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_TX_6, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_7 Slot Mapping", SND_SOC_NOPM,
 		QUATERNARY_TDM_TX_7, 0xFFFF,
-		0, 8, msm_tdm_slot_mapping_get,
+		0, TDM_SLOT_OFFSET_MAX, msm_tdm_slot_mapping_get,
 		msm_tdm_slot_mapping_put),
 	SOC_ENUM_EXT("EC Reference Channels", msm_snd_enum[8],
 			msm_ec_ref_ch_get, msm_ec_ref_ch_put),
@@ -6511,8 +6786,14 @@ static int apq8096_init_tdm_dev(struct device *dev)
 			sizeof(tdm_slot_offset_adp_mmxf));
 	} else if (!strcmp(match->data, "auto_custom_codec")) {
 		dev_dbg(dev, "%s: custom tdm slot offset\n", __func__);
-		msm_tdm_slot_width = 16;
-		msm_tdm_num_slots = 16;
+		msm_pri_tdm_slot_width = 16;
+		msm_pri_tdm_slot_num = 16;
+		msm_sec_tdm_slot_width = 16;
+		msm_sec_tdm_slot_num = 16;
+		msm_tert_tdm_slot_width = 16;
+		msm_tert_tdm_slot_num = 16;
+		msm_quat_tdm_slot_width = 16;
+		msm_quat_tdm_slot_num = 16;
 		memcpy(tdm_slot_offset,
 			tdm_slot_offset_custom,
 			sizeof(tdm_slot_offset_custom));