diff --git a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt index a3dc40936e8e..54a3c5689b9c 100644 --- a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt +++ b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt @@ -79,6 +79,7 @@ Optional properties: current issue. - qcom,qdsp6v61-1-1: Boolean- Present if the qdsp version is v61 1.1 - qcom,qdsp6v62-1-2: Boolean- Present if the qdsp version is v62 1.2 +- qcom,qdsp6v62-1-5: Boolean- Present if the qdsp version is v62 1.5 - qcom,mx-spike-wa: Boolean- Present if we need to assert QDSP6 I/O clamp, memory wordline clamp, and compiler memory clamp during MSS restart. - qcom,qdsp6v56-1-10: Boolean- Present if the qdsp version is v56 1.10 diff --git a/arch/arm/boot/dts/qcom/msmtriton-smp2p.dtsi b/arch/arm/boot/dts/qcom/msmtriton-smp2p.dtsi index 1a72414de094..b458bbb08dc2 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-smp2p.dtsi +++ b/arch/arm/boot/dts/qcom/msmtriton-smp2p.dtsi @@ -134,6 +134,29 @@ gpios = <&smp2pgpio_sleepstate_2_out 0 0>; }; + /* ssr - inbound entry from mss */ + smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - outbound entry to mss */ + smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + /* ssr - inbound entry from lpass */ smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in { compatible = "qcom,smp2pgpio"; diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/msmtriton.dtsi index 083c14af7839..807c40fcc46e 100644 --- a/arch/arm/boot/dts/qcom/msmtriton.dtsi +++ b/arch/arm/boot/dts/qcom/msmtriton.dtsi @@ -609,6 +609,59 @@ memory-region = <&venus_fw_mem>; status = "ok"; }; + + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-q6v55-mss"; + reg = <0x4080000 0x100>, + <0x1f63000 0x008>, + <0x1f65000 0x008>, + <0x1f64000 0x008>, + <0x4180000 0x040>, + <0x00179000 0x004>; + reg-names = "qdsp6_base", "halt_q6", "halt_modem", + "halt_nc", "rmb_base", "restart_reg"; + + clocks = <&clock_rpmcc RPM_XO_CLK_SRC>, + <&clock_gcc GCC_MSS_CFG_AHB_CLK>, + <&clock_gcc GCC_BIMC_MSS_Q6_AXI_CLK>, + <&clock_gcc GCC_BOOT_ROM_AHB_CLK>, + <&clock_gcc GPLL0_OUT_MSSCC>, + <&clock_gcc GCC_MSS_SNOC_AXI_CLK>, + <&clock_gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, + <&clock_rpmcc RPM_QDSS_CLK>; + clock-names = "xo", "iface_clk", "bus_clk", + "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", + "mnoc_axi_clk", "qdss_clk"; + qcom,proxy-clock-names = "xo", "qdss_clk"; + qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk", + "gpll0_mss_clk", "snoc_axi_clk", + "mnoc_axi_clk"; + + interrupts = <0 448 1>; + vdd_cx-supply = <&pmfalcon_s3b_level>; + vdd_cx-voltage = ; + vdd_mx-supply = <&pmfalcon_s5b_level>; + vdd_mx-uV = ; + qcom,firmware-name = "modem"; + qcom,pil-self-auth; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,override-acc; + qcom,qdsp6v62-1-5; + memory-region = <&modem_fw_mem>; + qcom,mem-protect-id = <0xF>; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; + qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + status = "ok"; + }; }; #include "msmtriton-ion.dtsi" diff --git a/drivers/soc/qcom/pil-q6v5.c b/drivers/soc/qcom/pil-q6v5.c index f8895e8a7b3d..5752aecb82bd 100644 --- a/drivers/soc/qcom/pil-q6v5.c +++ b/drivers/soc/qcom/pil-q6v5.c @@ -388,7 +388,7 @@ static int __pil_q6v55_reset(struct pil_desc *pil) mb(); udelay(1); - if (drv->qdsp6v62_1_2) { + if (drv->qdsp6v62_1_2 || drv->qdsp6v62_1_5) { for (i = BHS_CHECK_MAX_LOOPS; i > 0; i--) { if (readl_relaxed(drv->reg_base + QDSP6V62SS_BHS_STATUS) & QDSP6v55_BHS_EN_REST_ACK) @@ -488,7 +488,8 @@ static int __pil_q6v55_reset(struct pil_desc *pil) */ udelay(1); } - } else if (drv->qdsp6v61_1_1 || drv->qdsp6v62_1_2) { + } else if (drv->qdsp6v61_1_1 || drv->qdsp6v62_1_2 || + drv->qdsp6v62_1_5) { /* Deassert QDSP6 compiler memory clamp */ val = readl_relaxed(drv->reg_base + QDSP6SS_PWR_CTL); val &= ~QDSP6v55_CLAMP_QMC_MEM; @@ -501,7 +502,13 @@ static int __pil_q6v55_reset(struct pil_desc *pil) /* Turn on L1, L2, ETB and JU memories 1 at a time */ val = readl_relaxed(drv->reg_base + QDSP6V6SS_MEM_PWR_CTL); - for (i = 28; i >= 0; i--) { + + if (drv->qdsp6v62_1_5) + i = 29; + else + i = 28; + + for ( ; i >= 0; i--) { val |= BIT(i); writel_relaxed(val, drv->reg_base + QDSP6V6SS_MEM_PWR_CTL); @@ -663,6 +670,9 @@ struct q6v5_data *pil_q6v5_init(struct platform_device *pdev) drv->qdsp6v62_1_2 = of_property_read_bool(pdev->dev.of_node, "qcom,qdsp6v62-1-2"); + drv->qdsp6v62_1_5 = of_property_read_bool(pdev->dev.of_node, + "qcom,qdsp6v62-1-5"); + drv->non_elf_image = of_property_read_bool(pdev->dev.of_node, "qcom,mba-image-is-not-elf"); diff --git a/drivers/soc/qcom/pil-q6v5.h b/drivers/soc/qcom/pil-q6v5.h index 6a59b06f7b6c..9e8b8511e69b 100644 --- a/drivers/soc/qcom/pil-q6v5.h +++ b/drivers/soc/qcom/pil-q6v5.h @@ -62,6 +62,7 @@ struct q6v5_data { bool qdsp6v56_1_10; bool qdsp6v61_1_1; bool qdsp6v62_1_2; + bool qdsp6v62_1_5; bool non_elf_image; bool restart_reg_sec; bool override_acc;