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scsi: ufs-qcom-ice: add support for register interface changes

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This change adds support for following changes in register interface for
newer UFS controllers:
The register UFS_ICE_CTRL_INFO_n_1 contains 32-bit LSB of crypto data-unit
base number. The register UFS_ICE_CTRL_INFO_n_2 contains 32-bit MSB of the
crypto data-unit base number. The register UFS_ICE_CTRL_INFO_n_3 contains
bitfields BYPASS, CNFG_KEY_INDX, and CDU_SIZE.

Change-Id: I2a9b0b87e912a876e46746431c75e32a0e21a1c6
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
This commit is contained in:
Subhash Jadavani 2015-03-02 12:39:41 -08:00 • committed by David Keitel
parent cd64baf8a1
commit 295bcc19e7
2 changed files with 34 additions and 22 deletions
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39
drivers/scsi/ufs/ufs-qcom-ice.c
View file

@ -263,7 +263,7 @@ int ufs_qcom_ice_cfg(struct ufs_qcom_host *qcom_host, struct scsi_cmnd *cmd)
struct ice_data_setting ice_set;
unsigned int slot = 0;
sector_t lba = 0;
unsigned int ctrl_info_2_val = 0;
unsigned int ctrl_info_val = 0;
unsigned int bypass = 0;
struct request *req;
char cmd_op;
@ -320,27 +320,38 @@ int ufs_qcom_ice_cfg(struct ufs_qcom_host *qcom_host, struct scsi_cmnd *cmd)
UFS_QCOM_ICE_DISABLE_BYPASS;
/* Configure ICE index */
ctrl_info_2_val =
ctrl_info_val =
(ice_set.crypto_data.key_index &
MASK_UFS_QCOM_ICE_CTRL_INFO_2_KEY_INDEX)
<< OFFSET_UFS_QCOM_ICE_CTRL_INFO_2_KEY_INDEX;
MASK_UFS_QCOM_ICE_CTRL_INFO_KEY_INDEX)
<< OFFSET_UFS_QCOM_ICE_CTRL_INFO_KEY_INDEX;
/* Configure data unit size of transfer request */
ctrl_info_2_val |=
ctrl_info_val |=
(UFS_QCOM_ICE_TR_DATA_UNIT_4_KB &
MASK_UFS_QCOM_ICE_CTRL_INFO_2_CDU)
<< OFFSET_UFS_QCOM_ICE_CTRL_INFO_2_CDU;
MASK_UFS_QCOM_ICE_CTRL_INFO_CDU)
<< OFFSET_UFS_QCOM_ICE_CTRL_INFO_CDU;
/* Configure ICE bypass mode */
ctrl_info_2_val |=
(bypass & MASK_UFS_QCOM_ICE_CTRL_INFO_2_BYPASS)
<< OFFSET_UFS_QCOM_ICE_CTRL_INFO_2_BYPASS;
ctrl_info_val |=
(bypass & MASK_UFS_QCOM_ICE_CTRL_INFO_BYPASS)
<< OFFSET_UFS_QCOM_ICE_CTRL_INFO_BYPASS;
ufshcd_writel(qcom_host->hba, lba,
(REG_UFS_QCOM_ICE_CTRL_INFO_1_n + 8 * slot));
if (qcom_host->hw_ver.major < 0x2) {
ufshcd_writel(qcom_host->hba, lba,
(REG_UFS_QCOM_ICE_CTRL_INFO_1_n + 8 * slot));
ufshcd_writel(qcom_host->hba, ctrl_info_2_val,
(REG_UFS_QCOM_ICE_CTRL_INFO_2_n + 8 * slot));
ufshcd_writel(qcom_host->hba, ctrl_info_val,
(REG_UFS_QCOM_ICE_CTRL_INFO_2_n + 8 * slot));
} else {
ufshcd_writel(qcom_host->hba, (lba & 0xFFFFFFFF),
(REG_UFS_QCOM_ICE_CTRL_INFO_1_n + 16 * slot));
ufshcd_writel(qcom_host->hba, ((lba >> 32) & 0xFFFFFFFF),
(REG_UFS_QCOM_ICE_CTRL_INFO_2_n + 16 * slot));
ufshcd_writel(qcom_host->hba, ctrl_info_val,
(REG_UFS_QCOM_ICE_CTRL_INFO_3_n + 16 * slot));
}
/*
* Ensure UFS-ICE registers are being configured

17
drivers/scsi/ufs/ufs-qcom-ice.h
View file

@ -27,21 +27,22 @@ enum {
REG_UFS_QCOM_ICE_CFG = 0x2200,
REG_UFS_QCOM_ICE_CTRL_INFO_1_n = 0x2204,
REG_UFS_QCOM_ICE_CTRL_INFO_2_n = 0x2208,
REG_UFS_QCOM_ICE_CTRL_INFO_3_n = 0x220C,
};
#define NUM_QCOM_ICE_CTRL_INFO_n_REGS 32
/* UFS QCOM ICE CTRL Info 2 register offset */
/* UFS QCOM ICE CTRL Info register offset */
enum {
OFFSET_UFS_QCOM_ICE_CTRL_INFO_2_BYPASS = 0,
OFFSET_UFS_QCOM_ICE_CTRL_INFO_2_KEY_INDEX = 0x1,
OFFSET_UFS_QCOM_ICE_CTRL_INFO_2_CDU = 0x6,
OFFSET_UFS_QCOM_ICE_CTRL_INFO_BYPASS = 0,
OFFSET_UFS_QCOM_ICE_CTRL_INFO_KEY_INDEX = 0x1,
OFFSET_UFS_QCOM_ICE_CTRL_INFO_CDU = 0x6,
};
/* UFS QCOM ICE CTRL Info 2 register masks */
/* UFS QCOM ICE CTRL Info register masks */
enum {
MASK_UFS_QCOM_ICE_CTRL_INFO_2_BYPASS = 0x1,
MASK_UFS_QCOM_ICE_CTRL_INFO_2_KEY_INDEX = 0x1F,
MASK_UFS_QCOM_ICE_CTRL_INFO_2_CDU = 0x8,
MASK_UFS_QCOM_ICE_CTRL_INFO_BYPASS = 0x1,
MASK_UFS_QCOM_ICE_CTRL_INFO_KEY_INDEX = 0x1F,
MASK_UFS_QCOM_ICE_CTRL_INFO_CDU = 0x8,
};
/* UFS QCOM ICE encryption/decryption bypass state */