mmc: sdhci-pci: allow 8-bit bus width for Intel PCH
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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1 changed files with 33 additions and 0 deletions
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@ -28,6 +28,12 @@
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#include "sdhci.h"
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#include "sdhci.h"
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/*
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* PCI device IDs
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*/
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#define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
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#define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
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/*
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/*
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* PCI registers
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* PCI registers
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*/
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*/
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@ -174,6 +180,12 @@ static int mrst_hc_probe(struct sdhci_pci_chip *chip)
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return 0;
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return 0;
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}
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}
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static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
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{
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slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
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return 0;
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}
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#ifdef CONFIG_PM_RUNTIME
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#ifdef CONFIG_PM_RUNTIME
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static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
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static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
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@ -285,6 +297,11 @@ static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
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.probe_slot = mfd_emmc_probe_slot,
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.probe_slot = mfd_emmc_probe_slot,
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};
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};
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static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
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.quirks = SDHCI_QUIRK_BROKEN_ADMA,
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.probe_slot = pch_hc_probe_slot,
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};
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/* O2Micro extra registers */
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/* O2Micro extra registers */
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#define O2_SD_LOCK_WP 0xD3
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#define O2_SD_LOCK_WP 0xD3
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#define O2_SD_MULTI_VCC3V 0xEE
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#define O2_SD_MULTI_VCC3V 0xEE
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@ -820,6 +837,22 @@ static const struct pci_device_id pci_ids[] __devinitdata = {
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.driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
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.driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
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},
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},
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{
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
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},
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{
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
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},
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{
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{
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.vendor = PCI_VENDOR_ID_O2,
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.vendor = PCI_VENDOR_ID_O2,
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.device = PCI_DEVICE_ID_O2_8120,
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.device = PCI_DEVICE_ID_O2_8120,
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