From 2ba264341c60b4a5ab95ef75575a92b941cedc9d Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Thu, 29 Aug 2013 16:21:08 +0530 Subject: [PATCH] mmc: sdhci-msm: Fix issue with power save bit enablement The power save bit is currently enabled based on the clock rate (clk_rate > 400KHz) within struct sdhci_msm_host. But this clk_rate is updated with the latest value down in this function sdhci_msm_set_clock(). So during runtime/system resume when the card is still in initialization phase, the power save bit is getting enabled when sdhci_msm_set_clock() is called for the first time based on the previous rate which is wrong. Change-Id: I05dc8a4a760f658935de3831aaf8dd3b2b996466 Signed-off-by: Sahitya Tummala --- drivers/mmc/host/sdhci-msm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index a25f3e83037c..7bdc85437854 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -2405,7 +2405,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) curr_pwrsave = !!(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & CORE_CLK_PWRSAVE); - if ((msm_host->clk_rate > 400000) && + if ((clock > 400000) && !curr_pwrsave && mmc_host_may_gate_card(host->mmc->card)) writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) | CORE_CLK_PWRSAVE,