mips/kvm: Improve code formatting in arch/mips/kvm/kvm_locore.S

No code changes, just reflowing some comments and consistently using
tabs and spaces.  Object code is verified to be unchanged.

Signed-off-by: David Daney <david.daney@cavium.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
This commit is contained in:
David Daney 2013-08-01 13:22:33 -07:00 committed by Gleb Natapov
parent cc2df20c7c
commit 2c07ebbd2c

View file

@ -125,7 +125,10 @@ FEXPORT(__kvm_mips_vcpu_run)
/* Offset into vcpu->arch */ /* Offset into vcpu->arch */
addiu k1, a1, VCPU_HOST_ARCH addiu k1, a1, VCPU_HOST_ARCH
/* Save the host stack to VCPU, used for exception processing when we exit from the Guest */ /*
* Save the host stack to VCPU, used for exception processing
* when we exit from the Guest
*/
LONG_S sp, VCPU_HOST_STACK(k1) LONG_S sp, VCPU_HOST_STACK(k1)
/* Save the kernel gp as well */ /* Save the kernel gp as well */
@ -140,8 +143,10 @@ FEXPORT(__kvm_mips_vcpu_run)
LONG_L k0, VCPU_GUEST_EBASE(k1) LONG_L k0, VCPU_GUEST_EBASE(k1)
mtc0 k0, CP0_EBASE mtc0 k0, CP0_EBASE
/* Now that the new EBASE has been loaded, unset BEV, set interrupt mask as it was /*
* but make sure that timer interrupts are enabled * Now that the new EBASE has been loaded, unset BEV, set
* interrupt mask as it was but make sure that timer interrupts
* are enabled
*/ */
li k0, (ST0_EXL | KSU_USER | ST0_IE) li k0, (ST0_EXL | KSU_USER | ST0_IE)
andi v0, v0, ST0_IM andi v0, v0, ST0_IM
@ -327,8 +332,8 @@ NESTED (MIPSX(GuestException), CALLFRAME_SIZ, ra)
/* Save pointer to run in s0, will be saved by the compiler */ /* Save pointer to run in s0, will be saved by the compiler */
move s0, a0 move s0, a0
/* Save Host level EPC, BadVaddr and Cause to VCPU, useful to
/* Save Host level EPC, BadVaddr and Cause to VCPU, useful to process the exception */ * process the exception */
mfc0 k0,CP0_EPC mfc0 k0,CP0_EPC
LONG_S k0, VCPU_PC(k1) LONG_S k0, VCPU_PC(k1)
@ -389,8 +394,9 @@ NESTED (MIPSX(GuestException), CALLFRAME_SIZ, ra)
/* Jump to handler */ /* Jump to handler */
FEXPORT(__kvm_mips_jump_to_handler) FEXPORT(__kvm_mips_jump_to_handler)
/* XXXKYMA: not sure if this is safe, how large is the stack?? */ /* XXXKYMA: not sure if this is safe, how large is the stack??
/* Now jump to the kvm_mips_handle_exit() to see if we can deal with this in the kernel */ * Now jump to the kvm_mips_handle_exit() to see if we can deal
* with this in the kernel */
la t9, kvm_mips_handle_exit la t9, kvm_mips_handle_exit
jalr.hb t9 jalr.hb t9
addiu sp, sp, -CALLFRAME_SIZ /* BD Slot */ addiu sp, sp, -CALLFRAME_SIZ /* BD Slot */
@ -399,14 +405,16 @@ FEXPORT(__kvm_mips_jump_to_handler)
di di
ehb ehb
/* XXXKYMA: k0/k1 could have been blown away if we processed an exception /* XXXKYMA: k0/k1 could have been blown away if we processed
* while we were handling the exception from the guest, reload k1 * an exception while we were handling the exception from the
* guest, reload k1
*/ */
move k1, s1 move k1, s1
addiu k1, k1, VCPU_HOST_ARCH addiu k1, k1, VCPU_HOST_ARCH
/* Check return value, should tell us if we are returning to the host (handle I/O etc) /* Check return value, should tell us if we are returning to the
* or resuming the guest * host (handle I/O etc)or resuming the guest
*/ */
andi t0, v0, RESUME_HOST andi t0, v0, RESUME_HOST
bnez t0, __kvm_mips_return_to_host bnez t0, __kvm_mips_return_to_host
@ -436,7 +444,6 @@ __kvm_mips_return_to_guest:
mtc0 v1, CP0_STATUS mtc0 v1, CP0_STATUS
ehb ehb
/* Set Guest EPC */ /* Set Guest EPC */
LONG_L t0, VCPU_PC(k1) LONG_L t0, VCPU_PC(k1)
mtc0 t0, CP0_EPC mtc0 t0, CP0_EPC
@ -525,7 +532,8 @@ __kvm_mips_return_to_host:
LONG_L $0, PT_R0(k1) LONG_L $0, PT_R0(k1)
LONG_L $1, PT_R1(k1) LONG_L $1, PT_R1(k1)
/* r2/v0 is the return code, shift it down by 2 (arithmetic) to recover the err code */ /* r2/v0 is the return code, shift it down by 2 (arithmetic)
* to recover the err code */
sra k0, v0, 2 sra k0, v0, 2
move $2, k0 move $2, k0
@ -635,7 +643,6 @@ LEAF(MIPSX(SyncICache))
rdhwr v0, HW_SYNCI_Step rdhwr v0, HW_SYNCI_Step
beq v0, zero, 20f beq v0, zero, 20f
nop nop
10: 10:
synci 0(a0) synci 0(a0)
addu a0, a0, v0 addu a0, a0, v0