mips/kvm: Improve code formatting in arch/mips/kvm/kvm_locore.S
No code changes, just reflowing some comments and consistently using tabs and spaces. Object code is verified to be unchanged. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Gleb Natapov <gleb@redhat.com>
This commit is contained in:
David Daney
Gleb Natapov
parent
cc2df20c7c
commit
2c07ebbd2c
1 changed files with 438 additions and 431 deletions
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@ -1,13 +1,13 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Main entry point for the guest, exception handling.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Main entry point for the guest, exception handling.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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@ -62,7 +62,7 @@ FEXPORT(__kvm_mips_vcpu_run)
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.set noat
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/* k0/k1 not being used in host kernel context */
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addiu k1,sp, -PT_SIZE
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addiu k1, sp, -PT_SIZE
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LONG_S $0, PT_R0(k1)
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LONG_S $1, PT_R1(k1)
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LONG_S $2, PT_R2(k1)
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@ -111,7 +111,7 @@ FEXPORT(__kvm_mips_vcpu_run)
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LONG_S v0, PT_STATUS(k1)
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/* Save host ASID, shove it into the BVADDR location */
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mfc0 v1,CP0_ENTRYHI
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mfc0 v1, CP0_ENTRYHI
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andi v1, 0xff
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LONG_S v1, PT_HOST_ASID(k1)
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@ -120,33 +120,38 @@ FEXPORT(__kvm_mips_vcpu_run)
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LONG_S v1, PT_HOST_USERLOCAL(k1)
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/* DDATA_LO has pointer to vcpu */
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mtc0 a1,CP0_DDATA_LO
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mtc0 a1, CP0_DDATA_LO
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/* Offset into vcpu->arch */
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addiu k1, a1, VCPU_HOST_ARCH
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/* Save the host stack to VCPU, used for exception processing when we exit from the Guest */
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/*
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* Save the host stack to VCPU, used for exception processing
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* when we exit from the Guest
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*/
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LONG_S sp, VCPU_HOST_STACK(k1)
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/* Save the kernel gp as well */
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LONG_S gp, VCPU_HOST_GP(k1)
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/* Setup status register for running the guest in UM, interrupts are disabled */
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li k0,(ST0_EXL | KSU_USER| ST0_BEV)
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mtc0 k0,CP0_STATUS
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li k0, (ST0_EXL | KSU_USER | ST0_BEV)
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mtc0 k0, CP0_STATUS
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ehb
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/* load up the new EBASE */
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LONG_L k0, VCPU_GUEST_EBASE(k1)
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mtc0 k0,CP0_EBASE
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mtc0 k0, CP0_EBASE
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/* Now that the new EBASE has been loaded, unset BEV, set interrupt mask as it was
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* but make sure that timer interrupts are enabled
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/*
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* Now that the new EBASE has been loaded, unset BEV, set
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* interrupt mask as it was but make sure that timer interrupts
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* are enabled
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*/
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li k0,(ST0_EXL | KSU_USER | ST0_IE)
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li k0, (ST0_EXL | KSU_USER | ST0_IE)
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andi v0, v0, ST0_IM
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or k0, k0, v0
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mtc0 k0,CP0_STATUS
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mtc0 k0, CP0_STATUS
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ehb
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@ -168,7 +173,7 @@ FEXPORT(__kvm_mips_load_asid)
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addu t3, t1, t2
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LONG_L k0, (t3)
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andi k0, k0, 0xff
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mtc0 k0,CP0_ENTRYHI
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mtc0 k0, CP0_ENTRYHI
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ehb
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/* Disable RDHWR access */
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@ -279,7 +284,7 @@ NESTED (MIPSX(GuestException), CALLFRAME_SIZ, ra)
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LONG_S $14, VCPU_R14(k1)
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LONG_S $15, VCPU_R15(k1)
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LONG_S $16, VCPU_R16(k1)
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LONG_S $17,VCPU_R17(k1)
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LONG_S $17, VCPU_R17(k1)
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LONG_S $18, VCPU_R18(k1)
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LONG_S $19, VCPU_R19(k1)
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LONG_S $20, VCPU_R20(k1)
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@ -327,8 +332,8 @@ NESTED (MIPSX(GuestException), CALLFRAME_SIZ, ra)
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/* Save pointer to run in s0, will be saved by the compiler */
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move s0, a0
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/* Save Host level EPC, BadVaddr and Cause to VCPU, useful to process the exception */
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/* Save Host level EPC, BadVaddr and Cause to VCPU, useful to
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* process the exception */
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mfc0 k0,CP0_EPC
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LONG_S k0, VCPU_PC(k1)
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@ -373,7 +378,7 @@ NESTED (MIPSX(GuestException), CALLFRAME_SIZ, ra)
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LONG_L sp, VCPU_HOST_STACK(k1)
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/* Saved host state */
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addiu sp,sp, -PT_SIZE
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addiu sp, sp, -PT_SIZE
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/* XXXKYMA do we need to load the host ASID, maybe not because the
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* kernel entries are marked GLOBAL, need to verify
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@ -389,24 +394,27 @@ NESTED (MIPSX(GuestException), CALLFRAME_SIZ, ra)
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/* Jump to handler */
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FEXPORT(__kvm_mips_jump_to_handler)
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/* XXXKYMA: not sure if this is safe, how large is the stack?? */
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/* Now jump to the kvm_mips_handle_exit() to see if we can deal with this in the kernel */
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la t9,kvm_mips_handle_exit
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/* XXXKYMA: not sure if this is safe, how large is the stack??
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* Now jump to the kvm_mips_handle_exit() to see if we can deal
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* with this in the kernel */
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la t9, kvm_mips_handle_exit
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jalr.hb t9
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addiu sp,sp, -CALLFRAME_SIZ /* BD Slot */
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addiu sp, sp, -CALLFRAME_SIZ /* BD Slot */
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/* Return from handler Make sure interrupts are disabled */
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di
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ehb
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/* XXXKYMA: k0/k1 could have been blown away if we processed an exception
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* while we were handling the exception from the guest, reload k1
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/* XXXKYMA: k0/k1 could have been blown away if we processed
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* an exception while we were handling the exception from the
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* guest, reload k1
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*/
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move k1, s1
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addiu k1, k1, VCPU_HOST_ARCH
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/* Check return value, should tell us if we are returning to the host (handle I/O etc)
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* or resuming the guest
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/* Check return value, should tell us if we are returning to the
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* host (handle I/O etc)or resuming the guest
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*/
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andi t0, v0, RESUME_HOST
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bnez t0, __kvm_mips_return_to_host
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@ -426,7 +434,7 @@ __kvm_mips_return_to_guest:
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.set noat
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mtc0 k0, CP0_STATUS
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ehb
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mtc0 t0,CP0_EBASE
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mtc0 t0, CP0_EBASE
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/* Setup status register for running guest in UM */
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.set at
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@ -436,7 +444,6 @@ __kvm_mips_return_to_guest:
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mtc0 v1, CP0_STATUS
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ehb
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/* Set Guest EPC */
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LONG_L t0, VCPU_PC(k1)
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mtc0 t0, CP0_EPC
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@ -525,7 +532,8 @@ __kvm_mips_return_to_host:
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LONG_L $0, PT_R0(k1)
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LONG_L $1, PT_R1(k1)
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/* r2/v0 is the return code, shift it down by 2 (arithmetic) to recover the err code */
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/* r2/v0 is the return code, shift it down by 2 (arithmetic)
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* to recover the err code */
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sra k0, v0, 2
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move $2, k0
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@ -635,7 +643,6 @@ LEAF(MIPSX(SyncICache))
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rdhwr v0, HW_SYNCI_Step
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beq v0, zero, 20f
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nop
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10:
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synci 0(a0)
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addu a0, a0, v0
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