From 2ceb2d0ec04ea4eff858f594753941c1378a0b34 Mon Sep 17 00:00:00 2001 From: Padmanabhan Komanduru Date: Mon, 17 Nov 2014 13:22:47 +0530 Subject: [PATCH] msm: mdss: avoid corner cases with DSI_INT_CTRL register read/write To enable/disable a particular interrupt mask for DSI, we currently read the DSI_INT_CTRL register and add/remove the interrupt mask on top of the current register value. With this approach, we sometimes clear some interrupts without handling them. Handle this case by writing back only the required interrupt mask bits to the DSI_INT_CTRL register. Below is an instance of such issue when a DSI register read operation is performed. <3>[ 342.509070] mdss_dsi_isr: ndx=0 isr=3200002 -> At first, DSI error interrupt is received. <3>[ 342.512239] mdss_dsi_err_intr_ctrl: intr=1310003 enable=0 -> During DSI_INT_CTRL read/write operation, we clear the CMD_DMA_DONE interrupt which arrives few milli seconds after DSI error interrupt. <3>[ 342.517620] mdss_dsi_fifo_status: status=44441000 <3>[ 342.522351] mdss_dsi_timeout_status: status=1 <3>[ 342.526980] mdss_dsi_err_intr_ctrl: intr=3210002 enable=1 <3>[ 342.693365] mdss_dsi_cmds_rx: failed to tx cmd = 0xa -> This causes a CMD DMA timeout even though the CMD_DMA_DONE interrupt arrived. Change-Id: I82ba142d4da4ae5f4a1a2761c32b8af7964b538b Signed-off-by: Padmanabhan Komanduru --- drivers/video/fbdev/msm/mdss_dsi.h | 2 ++ drivers/video/fbdev/msm/mdss_dsi_host.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/video/fbdev/msm/mdss_dsi.h b/drivers/video/fbdev/msm/mdss_dsi.h index bb962ef4a7b7..54f2db5400b3 100644 --- a/drivers/video/fbdev/msm/mdss_dsi.h +++ b/drivers/video/fbdev/msm/mdss_dsi.h @@ -163,6 +163,8 @@ enum dsi_pm_type { #define DSI_INTR_CMD_MDP_DONE BIT(8) #define DSI_INTR_CMD_DMA_DONE_MASK BIT(1) #define DSI_INTR_CMD_DMA_DONE BIT(0) +/* Update this if more interrupt masks are added in future chipsets */ +#define DSI_INTR_TOTAL_MASK 0x2222AA02 #define DSI_CMD_TRIGGER_NONE 0x0 /* mdp trigger */ #define DSI_CMD_TRIGGER_TE 0x02 diff --git a/drivers/video/fbdev/msm/mdss_dsi_host.c b/drivers/video/fbdev/msm/mdss_dsi_host.c index 7f1dae75857c..146bd524ace7 100644 --- a/drivers/video/fbdev/msm/mdss_dsi_host.c +++ b/drivers/video/fbdev/msm/mdss_dsi_host.c @@ -719,6 +719,7 @@ void mdss_dsi_err_intr_ctrl(struct mdss_dsi_ctrl_pdata *ctrl, u32 mask, u32 intr; intr = MIPI_INP(ctrl->ctrl_base + 0x0110); + intr &= DSI_INTR_TOTAL_MASK; if (enable) intr |= mask; @@ -787,6 +788,7 @@ void mdss_dsi_restore_intr_mask(struct mdss_dsi_ctrl_pdata *ctrl) u32 mask; mask = MIPI_INP((ctrl->ctrl_base) + 0x0110); + mask &= DSI_INTR_TOTAL_MASK; mask |= (DSI_INTR_CMD_DMA_DONE_MASK | DSI_INTR_ERROR_MASK | DSI_INTR_BTA_DONE_MASK); MIPI_OUTP((ctrl->ctrl_base) + 0x0110, mask); @@ -1680,6 +1682,7 @@ void mdss_dsi_en_wait4dynamic_done(struct mdss_dsi_ctrl_pdata *ctrl) u32 data; /* DSI_INTL_CTRL */ data = MIPI_INP((ctrl->ctrl_base) + 0x0110); + data &= DSI_INTR_TOTAL_MASK; data |= DSI_INTR_DYNAMIC_REFRESH_MASK; MIPI_OUTP((ctrl->ctrl_base) + 0x0110, data); @@ -1695,6 +1698,7 @@ void mdss_dsi_en_wait4dynamic_done(struct mdss_dsi_ctrl_pdata *ctrl) pr_err("Dynamic interrupt timedout\n"); data = MIPI_INP((ctrl->ctrl_base) + 0x0110); + data &= DSI_INTR_TOTAL_MASK; data &= ~DSI_INTR_DYNAMIC_REFRESH_MASK; MIPI_OUTP((ctrl->ctrl_base) + 0x0110, data); } @@ -1706,6 +1710,7 @@ void mdss_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl) /* DSI_INTL_CTRL */ data = MIPI_INP((ctrl->ctrl_base) + 0x0110); + data &= DSI_INTR_TOTAL_MASK; data |= DSI_INTR_VIDEO_DONE_MASK; MIPI_OUTP((ctrl->ctrl_base) + 0x0110, data); @@ -1719,6 +1724,7 @@ void mdss_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl) msecs_to_jiffies(VSYNC_PERIOD * 4)); data = MIPI_INP((ctrl->ctrl_base) + 0x0110); + data &= DSI_INTR_TOTAL_MASK; data &= ~DSI_INTR_VIDEO_DONE_MASK; MIPI_OUTP((ctrl->ctrl_base) + 0x0110, data); }