Staging: bcm: DDRInit: fixed up some commenting issues.
I have deleated some unintelligible comments, and made a few minor white space corrections. Signed-off-by: Gary Alan Rookard Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gary Rookard
Greg Kroah-Hartman
parent
258726b350
commit
2d3fd5cabb
1 changed files with 74 additions and 75 deletions
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@ -29,17 +29,17 @@ static struct bcm_ddr_setting asT3_DDRSetting133MHz[] = {/* DPLL Clock Setting *
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{0x0F007010, 0x01000000},
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{0x0F007014, 0x01000100},
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{0x0F007018, 0x01000000},
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{0x0F00701c, 0x01020001},/* POP - 0x00020001 Normal 0x01020001 */
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{0x0F007020, 0x04030107}, /* Normal - 0x04030107 POP - 0x05030107 */
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{0x0F00701c, 0x01020001},
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{0x0F007020, 0x04030107},
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{0x0F007024, 0x02000007},
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{0x0F007028, 0x02020202},
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{0x0F00702c, 0x0206060a},/* ROB- 0x0205050a,//0x0206060a */
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{0x0F00702c, 0x0206060a},
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{0x0F007030, 0x05000000},
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{0x0F007034, 0x00000003},
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{0x0F007038, 0x110a0200},/* ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 */
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{0x0F00703C, 0x02101010},/* ROB - 0x02101010,//0x02101018}, */
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{0x0F007040, 0x45751200},/* ROB - 0x45751200,//0x450f1200}, */
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{0x0F007044, 0x110a0d00},/* ROB - 0x110a0d00//0x111f0d00 */
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{0x0F007038, 0x110a0200},
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{0x0F00703C, 0x02101010},
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{0x0F007040, 0x45751200},
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{0x0F007044, 0x110a0d00},
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{0x0F007048, 0x081b0306},
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{0x0F00704c, 0x00000000},
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{0x0F007050, 0x0000001c},
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@ -124,7 +124,6 @@ static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {/* DPLL Clock Setting *
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{0x0f000860, 0x00000000},
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{0x0f000880, 0x000003DD},
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/* Changed source for X-bar and MIPS clock to APLL */
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/* 0x0f000840,0x0FFF1800, */
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{0x0f000840, 0x0FFF1B00},
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{0x0f000870, 0x00000002},
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{0x0F00a044, 0x1fffffff},
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@ -142,8 +141,8 @@ static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {/* DPLL Clock Setting *
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{0x0F007010, 0x01000000},
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{0x0F007014, 0x01000100},
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{0x0F007018, 0x01000000},
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{0x0F00701c, 0x01020001}, /* POP - 0x00020000 Normal 0x01020000 */
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{0x0F007020, 0x04020107},/* Normal - 0x04030107 POP - 0x05030107 */
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{0x0F00701c, 0x01020001},
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{0x0F007020, 0x04020107},
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{0x0F007024, 0x00000007},
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{0x0F007028, 0x01020201},
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{0x0F00702c, 0x0204040A},
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@ -153,7 +152,7 @@ static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {/* DPLL Clock Setting *
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{0x0F00703C, 0x02030320},
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{0x0F007040, 0x6E7F1200},
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{0x0F007044, 0x01190A00},
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{0x0F007048, 0x06120305},/* 0x02690204 // 0x06120305 */
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{0x0F007048, 0x06120305},
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{0x0F00704c, 0x00000000},
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{0x0F007050, 0x0000001C},
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{0x0F007054, 0x00000000},
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@ -214,17 +213,17 @@ static struct bcm_ddr_setting asT3B_DDRSetting133MHz[] = {/* DPLL Clock Setting
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{0x0F007010, 0x01000000},
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{0x0F007014, 0x01000100},
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{0x0F007018, 0x01000000},
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{0x0F00701c, 0x01020001},/* POP - 0x00020001 Normal 0x01020001 */
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{0x0F007020, 0x04030107}, /* Normal - 0x04030107 POP - 0x05030107 */
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{0x0F00701c, 0x01020001},
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{0x0F007020, 0x04030107},
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{0x0F007024, 0x02000007},
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{0x0F007028, 0x02020202},
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{0x0F00702c, 0x0206060a},/* ROB- 0x0205050a,//0x0206060a */
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{0x0F00702c, 0x0206060a},
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{0x0F007030, 0x05000000},
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{0x0F007034, 0x00000003},
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{0x0F007038, 0x130a0200},/* ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 */
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{0x0F00703C, 0x02101012},/* ROB - 0x02101010,//0x02101018}, */
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{0x0F007040, 0x457D1200},/* ROB - 0x45751200,//0x450f1200}, */
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{0x0F007044, 0x11130d00},/*ROB - 0x110a0d00//0x111f0d00 */
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{0x0F007038, 0x130a0200},
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{0x0F00703C, 0x02101012},
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{0x0F007040, 0x457D1200},
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{0x0F007044, 0x11130d00},
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{0x0F007048, 0x040D0306},
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{0x0F00704c, 0x00000000},
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{0x0F007050, 0x0000001c},
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@ -322,8 +321,8 @@ static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {/* DPLL Clock Setting
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{0x0F007010, 0x01000000},
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{0x0F007014, 0x01000100},
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{0x0F007018, 0x01000000},
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{0x0F00701c, 0x01020000}, /* POP - 0x00020000 Normal 0x01020000 */
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{0x0F007020, 0x04020107},/* Normal - 0x04030107 POP - 0x05030107 */
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{0x0F00701c, 0x01020000},
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{0x0F007020, 0x04020107},
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{0x0F007024, 0x00000007},
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{0x0F007028, 0x01020201},
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{0x0F00702c, 0x0204040A},
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@ -333,7 +332,7 @@ static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {/* DPLL Clock Setting
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{0x0F00703C, 0x02030320},
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{0x0F007040, 0x6E7F1200},
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{0x0F007044, 0x01190A00},
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{0x0F007048, 0x06120305},/* 0x02690204 // 0x06120305 */
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{0x0F007048, 0x06120305},
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{0x0F00704c, 0x00000000},
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{0x0F007050, 0x0100001C},
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{0x0F007054, 0x00000000},
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@ -377,17 +376,17 @@ static struct bcm_ddr_setting asT3LP_DDRSetting133MHz[] = {/* DPLL Clock Setting
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{0x0F007010, 0x01000000},
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{0x0F007014, 0x01000100},
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{0x0F007018, 0x01000000},
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{0x0F00701c, 0x01020001},/* POP - 0x00020001 Normal 0x01020001 */
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{0x0F007020, 0x04030107}, /* Normal - 0x04030107 POP - 0x05030107 */
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{0x0F00701c, 0x01020001},
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{0x0F007020, 0x04030107},
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{0x0F007024, 0x02000007},
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{0x0F007028, 0x02020200},
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{0x0F00702c, 0x0206060a},/* ROB- 0x0205050a,//0x0206060a */
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{0x0F00702c, 0x0206060a},
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{0x0F007030, 0x05000000},
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{0x0F007034, 0x00000003},
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{0x0F007038, 0x200a0200},/* ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 */
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{0x0F00703C, 0x02101020},/* ROB - 0x02101010,//0x02101018, */
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{0x0F007040, 0x45711200},/* ROB - 0x45751200,//0x450f1200, */
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{0x0F007044, 0x110D0D00},/* ROB - 0x110a0d00//0x111f0d00 */
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{0x0F007038, 0x200a0200},
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{0x0F00703C, 0x02101020},
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{0x0F007040, 0x45711200},
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{0x0F007044, 0x110D0D00},
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{0x0F007048, 0x04080306},
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{0x0F00704c, 0x00000000},
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{0x0F007050, 0x0100001c},
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@ -437,17 +436,17 @@ static struct bcm_ddr_setting asT3LP_DDRSetting100MHz[] = {/* DPLL Clock Setting
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{0x0F007010, 0x01000000},
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{0x0F007014, 0x01000100},
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{0x0F007018, 0x01000000},
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{0x0F00701c, 0x01020000},/* POP - 0x00020001 Normal 0x01020001 */
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{0x0F007020, 0x04020107}, /* Normal - 0x04030107 POP - 0x05030107 */
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{0x0F00701c, 0x01020000},
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{0x0F007020, 0x04020107},
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{0x0F007024, 0x00000007},
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{0x0F007028, 0x01020200},
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{0x0F00702c, 0x0204040a},/* ROB- 0x0205050a,//0x0206060a */
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{0x0F00702c, 0x0204040a},
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{0x0F007030, 0x06000000},
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{0x0F007034, 0x00000004},
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{0x0F007038, 0x1F080200},/* ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 */
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{0x0F00703C, 0x0203031F},/* ROB - 0x02101010,//0x02101018, */
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{0x0F007040, 0x6e001200},/* ROB - 0x45751200,//0x450f1200, */
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{0x0F007044, 0x011a0a00},/* ROB - 0x110a0d00//0x111f0d00 */
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{0x0F007038, 0x1F080200},
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{0x0F00703C, 0x0203031F},
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{0x0F007040, 0x6e001200},
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{0x0F007044, 0x011a0a00},
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{0x0F007048, 0x03000305},
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{0x0F00704c, 0x00000000},
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{0x0F007050, 0x0100001c},
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@ -615,17 +614,17 @@ static struct bcm_ddr_setting asT3LPB_DDRSetting133MHz[] = {/* DPLL Clock Settin
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{0x0F007010, 0x01000000},
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{0x0F007014, 0x01000100},
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{0x0F007018, 0x01000000},
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{0x0F00701c, 0x01020001},/* POP - 0x00020001 Normal 0x01020001 */
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{0x0F007020, 0x04030107}, /* Normal - 0x04030107 POP - 0x05030107 */
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{0x0F00701c, 0x01020001},
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{0x0F007020, 0x04030107},
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{0x0F007024, 0x02000007},
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{0x0F007028, 0x02020200},
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{0x0F00702c, 0x0206060a},/* ROB- 0x0205050a,//0x0206060a */
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{0x0F00702c, 0x0206060a},
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{0x0F007030, 0x05000000},
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{0x0F007034, 0x00000003},
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{0x0F007038, 0x190a0200},/* ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 */
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{0x0F00703C, 0x02101017},/* ROB - 0x02101010,//0x02101018, */
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{0x0F007040, 0x45171200},/* ROB - 0x45751200,//0x450f1200, */
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{0x0F007044, 0x11290D00},/* ROB - 0x110a0d00//0x111f0d00 */
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{0x0F007038, 0x190a0200},
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{0x0F00703C, 0x02101017},
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{0x0F007040, 0x45171200},
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{0x0F007044, 0x11290D00},
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{0x0F007048, 0x04080306},
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{0x0F00704c, 0x00000000},
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{0x0F007050, 0x0100001c},
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@ -676,17 +675,17 @@ static struct bcm_ddr_setting asT3LPB_DDRSetting100MHz[] = {/* DPLL Clock Settin
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{0x0F007010, 0x01000000},
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{0x0F007014, 0x01000100},
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{0x0F007018, 0x01000000},
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{0x0F00701c, 0x01020000},/* POP - 0x00020001 Normal 0x01020001 */
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{0x0F007020, 0x04020107}, /* Normal - 0x04030107 POP - 0x05030107 */
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{0x0F00701c, 0x01020000},
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{0x0F007020, 0x04020107},
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{0x0F007024, 0x00000007},
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{0x0F007028, 0x01020200},
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{0x0F00702c, 0x0204040a},/* ROB- 0x0205050a,//0x0206060a */
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{0x0F00702c, 0x0204040a},
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{0x0F007030, 0x06000000},
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{0x0F007034, 0x00000004},
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{0x0F007038, 0x1F080200},/* ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 */
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{0x0F00703C, 0x0203031F},/* ROB - 0x02101010,//0x02101018, */
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{0x0F007040, 0x6e001200},/* ROB - 0x45751200,//0x450f1200, */
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{0x0F007044, 0x011a0a00},/* ROB - 0x110a0d00//0x111f0d00 */
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{0x0F007038, 0x1F080200},
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{0x0F00703C, 0x0203031F},
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{0x0F007040, 0x6e001200},
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{0x0F007044, 0x011a0a00},
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{0x0F007048, 0x03000305},
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{0x0F00704c, 0x00000000},
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{0x0F007050, 0x0100001c},
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