From 7b2f8ee7696e33566aa8e3ed523d70994184c7bc Mon Sep 17 00:00:00 2001 From: Prasad Sodagudi Date: Thu, 12 Jan 2017 10:11:39 -0800 Subject: [PATCH 1/2] arm64: Potential rollover condition for timer counter There is potential rollover condition for CNTVCT and CNTPCT counters. So on any architecture timer counter read, if the least significant 32 bits are set, reread counter. CRs-Fixed: 1074621 Change-Id: I136a5f0ee04deeb74c03800d591e44fbd9b4dd39 Signed-off-by: Prasad Sodagudi --- arch/arm64/include/asm/arch_timer.h | 7 +++++++ drivers/clocksource/Kconfig | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index fbe0ca31a99c..09eb5b463635 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -119,7 +119,14 @@ static inline u64 arch_counter_get_cntvct(void) u64 cval; isb(); +#if IS_ENABLED(CONFIG_MSM_TIMER_LEAP) +#define L32_BITS 0x00000000FFFFFFFF + do { + asm volatile("mrs %0, cntvct_el0" : "=r" (cval)); + } while ((cval & L32_BITS) == L32_BITS); +#else asm volatile("mrs %0, cntvct_el0" : "=r" (cval)); +#endif return cval; } diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 2eb5f0efae90..8bf3355e95db 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -158,6 +158,15 @@ config ARM_ARCH_TIMER_EVTSTREAM This must be disabled for hardware validation purposes to detect any hardware anomalies of missing events. +config MSM_TIMER_LEAP + bool "ARCH TIMER counter rollover" + default n + depends on ARM_ARCH_TIMER && ARM64 + help + This option enables a check for least significant 32 bits of + counter rollover. On every counter read if least significant + 32 bits are set, reread counter. + config ARM_GLOBAL_TIMER bool select CLKSRC_OF if OF From 15074fffc8470f1b9f4df8b83aafc0d50fad0a17 Mon Sep 17 00:00:00 2001 From: Prasad Sodagudi Date: Fri, 13 Jan 2017 18:03:58 -0800 Subject: [PATCH 2/2] defconfig: msm: Enable MSM_TIMER_LEAP Enable MSM_TIMER_LEAP config flag in both msmcortex_defocnfig and msmcorte-perf_defconfig files. This option enables check for architecture timer leaps, when all least significant 32bits of CNTVCT or CNTPCT counter is set and rereads counters. CRs-Fixed: 1074621 Change-Id: I0ffa124df76f8cc063c2ebee5497baed879c76ef Signed-off-by: Prasad Sodagudi --- arch/arm64/configs/msmcortex-perf_defconfig | 1 + arch/arm64/configs/msmcortex_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/msmcortex-perf_defconfig b/arch/arm64/configs/msmcortex-perf_defconfig index 7c34ea8caba1..9700145bfdf6 100644 --- a/arch/arm64/configs/msmcortex-perf_defconfig +++ b/arch/arm64/configs/msmcortex-perf_defconfig @@ -496,6 +496,7 @@ CONFIG_SEEMP_CORE=y CONFIG_USB_BAM=y CONFIG_MSM_MDSS_PLL=y CONFIG_REMOTE_SPINLOCK_MSM=y +CONFIG_MSM_TIMER_LEAP=y CONFIG_IOMMU_IO_PGTABLE_FAST=y CONFIG_ARM_SMMU=y CONFIG_IOMMU_DEBUG=y diff --git a/arch/arm64/configs/msmcortex_defconfig b/arch/arm64/configs/msmcortex_defconfig index 9d7baa24e271..77b5390fd384 100644 --- a/arch/arm64/configs/msmcortex_defconfig +++ b/arch/arm64/configs/msmcortex_defconfig @@ -505,6 +505,7 @@ CONFIG_SEEMP_CORE=y CONFIG_USB_BAM=y CONFIG_MSM_MDSS_PLL=y CONFIG_REMOTE_SPINLOCK_MSM=y +CONFIG_MSM_TIMER_LEAP=y CONFIG_IOMMU_IO_PGTABLE_FAST=y CONFIG_IOMMU_IO_PGTABLE_FAST_SELFTEST=y CONFIG_ARM_SMMU=y