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ARM: dts: msm: add devfreq nodes to msmfalcon target

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Add devfreq DCVS nodes mincpu, cpubw, memlat to msmfalcon
target.

Change-Id: I29572841624c1cb96d85e2dcfe620b455867d41e
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
This commit is contained in:
Santosh Mardi 2016-12-22 15:02:11 +05:30
parent e379f786aa
commit 2e89457a54
1 changed files with 130 additions and 0 deletions
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130
arch/arm/boot/dts/qcom/msmfalcon.dtsi
View file

@ -952,6 +952,136 @@
#clock-cells = <1>;
};
cpubw: qcom,cpubw {
compatible = "qcom,devbw";
governor = "performance";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 762 /* 100 MHz */ >,
< 1144 /* 150 MHz */ >,
< 1525 /* 200 MHz */ >,
< 2288 /* 300 MHz */ >,
< 3143 /* 412 MHz */ >,
< 4173 /* 547 MHz */ >,
< 5195 /* 681 MHz */ >,
< 5859 /* 768 MHz */ >,
< 7759 /* 1017 MHz */ >,
< 9887 /* 1296 MHz */ >,
< 10327 /* 1353 MHz */ >,
< 11863 /* 1555 MHz */ >,
< 13763 /* 1804 MHz */ >;
};
bwmon: qcom,cpu-bwmon {
compatible = "qcom,bimc-bwmon3";
reg = <0x01008000 0x300>, <0x01001000 0x200>;
reg-names = "base", "global_base";
interrupts = <0 183 4>;
qcom,mport = <0>;
qcom,target-dev = <&cpubw>;
};
mincpubw: qcom,mincpubw {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 762 /* 100 MHz */ >,
< 1144 /* 150 MHz */ >,
< 1525 /* 200 MHz */ >,
< 2288 /* 300 MHz */ >,
< 3143 /* 412 MHz */ >,
< 4173 /* 547 MHz */ >,
< 5195 /* 681 MHz */ >,
< 5859 /* 768 MHz */ >,
< 7759 /* 1017 MHz */ >,
< 9887 /* 1296 MHz */ >,
< 10327 /* 1353 MHz */ >,
< 11863 /* 1555 MHz */ >,
< 13763 /* 1804 MHz */ >;
};
memlat_cpu0: qcom,memlat-cpu0 {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 762 /* 100 MHz */ >,
< 1144 /* 150 MHz */ >,
< 1525 /* 200 MHz */ >,
< 2288 /* 300 MHz */ >,
< 3143 /* 412 MHz */ >,
< 4173 /* 547 MHz */ >,
< 5195 /* 681 MHz */ >,
< 5859 /* 768 MHz */ >,
< 7759 /* 1017 MHz */ >,
< 9887 /* 1296 MHz */ >,
< 10327 /* 1353 MHz */ >,
< 11863 /* 1555 MHz */ >,
< 13763 /* 1804 MHz */ >;
};
memlat_cpu4: qcom,memlat-cpu4 {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 762 /* 100 MHz */ >,
< 1144 /* 150 MHz */ >,
< 1525 /* 200 MHz */ >,
< 2288 /* 300 MHz */ >,
< 3143 /* 412 MHz */ >,
< 4173 /* 547 MHz */ >,
< 5195 /* 681 MHz */ >,
< 5859 /* 768 MHz */ >,
< 7759 /* 1017 MHz */ >,
< 9887 /* 1296 MHz */ >,
< 10327 /* 1353 MHz */ >,
< 11863 /* 1555 MHz */ >,
< 13763 /* 1804 MHz */ >;
};
devfreq_memlat_0: qcom,arm-memlat-mon-0 {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,target-dev = <&memlat_cpu0>;
qcom,core-dev-table =
< 633600 1525 >,
< 1401600 4173 >,
< 1881600 7759 >;
};
devfreq_memlat_4: qcom,arm-memlat-mon-4 {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,target-dev = <&memlat_cpu4>;
qcom,core-dev-table =
< 1113600 1525 >,
< 1401600 7759 >,
< 2150400 11863 >,
< 2457600 13763 >;
};
devfreq_cpufreq: devfreq-cpufreq {
mincpubw-cpufreq {
target-dev = <&mincpubw>;
cpu-to-dev-map-0 =
< 633600 1525 >,
< 1401600 3143 >,
< 1881600 5859 >;
cpu-to-dev-map-4 =
< 1113600 1525 >,
< 1401600 4173 >,
< 1747200 5859 >,
< 2150400 7759 >,
< 2457600 13763 >;
};
};
sdhc_1: sdhci@c0c4000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>;