evie/android_kernel_oneplus_msm8998
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msm: mdss: remove timing db mode from DSI host init sequence

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In the current implementation DSI timing db(Double Buffering)
mode is set as part of DSI controller initialization. This is
causing DSI command transfer failures when sending panel init
commands during device resume for some platforms like SDM660.
Since on these platforms DSI_CMD_OFFSET and DSI_CMD_LENGTH
register has now become double buffered and hence would need a
control flush, for these registers to take effect. But control
flush in driver does not happen until panel init is done properly.
So removing the programing of timing db registers from DSI host
initialization sequence as this is already taken care during dynamic
refresh rate change usecase.

Change-Id: Ia08788127f4d132530e3f3a28efd9d7ee9869483
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
This commit is contained in:
Sandeep Panda 2017-01-10 14:12:28 +05:30
parent a6d83d2e8e
commit 2eb4e731c5
1 changed files with 0 additions and 4 deletions
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4
drivers/video/fbdev/msm/mdss_dsi_host.c
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@ -1343,8 +1343,6 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata)
vsync_period = vspw + vbp + height + dummy_yres + vfp;
hsync_period = hspw + hbp + width + dummy_xres + hfp;
if (ctrl_pdata->timing_db_mode)
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e8, 0x1);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x24,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
@ -1358,8 +1356,6 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata)
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x30, (hspw << 16));
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x34, 0);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x38, (vspw << 16));
if (ctrl_pdata->timing_db_mode)
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e4, 0x1);
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;