sdhci: msm: add support for new vendor capabilities

Add support for new vendor capabilities on the msm
sdhci controller.

Change-Id: I934e35de4c566c9ba351e39d6eab3d88ae61a4d0
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
[subhashj@codeaurora.org: fix trivial merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This commit is contained in:
Abhimanyu Kapur 2014-09-10 17:27:43 -07:00 committed by Subhash Jadavani
parent ef99192336
commit 2edac2000f

View file

@ -50,6 +50,10 @@
#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
#define CORE_8_BIT_SUPPORT (1 << 18)
#define CORE_3_0V_SUPPORT (1 << 25)
#define CDR_SELEXT_SHIFT 20
#define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
#define CMUX_SHIFT_PHASE_SHIFT 24
@ -582,6 +586,10 @@ static int sdhci_msm_probe(struct platform_device *pdev)
/* Set HC_MODE_EN bit in HC_MODE register */
writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
writel_relaxed((readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES) |
CORE_3_0V_SUPPORT | CORE_8_BIT_SUPPORT),
host->ioaddr + CORE_VENDOR_SPEC_CAPABILITIES0);
host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
host->quirks |= SDHCI_QUIRK_SINGLE_POWER_WRITE;