evie/android_kernel_oneplus_msm8998
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msm: mdss: add mdp clock calculations for BWC decode

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BWC decode works at 2 pixels/clk and MDP clock requirement needs to be
adjusted to account for this. If BWC decode is enabled and MDP clock is
not sufficient then real-time pipeline might suffer from throughput
delays and might result in under-runs. Prevent this by calculating MDP
clock rate when BWC decode is needed and then choose max MDP clock rate
by comparing normal MDP clock and bwc MDP clock.

Change-Id: I92afc5a3c7ec29602ffdeec1ada0d67c57c4497f
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
This commit is contained in:
Ujwal Patel 2014-09-30 11:02:25 -07:00 • committed by David Keitel
parent 270c727b29
commit 2fe10db9d2
1 changed files with 11 additions and 0 deletions
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11
drivers/video/fbdev/msm/mdss_mdp_ctl.c
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@ -529,6 +529,17 @@ int mdss_mdp_perf_calc_pipe(struct mdss_mdp_pipe *pipe,
rate = (rate * src_h) / dst.h;
rate *= v_total * fps;
/* pipes decoding BWC content have different clk requirement */
if (pipe->bwc_mode && !pipe->src_fmt->is_yuv &&
pipe->src_fmt->bpp == 4) {
u32 bwc_rate =
mult_frac((src.w * src_h * fps), v_total, dst.h << 1);
pr_debug("src: w:%d h:%d fps:%d vtotal:%d dst h:%d\n",
src.w, src_h, fps, v_total, dst.h);
pr_debug("pipe%d: bwc_rate=%d normal_rate=%d\n",
pipe->num, bwc_rate, rate);
rate = max(bwc_rate, rate);
}
quota = mult_frac(quota, v_total, dst.h);
if (!mixer->ctl->is_video_mode)