evie/android_kernel_oneplus_msm8998
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ARM: qcom: scm: Get cacheline size from CTR

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Instead of hardcoding the cacheline size as 32, get the cacheline size from
the CTR register.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
This commit is contained in:
Stephen Boyd 2014-08-04 18:31:44 -07:00 • committed by Kumar Gala
parent f76c691657
commit 30cbb0c01b
1 changed files with 8 additions and 6 deletions
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14
arch/arm/mach-qcom/scm.c
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@ -27,9 +27,6 @@
#include "scm.h" #include "scm.h"
/* Cache line size for msm8x60 */
#define CACHELINESIZE 32
#define SCM_ENOMEM -5 #define SCM_ENOMEM -5
#define SCM_EOPNOTSUPP -4 #define SCM_EOPNOTSUPP -4
#define SCM_EINVAL_ADDR -3 #define SCM_EINVAL_ADDR -3
@ -214,13 +211,18 @@ static int __scm_call(const struct scm_command *cmd)
static void scm_inv_range(unsigned long start, unsigned long end) static void scm_inv_range(unsigned long start, unsigned long end)
{ {
start = round_down(start, CACHELINESIZE); u32 cacheline_size, ctr;
end = round_up(end, CACHELINESIZE);
asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
cacheline_size = 4 << ((ctr >> 16) & 0xf);
start = round_down(start, cacheline_size);
end = round_up(end, cacheline_size);
outer_inv_range(start, end); outer_inv_range(start, end);
while (start < end) { while (start < end) {
asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start) asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
: "memory"); : "memory");
start += CACHELINESIZE; start += cacheline_size;
} }
dsb(); dsb();
isb(); isb();