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phy: phy-qocm-ufs: update initialization sequence for msmcobalt RUMI

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This change updates the initialization sequence of the QRBTC-V2
phy, for msmcobalt RUMI platform.

Change-Id: I369608b41e0b150334e9a7e9ad99b7cde8341dae
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
This commit is contained in:
Yaniv Gardi 2015-10-12 12:22:06 +03:00 • committed by David Keitel
parent c8d92a5e44
commit 31155086bb
2 changed files with 16 additions and 18 deletions
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31
drivers/phy/phy-qcom-ufs-qrbtc-v2.c
View file

@ -24,6 +24,16 @@ int ufs_qcom_phy_qrbtc_v2_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
int tbl_size_A;
struct ufs_qcom_phy_calibration *tbl_A;
writel_relaxed(0x15f, ufs_qcom_phy->mmio + U11_UFS_RESET_REG_OFFSET);
/* 50ms are required to stabilize the reset */
usleep_range(50000, 50100);
writel_relaxed(0x0, ufs_qcom_phy->mmio + U11_UFS_RESET_REG_OFFSET);
/* Set R3PC REF CLK */
writel_relaxed(0x80, ufs_qcom_phy->mmio + U11_QRBTC_CONTROL_OFFSET);
tbl_A = phy_cal_table_rate_A;
tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);
@ -36,6 +46,7 @@ int ufs_qcom_phy_qrbtc_v2_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
dev_err(ufs_qcom_phy->dev,
"%s: ufs_qcom_phy_calibrate() failed %d\n",
__func__, err);
return err;
}
@ -61,6 +72,8 @@ ufs_qcom_phy_qrbtc_v2_is_pcs_ready(struct ufs_qcom_phy *phy_common)
dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
__func__, err);
writel_relaxed(0x100, phy_common->mmio + U11_QRBTC_TX_CLK_CTRL);
return err;
}
@ -80,24 +93,8 @@ static void ufs_qcom_phy_qrbtc_v2_start_serdes(struct ufs_qcom_phy *phy)
static int ufs_qcom_phy_qrbtc_v2_init(struct phy *generic_phy)
{
struct ufs_qcom_phy_qrbtc_v2 *phy = phy_get_drvdata(generic_phy);
struct ufs_qcom_phy *phy_common = &phy->common_cfg;
int err = 0;
return 0;
writel_relaxed(0x15f, phy_common->mmio + U11_UFS_RESET_REG_OFFSET);
/* 50ms are required to stabilize the reset */
usleep_range(50000, 50100);
writel_relaxed(0x0, phy_common->mmio + U11_UFS_RESET_REG_OFFSET);
/* Set R3PC REF CLK */
writel_relaxed(0x80, phy_common->mmio + U11_QRBTC_CONTROL_OFFSET);
ufs_qcom_phy_qrbtc_v2_phy_calibrate(phy_common, false);
ufs_qcom_phy_qrbtc_v2_start_serdes(phy_common);
ufs_qcom_phy_qrbtc_v2_is_pcs_ready(phy_common);
return err;
}
struct phy_ops ufs_qcom_phy_qrbtc_v2_phy_ops = {

3
drivers/phy/phy-qcom-ufs-qrbtc-v2.h
View file

@ -62,6 +62,7 @@
/* QRBTC V2 USER REGISTERS */
#define U11_UFS_RESET_REG_OFFSET PHY_USR(0x4)
#define U11_QRBTC_CONTROL_OFFSET PHY_USR(0x18)
#define U11_QRBTC_TX_CLK_CTRL PHY_USR(0x20)
static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PHY_START_OFFSET, 0x00),
@ -88,7 +89,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3B),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x0A),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x04),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PWM_CNTRL1, 0x8F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PWM_CNTRL1, 0xCF),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PWM_CNTRL2, 0x61),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PWM_NDIV, 0x4F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CDR_CONTROL, 0xF2),