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mvebu dt changes for v3.13

Browse source 
- mvebu
     - add MSI
     - new compatible string for mv64xxx-i2c
 
  - dove
     - use the pre-processor
     - define the MBus nodes
     - add PCIe controllers
     - add Globalscale D3Plug
     - relocate internal registers nodes
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Merge tag 'dt-3.13' of git://git.infradead.org/linux-mvebu into next/dt

From Jason Cooper:
mvebu dt changes for v3.13

 - mvebu
    - add MSI
    - new compatible string for mv64xxx-i2c

 - dove
    - use the pre-processor
    - define the MBus nodes
    - add PCIe controllers
    - add Globalscale D3Plug
    - relocate internal registers nodes

* tag 'dt-3.13' of git://git.infradead.org/linux-mvebu:
  ARM: dove: add initial DT file for Globalscale D3Plug
  ARM: dove: add PCIe controllers to SoC DT
  ARM: dove: relocate internal registers device nodes
  ARM: dove: add MBus DT node
  ARM: dove: add MBUS_ID macro to Dove DT
  ARM: dove: use preprocessor on device tree files
  ARM: mvebu: link PCIe controllers to the MSI controller
  ARM: mvebu: the MPIC now provides MSI controller features
  ARM: dts: mvebu: Update with the new compatible string for mv64xxx-i2c

Signed-off-by: Kevin Hilman <khilman@linaro.org>
This commit is contained in:
Kevin Hilman 2013-10-09 13:21:51 -07:00
commit 3197e4a123
13 changed files with 649 additions and 455 deletions
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1
arch/arm/boot/dts/Makefile
View file

@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
dove-cubox.dtb \
dove-d2plug.dtb \
dove-d3plug.dtb \
dove-dove-db.dtb
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \

3
arch/arm/boot/dts/armada-370-xp.dtsi
View file

@ -113,6 +113,7 @@
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
msi-controller;
};
coherency-fabric@20200 {
@ -176,7 +177,6 @@
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <31>;
@ -187,7 +187,6 @@
i2c1: i2c@11100 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <32>;

9
arch/arm/boot/dts/armada-370.dtsi
View file

@ -44,6 +44,7 @@
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&mpic>;
bus-range = <0x00 0xff>;
ranges =
@ -218,6 +219,14 @@
};
};
i2c0: i2c@11000 {
reg = <0x11000 0x20>;
};
i2c1: i2c@11100 {
reg = <0x11100 0x20>;
};
usb@50000 {
clocks = <&coreclk 0>;
};

1
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View file

@ -57,6 +57,7 @@
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&mpic>;
bus-range = <0x00 0xff>;
ranges =

1
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View file

@ -58,6 +58,7 @@
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&mpic>;
bus-range = <0x00 0xff>;
ranges =

1
arch/arm/boot/dts/armada-xp-mv78460.dtsi
View file

@ -74,6 +74,7 @@
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&mpic>;
bus-range = <0x00 0xff>;
ranges =

10
arch/arm/boot/dts/armada-xp.dtsi
View file

@ -145,6 +145,16 @@
};
};
i2c0: i2c@11000 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
i2c1: i2c@11100 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};
usb@50000 {
clocks = <&gateclk 18>;
};

2
arch/arm/boot/dts/dove-cm-a510.dts
View file

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "dove.dtsi"
#include "dove.dtsi"
/ {
model = "Compulab CM-A510";

2
arch/arm/boot/dts/dove-cubox.dts
View file

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "dove.dtsi"
#include "dove.dtsi"
/ {
model = "SolidRun CuBox";

2
arch/arm/boot/dts/dove-d2plug.dts
View file

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "dove.dtsi"
#include "dove.dtsi"
/ {
model = "Globalscale D2Plug";

103
arch/arm/boot/dts/dove-d3plug.dts Normal file
View file

@ -0,0 +1,103 @@
/dts-v1/;
#include "dove.dtsi"
/ {
model = "Globalscale D3Plug";
compatible = "globalscale,d3plug", "marvell,dove";
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p2 rw rootwait";
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>;
pinctrl-names = "default";
wlan-act {
label = "wlan-act";
gpios = <&gpio0 0 1>;
};
wlan-ap {
label = "wlan-ap";
gpios = <&gpio0 1 1>;
};
status {
label = "status";
gpios = <&gpio0 2 1>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
usb_power: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "USB Power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 8 0>;
pinctrl-0 = <&pmx_gpio_8>;
pinctrl-names = "default";
};
};
};
&uart0 { status = "okay"; };
&sata0 { status = "okay"; };
&i2c0 { status = "okay"; };
/* Samsung M8G2F eMMC */
&sdio0 {
status = "okay";
non-removable;
bus-width = <4>;
};
/* Marvell SD8787 WLAN/BT */
&sdio1 {
status = "okay";
non-removable;
};
&spi0 {
status = "okay";
/* spi0.0: 2M Flash Macronix MX25L1605D */
spi-flash@0 {
compatible = "st,m25l1605d";
spi-max-frequency = <86000000>;
reg = <0>;
};
};
&pcie {
status = "okay";
/* Fresco Logic USB3.0 xHCI controller */
pcie-port@0 {
status = "okay";
reset-gpios = <&gpio0 26 1>;
reset-delay-us = <20000>;
pinctrl-0 = <&pmx_camera_gpio>;
pinctrl-names = "default";
};
/* Mini-PCIe slot */
pcie-port@1 {
status = "okay";
reset-gpios = <&gpio0 25 1>;
};
};

2
arch/arm/boot/dts/dove-dove-db.dts
View file

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "dove.dtsi"
#include "dove.dtsi"
/ {
model = "Marvell DB-MV88AP510-BP Development Board";

97
arch/arm/boot/dts/dove.dtsi
View file

@ -1,8 +1,11 @@
/include/ "skeleton.dtsi"
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
compatible = "marvell,dove";
model = "Marvell Armada 88AP510 SoC";
interrupt-parent = <&intc>;
aliases {
gpio0 = &gpio0;
@ -27,20 +30,87 @@
marvell,tauros2-cache-features = <0>;
};
soc@f1000000 {
mbus {
compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
pcie: pcie-controller {
compatible = "marvell,dove-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&intc>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
pcie-port@0 {
device_type = "pci";
status = "disabled";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
clocks = <&gate_clk 4>;
marvell,pcie-port = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 16>;
};
pcie-port@1 {
device_type = "pci";
status = "disabled";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
clocks = <&gate_clk 5>;
marvell,pcie-port = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 18>;
};
};
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
mbusc: mbus-ctrl@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x80>, <0x800100 0x8>;
};
timer: timer@20300 {
compatible = "marvell,orion-timer";
@ -422,7 +492,7 @@
crypto: crypto-engine@30000 {
compatible = "marvell,orion-crypto";
reg = <0x30000 0x10000>,
<0xc8000000 0x800>;
<0xffffe000 0x800>;
reg-names = "regs", "sram";
interrupts = <31>;
clocks = <&gate_clk 15>;
@ -444,7 +514,6 @@
channel1 {
interrupts = <40>;
dmacap,memset;
dmacap,memcpy;
dmacap,xor;
};
@ -465,7 +534,6 @@
channel1 {
interrupts = <43>;
dmacap,memset;
dmacap,memcpy;
dmacap,xor;
};
@ -486,7 +554,7 @@
};
};
eth: ethernet-controller@72000 {
eth: ethernet-ctrl@72000 {
compatible = "marvell,orion-eth";
#address-cells = <1>;
#size-cells = <0>;
@ -506,4 +574,5 @@
};
};
};
};
};