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[IA64] Add dp bit to cache and bus check structs

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Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's
Manual" (January 2006) adds a dp bit to the cache_check and bus_check
fields (pages 2:401-2:404).  This patch gets the structs back in sync
with the spec.

Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Russ Anderson 2006-10-25 14:18:27 -05:00 • committed by Tony Luck
parent c69577711a
commit 323cbb0991
1 changed files with 5 additions and 3 deletions
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8
include/asm-ia64/pal.h
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@ -487,10 +487,12 @@ typedef struct pal_cache_check_info_s {
* error occurred * error occurred
*/ */
wiv : 1, /* Way field valid */ wiv : 1, /* Way field valid */
reserved2 : 10, reserved2 : 1,
dp : 1, /* Data poisoned on MBE */
reserved3 : 8,
index : 20, /* Cache line index */ index : 20, /* Cache line index */
reserved3 : 2, reserved4 : 2,
is : 1, /* instruction set (1 == ia32) */ is : 1, /* instruction set (1 == ia32) */
iv : 1, /* instruction set field valid */ iv : 1, /* instruction set field valid */
@ -557,7 +559,7 @@ typedef struct pal_bus_check_info_s {
type : 8, /* Bus xaction type*/ type : 8, /* Bus xaction type*/
sev : 5, /* Bus error severity*/ sev : 5, /* Bus error severity*/
hier : 2, /* Bus hierarchy level */ hier : 2, /* Bus hierarchy level */
reserved1 : 1, dp : 1, /* Data poisoned on MBE */
bsi : 8, /* Bus error status bsi : 8, /* Bus error status
* info * info
*/ */