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Revert "iommu/arm-smmu: add DT option to avoid enabling translations on attach"

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This reverts commit 5642406b6c3e
("iommu/arm-smmu: add DT option to avoid enabling translations on attach")

This device tree option is obsolete. Remove it.

Change-Id: I6fc2e3127295b9b597acc21ef5d6b1f78519de68
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
This commit is contained in:
Patrick Daly 2016-03-16 18:48:02 -07:00 • committed by David Keitel
parent 2cf0c8e08a
commit 33c174483b
2 changed files with 1 additions and 17 deletions
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12
Documentation/devicetree/bindings/iommu/arm,smmu.txt
View file

@ -92,18 +92,6 @@ conditions.
Thulium v1. You *must* also set qcom,tz-device-id for Thulium v1. You *must* also set qcom,tz-device-id for
this to work. this to work.
- qcom,no-mmu-enable : When attaching to this SMMU, program everything as
usual (stream matching table, etc) but leave the SCTLR.M
bit disabled, so that the SMMU doesn't actually perform
translations. This is needed in cases where the stream
matching table needs to be set up without turning on SMMU
translations (for example, when nested translations are
used with a hypervisor controlling stage-2). This mode of
operation is described in the ARM SMMU spec as "stage 1
and stage 2 contexts are valid, but the SMMU is not
enabled for stage 1 translation" (Section 2.1: "Overview
of SMMU operation").
- qcom,no-smr-check : Usually when an SMMU probes we do a sanity check on - qcom,no-smr-check : Usually when an SMMU probes we do a sanity check on
the SMR registers to make sure they can fully support all the SMR registers to make sure they can fully support all
of the mask bits. This check can cause problems for use of the mask bits. This check can cause problems for use

6
drivers/iommu/arm-smmu.c
View file

@ -361,7 +361,6 @@ struct arm_smmu_device {
#define ARM_SMMU_OPT_ERRATA_CTX_FAULT_HANG (1 << 5) #define ARM_SMMU_OPT_ERRATA_CTX_FAULT_HANG (1 << 5)
#define ARM_SMMU_OPT_FATAL_ASF (1 << 6) #define ARM_SMMU_OPT_FATAL_ASF (1 << 6)
#define ARM_SMMU_OPT_ERRATA_TZ_ATOS (1 << 7) #define ARM_SMMU_OPT_ERRATA_TZ_ATOS (1 << 7)
#define ARM_SMMU_OPT_NO_M (1 << 8)
#define ARM_SMMU_OPT_NO_SMR_CHECK (1 << 9) #define ARM_SMMU_OPT_NO_SMR_CHECK (1 << 9)
#define ARM_SMMU_OPT_DYNAMIC (1 << 10) #define ARM_SMMU_OPT_DYNAMIC (1 << 10)
#define ARM_SMMU_OPT_HALT (1 << 11) #define ARM_SMMU_OPT_HALT (1 << 11)
@ -484,7 +483,6 @@ static struct arm_smmu_option_prop arm_smmu_options[] = {
{ ARM_SMMU_OPT_ERRATA_CTX_FAULT_HANG, "qcom,errata-ctx-fault-hang" }, { ARM_SMMU_OPT_ERRATA_CTX_FAULT_HANG, "qcom,errata-ctx-fault-hang" },
{ ARM_SMMU_OPT_FATAL_ASF, "qcom,fatal-asf" }, { ARM_SMMU_OPT_FATAL_ASF, "qcom,fatal-asf" },
{ ARM_SMMU_OPT_ERRATA_TZ_ATOS, "qcom,errata-tz-atos" }, { ARM_SMMU_OPT_ERRATA_TZ_ATOS, "qcom,errata-tz-atos" },
{ ARM_SMMU_OPT_NO_M, "qcom,no-mmu-enable" },
{ ARM_SMMU_OPT_NO_SMR_CHECK, "qcom,no-smr-check" }, { ARM_SMMU_OPT_NO_SMR_CHECK, "qcom,no-smr-check" },
{ ARM_SMMU_OPT_DYNAMIC, "qcom,dynamic" }, { ARM_SMMU_OPT_DYNAMIC, "qcom,dynamic" },
{ ARM_SMMU_OPT_HALT, "qcom,enable-smmu-halt"}, { ARM_SMMU_OPT_HALT, "qcom,enable-smmu-halt"},
@ -1455,9 +1453,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
} }
/* SCTLR */ /* SCTLR */
reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_EAE_SBOP; reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
if (!(smmu->options & ARM_SMMU_OPT_NO_M))
reg |= SCTLR_M;
if (stage1) if (stage1)
reg |= SCTLR_S1_ASIDPNE; reg |= SCTLR_S1_ASIDPNE;
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN