Merge "clk: msm: clock: Remove controlling some graphics clocks in Linux"
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commit
35021f91c8
3 changed files with 0 additions and 29 deletions
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@ -1707,17 +1707,6 @@ static struct branch_clk gcc_gpu_bimc_gfx_clk = {
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},
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};
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static struct branch_clk gcc_gpu_bimc_gfx_src_clk = {
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.cbcr_reg = GCC_GPU_BIMC_GFX_SRC_CBCR,
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.has_sibling = 1,
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.base = &virt_base,
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.c = {
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.dbg_name = "gcc_gpu_bimc_gfx_src_clk",
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.ops = &clk_ops_branch,
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CLK_INIT(gcc_gpu_bimc_gfx_src_clk.c),
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},
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};
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static struct branch_clk gcc_gpu_cfg_ahb_clk = {
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.cbcr_reg = GCC_GPU_CFG_AHB_CBCR,
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.has_sibling = 1,
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@ -1731,17 +1720,6 @@ static struct branch_clk gcc_gpu_cfg_ahb_clk = {
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},
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};
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static struct branch_clk gcc_gpu_snoc_dvm_gfx_clk = {
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.cbcr_reg = GCC_GPU_SNOC_DVM_GFX_CBCR,
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.has_sibling = 1,
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.base = &virt_base,
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.c = {
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.dbg_name = "gcc_gpu_snoc_dvm_gfx_clk",
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.ops = &clk_ops_branch,
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CLK_INIT(gcc_gpu_snoc_dvm_gfx_clk.c),
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},
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};
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static struct branch_clk gcc_gpu_iref_clk = {
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.cbcr_reg = GCC_GPU_IREF_EN,
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.has_sibling = 1,
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@ -2454,7 +2432,6 @@ static struct mux_clk gcc_debug_mux = {
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{ &gcc_mss_mnoc_bimc_axi_clk.c, 0x0120 },
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{ &gcc_mss_snoc_axi_clk.c, 0x0123 },
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{ &gcc_gpu_cfg_ahb_clk.c, 0x013b },
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{ &gcc_gpu_bimc_gfx_src_clk.c, 0x013e },
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{ &gcc_gpu_bimc_gfx_clk.c, 0x013f },
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{ &gcc_qspi_ahb_clk.c, 0x0156 },
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{ &gcc_qspi_ref_clk.c, 0x0157 },
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@ -2649,9 +2626,7 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = {
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CLK_LIST(gcc_gp2_clk),
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CLK_LIST(gcc_gp3_clk),
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CLK_LIST(gcc_gpu_bimc_gfx_clk),
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CLK_LIST(gcc_gpu_bimc_gfx_src_clk),
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CLK_LIST(gcc_gpu_cfg_ahb_clk),
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CLK_LIST(gcc_gpu_snoc_dvm_gfx_clk),
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CLK_LIST(gcc_gpu_iref_clk),
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CLK_LIST(gcc_hmss_ahb_clk),
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CLK_LIST(gcc_hmss_dvm_bus_clk),
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@ -198,9 +198,7 @@
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#define clk_gcc_gp1_clk 0x057f7b69
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#define clk_gcc_gp2_clk 0x9bf83ffd
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#define clk_gcc_gp3_clk 0xec6539ee
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#define clk_gcc_gpu_snoc_dvm_gfx_clk 0xc9147451
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#define clk_gcc_gpu_bimc_gfx_clk 0x3909459b
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#define clk_gcc_gpu_bimc_gfx_src_clk 0x377cb748
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#define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57
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#define clk_gcc_gpu_iref_clk 0xfd82abad
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#define clk_gcc_hmss_ahb_clk 0x62818713
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@ -167,9 +167,7 @@
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#define GCC_GP2_CBCR 0x65000
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#define GCC_GP3_CBCR 0x66000
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#define GCC_GPU_BIMC_GFX_CBCR 0x71010
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#define GCC_GPU_BIMC_GFX_SRC_CBCR 0x7100C
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#define GCC_GPU_CFG_AHB_CBCR 0x71004
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#define GCC_GPU_SNOC_DVM_GFX_CBCR 0x71018
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#define GCC_GPU_IREF_EN 0x88010
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#define GCC_HMSS_AHB_CBCR 0x48000
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#define GCC_HMSS_DVM_BUS_CBCR 0x4808C
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