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msm: mdss: Update PP cache to use different PA structure

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The PP cache currently stores the 'data' structure for PAv2. For newer
MDP targets, the PP res cache needs to store the PAv2 config data
structure, which has some PAv2 configuration info as well as the 'data'
structure nested inside. The configuration structure is needed in the
cache because it contains info for newer targets required when updating
the registers.

Change-Id: Idd1aa23687245ab7cc71c2c7a9cb74958c77dcec
Signed-off-by: Benet Clark <benetc@codeaurora.org>
This commit is contained in:
Benet Clark 2014-11-26 02:45:59 -08:00 • committed by David Keitel
parent 2caa0b46c7
commit 3524a114f2
2 changed files with 14 additions and 9 deletions
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21
drivers/video/fbdev/msm/mdss_mdp_pp.c
View file

@ -1645,6 +1645,7 @@ static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_mixer *mixer)
struct mdss_data_type *mdata;
struct mdss_ad_info *ad = NULL;
struct mdss_mdp_ad *ad_hw = NULL;
struct mdp_pa_v2_cfg_data *pa_v2_cfg_data = NULL;
struct mdss_mdp_ctl *ctl;
u32 mixer_cnt;
u32 mixer_id[MDSS_MDP_INTF_MAX_LAYERMIXER];
@ -1694,8 +1695,9 @@ static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_mixer *mixer)
pp_sts = &mdss_pp_res->pp_disp_sts[disp_num];
if (mdata->mdp_rev >= MDSS_MDP_HW_REV_103) {
pa_v2_cfg_data = &mdss_pp_res->pa_v2_disp_cfg[disp_num];
pp_pa_v2_config(flags, base + MDSS_MDP_REG_DSPP_PA_BASE, pp_sts,
&mdss_pp_res->pa_v2_disp_cfg[disp_num],
&pa_v2_cfg_data->pa_v2_data,
PP_DSPP);
} else
pp_pa_config(flags, base + MDSS_MDP_REG_DSPP_PA_BASE, pp_sts,
@ -1908,7 +1910,7 @@ int mdss_mdp_pp_setup_locked(struct mdss_mdp_ctl *ctl)
mutex_lock(&mdss_pp_mutex);
flags = mdss_pp_res->pp_disp_flags[disp_num];
pa_v2_flags = mdss_pp_res->pa_v2_disp_cfg[disp_num].flags;
pa_v2_flags = mdss_pp_res->pa_v2_disp_cfg[disp_num].pa_v2_data.flags;
/*
* If a LUT based PP feature needs to be reprogrammed during resume,
@ -1965,6 +1967,7 @@ int mdss_mdp_pp_resume(struct mdss_mdp_ctl *ctl, u32 dspp_num)
struct mdss_ad_info *ad;
struct mdss_data_type *mdata;
struct msm_fb_data_type *bl_mfd;
struct mdp_pa_v2_cfg_data *pa_v2_cache_cfg = NULL;
if (!ctl || !ctl->mdata || !ctl->mfd) {
pr_err("invalid input: ctl = 0x%p, mdata = 0x%p, mfd = 0x%p\n",
@ -1983,10 +1986,11 @@ int mdss_mdp_pp_resume(struct mdss_mdp_ctl *ctl, u32 dspp_num)
if (pp_sts.pa_sts & PP_STS_ENABLE) {
flags |= PP_FLAGS_DIRTY_PA;
pa_v2_cache_cfg = &mdss_pp_res->pa_v2_disp_cfg[disp_num];
if (mdata->mdp_rev >= MDSS_MDP_HW_REV_103) {
if (!(mdss_pp_res->pa_v2_disp_cfg[disp_num].flags
if (!(pa_v2_cache_cfg->pa_v2_data.flags
& MDP_PP_OPS_DISABLE))
mdss_pp_res->pa_v2_disp_cfg[disp_num].flags |=
pa_v2_cache_cfg->pa_v2_data.flags |=
MDP_PP_OPS_WRITE;
} else {
if (!(mdss_pp_res->pa_disp_cfg[disp_num].flags
@ -2456,6 +2460,7 @@ int mdss_mdp_pa_v2_config(struct mdp_pa_v2_cfg_data *config,
u32 disp_num, dspp_num = 0;
char __iomem *pa_addr;
struct mdss_data_type *mdata = mdss_mdp_get_mdata();
struct mdp_pa_v2_cfg_data *pa_v2_cache = NULL;
if (mdata->mdp_rev < MDSS_MDP_HW_REV_103)
return -EINVAL;
@ -2500,11 +2505,11 @@ int mdss_mdp_pa_v2_config(struct mdp_pa_v2_cfg_data *config,
if (ret)
goto pa_config_exit;
}
mdss_pp_res->pa_v2_disp_cfg[disp_num] =
config->pa_v2_data;
mdss_pp_res->pa_v2_disp_cfg[disp_num].six_zone_curve_p0 =
pa_v2_cache = &mdss_pp_res->pa_v2_disp_cfg[disp_num];
*pa_v2_cache = *config;
pa_v2_cache->pa_v2_data.six_zone_curve_p0 =
&mdss_pp_res->six_zone_lut_curve_p0[disp_num][0];
mdss_pp_res->pa_v2_disp_cfg[disp_num].six_zone_curve_p1 =
pa_v2_cache->pa_v2_data.six_zone_curve_p1 =
&mdss_pp_res->six_zone_lut_curve_p1[disp_num][0];
mdss_pp_res->pp_disp_flags[disp_num] |= PP_FLAGS_DIRTY_PA;
}

2
drivers/video/fbdev/msm/mdss_mdp_pp.h
View file

@ -125,7 +125,7 @@ struct mdss_pp_res_type {
gc_lut_b[MDSS_BLOCK_DISP_NUM][GC_LUT_SEGMENTS];
u32 enhist_lut[MDSS_BLOCK_DISP_NUM][ENHIST_LUT_ENTRIES];
struct mdp_pa_cfg pa_disp_cfg[MDSS_BLOCK_DISP_NUM];
struct mdp_pa_v2_data pa_v2_disp_cfg[MDSS_BLOCK_DISP_NUM];
struct mdp_pa_v2_cfg_data pa_v2_disp_cfg[MDSS_BLOCK_DISP_NUM];
u32 six_zone_lut_curve_p0[MDSS_BLOCK_DISP_NUM][MDP_SIX_ZONE_LUT_SIZE];
u32 six_zone_lut_curve_p1[MDSS_BLOCK_DISP_NUM][MDP_SIX_ZONE_LUT_SIZE];
struct mdp_pcc_cfg_data pcc_disp_cfg[MDSS_BLOCK_DISP_NUM];