ARM: kprobes: Migrate ARM data-processing (register) instructions to decoding tables
Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
This commit is contained in:
Jon Medhurst
Tixy
parent
9f596e5126
commit
3535a89ab2
1 changed files with 63 additions and 48 deletions
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@ -968,6 +968,68 @@ static const union decode_item arm_1111_table[] = {
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DECODE_END
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DECODE_END
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};
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};
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static const union decode_item arm_cccc_000x_table[] = {
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/* Data-processing (register) */
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/* <op>S PC, ... cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx */
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DECODE_REJECT (0x0e10f000, 0x0010f000),
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/* MOV IP, SP 1110 0001 1010 0000 1100 0000 0000 1101 */
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DECODE_SIMULATE (0xffffffff, 0xe1a0c00d, simulate_mov_ipsp),
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/* TST (register) cccc 0001 0001 xxxx xxxx xxxx xxx0 xxxx */
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/* TEQ (register) cccc 0001 0011 xxxx xxxx xxxx xxx0 xxxx */
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/* CMP (register) cccc 0001 0101 xxxx xxxx xxxx xxx0 xxxx */
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/* CMN (register) cccc 0001 0111 xxxx xxxx xxxx xxx0 xxxx */
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DECODE_EMULATEX (0x0f900010, 0x01100000, emulate_rd12rn16rm0rs8_rwflags,
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REGS(ANY, 0, 0, 0, ANY)),
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/* MOV (register) cccc 0001 101x xxxx xxxx xxxx xxx0 xxxx */
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/* MVN (register) cccc 0001 111x xxxx xxxx xxxx xxx0 xxxx */
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DECODE_EMULATEX (0x0fa00010, 0x01a00000, emulate_rd12rn16rm0rs8_rwflags,
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REGS(0, ANY, 0, 0, ANY)),
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/* AND (register) cccc 0000 000x xxxx xxxx xxxx xxx0 xxxx */
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/* EOR (register) cccc 0000 001x xxxx xxxx xxxx xxx0 xxxx */
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/* SUB (register) cccc 0000 010x xxxx xxxx xxxx xxx0 xxxx */
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/* RSB (register) cccc 0000 011x xxxx xxxx xxxx xxx0 xxxx */
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/* ADD (register) cccc 0000 100x xxxx xxxx xxxx xxx0 xxxx */
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/* ADC (register) cccc 0000 101x xxxx xxxx xxxx xxx0 xxxx */
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/* SBC (register) cccc 0000 110x xxxx xxxx xxxx xxx0 xxxx */
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/* RSC (register) cccc 0000 111x xxxx xxxx xxxx xxx0 xxxx */
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/* ORR (register) cccc 0001 100x xxxx xxxx xxxx xxx0 xxxx */
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/* BIC (register) cccc 0001 110x xxxx xxxx xxxx xxx0 xxxx */
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DECODE_EMULATEX (0x0e000010, 0x00000000, emulate_rd12rn16rm0rs8_rwflags,
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REGS(ANY, ANY, 0, 0, ANY)),
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/* TST (reg-shift reg) cccc 0001 0001 xxxx xxxx xxxx 0xx1 xxxx */
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/* TEQ (reg-shift reg) cccc 0001 0011 xxxx xxxx xxxx 0xx1 xxxx */
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/* CMP (reg-shift reg) cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */
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/* CMN (reg-shift reg) cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */
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DECODE_EMULATEX (0x0f900090, 0x01100010, emulate_rd12rn16rm0rs8_rwflags,
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REGS(ANY, 0, NOPC, 0, ANY)),
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/* MOV (reg-shift reg) cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */
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/* MVN (reg-shift reg) cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */
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DECODE_EMULATEX (0x0fa00090, 0x01a00010, emulate_rd12rn16rm0rs8_rwflags,
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REGS(0, ANY, NOPC, 0, ANY)),
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/* AND (reg-shift reg) cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */
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/* EOR (reg-shift reg) cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */
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/* SUB (reg-shift reg) cccc 0000 010x xxxx xxxx xxxx 0xx1 xxxx */
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/* RSB (reg-shift reg) cccc 0000 011x xxxx xxxx xxxx 0xx1 xxxx */
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/* ADD (reg-shift reg) cccc 0000 100x xxxx xxxx xxxx 0xx1 xxxx */
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/* ADC (reg-shift reg) cccc 0000 101x xxxx xxxx xxxx 0xx1 xxxx */
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/* SBC (reg-shift reg) cccc 0000 110x xxxx xxxx xxxx 0xx1 xxxx */
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/* RSC (reg-shift reg) cccc 0000 111x xxxx xxxx xxxx 0xx1 xxxx */
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/* ORR (reg-shift reg) cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */
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/* BIC (reg-shift reg) cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */
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DECODE_EMULATEX (0x0e000090, 0x00000010, emulate_rd12rn16rm0rs8_rwflags,
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REGS(ANY, ANY, NOPC, 0, ANY)),
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DECODE_END
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};
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static enum kprobe_insn __kprobes
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static enum kprobe_insn __kprobes
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space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
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space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
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{
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{
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@ -1126,54 +1188,7 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
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return prep_emulate_ldr_str(insn, asi);
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return prep_emulate_ldr_str(insn, asi);
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}
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}
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/* cccc 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx */
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return kprobe_decode_insn(insn, asi, arm_cccc_000x_table, false);
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/*
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* ALU op with S bit and Rd == 15 :
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* cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx
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*/
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if ((insn & 0x0e10f000) == 0x0010f000)
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return INSN_REJECTED;
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/*
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* "mov ip, sp" is the most common kprobe'd instruction by far.
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* Check and optimize for it explicitly.
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*/
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if (insn == 0xe1a0c00d) {
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asi->insn_handler = simulate_mov_ipsp;
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return INSN_GOOD_NO_SLOT;
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}
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/*
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* Data processing: Immediate-shift / Register-shift
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* ALU op : cccc 000x xxxx xxxx xxxx xxxx xxxx xxxx
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* CPY : cccc 0001 1010 xxxx xxxx 0000 0000 xxxx
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* MOV : cccc 0001 101x xxxx xxxx xxxx xxxx xxxx
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* *S (bit 20) updates condition codes
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* ADC/SBC/RSC reads the C flag
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*/
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insn &= 0xfff00ff0; /* Rn = r0, Rd = r0 */
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insn |= 0x00000001; /* Rm = r1 */
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if (insn & 0x010) {
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insn &= 0xfffff0ff; /* register shift */
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insn |= 0x00000200; /* Rs = r2 */
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}
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asi->insn[0] = insn;
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if ((insn & 0x0f900000) == 0x01100000) {
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/*
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* TST : cccc 0001 0001 xxxx xxxx xxxx xxxx xxxx
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* TEQ : cccc 0001 0011 xxxx xxxx xxxx xxxx xxxx
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* CMP : cccc 0001 0101 xxxx xxxx xxxx xxxx xxxx
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* CMN : cccc 0001 0111 xxxx xxxx xxxx xxxx xxxx
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*/
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asi->insn_handler = emulate_alu_tests;
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} else {
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/* ALU ops which write to Rd */
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asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
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emulate_alu_rwflags : emulate_alu_rflags;
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}
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return INSN_GOOD;
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}
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}
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static enum kprobe_insn __kprobes
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static enum kprobe_insn __kprobes
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