drm/i915: Use atomic state for calculating DVO_2X_MODE on i830.
This is a small behavioral change because it leaves DVO_2X_MODE set between crtc_disable and crtc_enable. This is probably harmless though and if not should be fixed by calculating 2x mode before enable/disable pll. This is needed because intel_crtc->active will be removed eventually. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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1 changed files with 2 additions and 2 deletions
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@ -1698,7 +1698,7 @@ static int intel_num_dvo_pipes(struct drm_device *dev)
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int count = 0;
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int count = 0;
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for_each_intel_crtc(dev, crtc)
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for_each_intel_crtc(dev, crtc)
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count += crtc->active &&
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count += crtc->base.state->active &&
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intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
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intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
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return count;
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return count;
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@ -1779,7 +1779,7 @@ static void i9xx_disable_pll(struct intel_crtc *crtc)
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/* Disable DVO 2x clock on both PLLs if necessary */
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/* Disable DVO 2x clock on both PLLs if necessary */
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if (IS_I830(dev) &&
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if (IS_I830(dev) &&
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intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
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intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
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intel_num_dvo_pipes(dev) == 1) {
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!intel_num_dvo_pipes(dev)) {
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I915_WRITE(DPLL(PIPE_B),
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I915_WRITE(DPLL(PIPE_B),
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I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
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I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
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I915_WRITE(DPLL(PIPE_A),
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I915_WRITE(DPLL(PIPE_A),
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