staging: brcm80211: removed more unused dma32 code
Since two preprocessor defines are always '1', could remove code that was never compiled in and removed references to these preprocessor defines (DMA64_ENAB and DMA64_MODE). Signed-off-by: Roland Vossen <rvossen@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Roland Vossen
Greg Kroah-Hartman
parent
2fd31011ac
commit
36e319bd39
1 changed files with 162 additions and 232 deletions
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@ -151,9 +151,6 @@ typedef struct dma_info {
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bool aligndesc_4k; /* descriptor base need to be aligned or not */
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} dma_info_t;
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#define DMA64_ENAB(di) 1
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#define DMA64_MODE(di) 1
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/* DMA Scatter-gather list is supported. Note this is limited to TX direction only */
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#ifdef BCMDMASGLISTOSL
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#define DMASGLIST_ENAB true
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@ -380,11 +377,7 @@ struct hnddma_pub *dma_attach(struct osl_info *osh, char *name, si_t *sih,
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/* old chips w/o sb is no longer supported */
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ASSERT(sih != NULL);
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if (DMA64_ENAB(di))
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di->dma64 =
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((si_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);
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else
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di->dma64 = 0;
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di->dma64 = ((si_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);
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/* check arguments */
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ASSERT(ISPOWEROF2(ntxd));
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@ -396,17 +389,11 @@ struct hnddma_pub *dma_attach(struct osl_info *osh, char *name, si_t *sih,
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ASSERT(dmaregstx == NULL);
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/* init dma reg pointer */
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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ASSERT(ntxd <= D64MAXDD);
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ASSERT(nrxd <= D64MAXDD);
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di->d64txregs = (dma64regs_t *) dmaregstx;
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di->d64rxregs = (dma64regs_t *) dmaregsrx;
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di->hnddma.di_fn = (const di_fcn_t *)&dma64proc;
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} else {
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DMA_ERROR(("dma_attach: driver doesn't support 32-bit DMA\n"));
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ASSERT(0);
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goto fail;
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}
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/* Default flags (which can be changed by the driver calling dma_ctrlflags
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* before enable): For backwards compatibility both Rx Overflow Continue
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@ -416,7 +403,11 @@ struct hnddma_pub *dma_attach(struct osl_info *osh, char *name, si_t *sih,
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di->hnddma.di_fn->ctrlflags(&di->hnddma, DMA_CTRL_ROC | DMA_CTRL_PEN,
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0);
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DMA_TRACE(("%s: dma_attach: %s osh %p flags 0x%x ntxd %d nrxd %d rxbufsize %d " "rxextheadroom %d nrxpost %d rxoffset %d dmaregstx %p dmaregsrx %p\n", name, (DMA64_MODE(di) ? "DMA64" : "DMA32"), osh, di->hnddma.dmactrlflags, ntxd, nrxd, rxbufsize, rxextheadroom, nrxpost, rxoffset, dmaregstx, dmaregsrx));
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DMA_TRACE(("%s: dma_attach: %s osh %p flags 0x%x ntxd %d nrxd %d "
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"rxbufsize %d rxextheadroom %d nrxpost %d rxoffset %d "
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"dmaregstx %p dmaregsrx %p\n", name, "DMA64", osh,
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di->hnddma.dmactrlflags, ntxd, nrxd, rxbufsize,
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rxextheadroom, nrxpost, rxoffset, dmaregstx, dmaregsrx));
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/* make a private copy of our callers name */
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strncpy(di->name, name, MAXNAMEL);
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@ -450,15 +441,9 @@ struct hnddma_pub *dma_attach(struct osl_info *osh, char *name, si_t *sih,
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di->dataoffsetlow = 0;
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/* for pci bus, add offset */
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if (sih->bustype == PCI_BUS) {
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if ((sih->buscoretype == PCIE_CORE_ID) && DMA64_MODE(di)) {
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/* pcie with DMA64 */
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di->ddoffsetlow = 0;
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di->ddoffsethigh = SI_PCIE_DMA_H32;
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} else {
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/* pci(DMA32/DMA64) or pcie with DMA32 */
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di->ddoffsetlow = SI_PCI_DMA;
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di->ddoffsethigh = 0;
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}
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di->dataoffsetlow = di->ddoffsetlow;
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di->dataoffsethigh = di->ddoffsethigh;
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}
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@ -478,14 +463,11 @@ struct hnddma_pub *dma_attach(struct osl_info *osh, char *name, si_t *sih,
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/* does the descriptors need to be aligned and if yes, on 4K/8K or not */
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di->aligndesc_4k = _dma_descriptor_align(di);
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if (di->aligndesc_4k) {
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if (DMA64_MODE(di)) {
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di->dmadesc_align = D64RINGALIGN_BITS;
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if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2)) {
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/* for smaller dd table, HW relax the alignment requirement */
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/* for smaller dd table, HW relax alignment reqmnt */
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di->dmadesc_align = D64RINGALIGN_BITS - 1;
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}
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} else
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di->dmadesc_align = D32RINGALIGN_BITS;
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} else
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di->dmadesc_align = 4; /* 16 byte alignment */
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@ -659,10 +641,7 @@ static bool _dma32_addrext(struct osl_info *osh, dma32regs_t *dma32regs)
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static bool _dma_alloc(dma_info_t *di, uint direction)
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{
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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return dma64_alloc(di, direction);
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} else
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ASSERT(0);
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}
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/* !! may be called with core in reset */
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@ -676,7 +655,6 @@ static void _dma_detach(dma_info_t *di)
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ASSERT(di->rxin == di->rxout);
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/* free dma descriptor rings */
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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if (di->txd64)
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DMA_FREE_CONSISTENT(di->osh,
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((s8 *)di->txd64 -
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@ -687,8 +665,6 @@ static void _dma_detach(dma_info_t *di)
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((s8 *)di->rxd64 -
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di->rxdalign), di->rxdalloc,
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(di->rxdpaorig), &di->rx_dmah);
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} else
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ASSERT(0);
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/* free packet pointer vectors */
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if (di->txp)
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@ -711,7 +687,6 @@ static void _dma_detach(dma_info_t *di)
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static bool _dma_descriptor_align(dma_info_t *di)
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{
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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u32 addrl;
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/* Check to see if the descriptors need to be aligned on 4K/8K or not */
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@ -726,41 +701,36 @@ static bool _dma_descriptor_align(dma_info_t *di)
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if (addrl != 0)
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return false;
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}
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}
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return true;
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}
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/* return true if this dma engine supports DmaExtendedAddrChanges, otherwise false */
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static bool _dma_isaddrext(dma_info_t *di)
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{
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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/* DMA64 supports full 32- or 64-bit operation. AE is always valid */
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/* not all tx or rx channel are available */
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if (di->d64txregs != NULL) {
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if (!_dma64_addrext(di->osh, di->d64txregs)) {
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DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have AE set\n", di->name));
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DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have "
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"AE set\n", di->name));
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ASSERT(0);
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}
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return true;
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} else if (di->d64rxregs != NULL) {
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if (!_dma64_addrext(di->osh, di->d64rxregs)) {
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DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have AE set\n", di->name));
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DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have "
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"AE set\n", di->name));
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ASSERT(0);
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}
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return true;
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}
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return false;
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} else
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ASSERT(0);
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return false;
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}
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/* initialize descriptor table base address */
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static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa)
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{
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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if (!di->aligndesc_4k) {
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if (direction == DMA_TX)
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di->xmtptrbase = PHYSADDRLO(pa);
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@ -808,18 +778,13 @@ static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa)
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D64_RC_AE, (ae << D64_RC_AE_SHIFT));
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}
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}
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} else
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ASSERT(0);
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}
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static void _dma_fifoloopbackenable(dma_info_t *di)
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{
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DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
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if (DMA64_ENAB(di) && DMA64_MODE(di))
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OR_REG(di->osh, &di->d64txregs->control, D64_XC_LE);
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else
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ASSERT(0);
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}
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static void _dma_rxinit(dma_info_t *di)
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@ -832,7 +797,6 @@ static void _dma_rxinit(dma_info_t *di)
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di->rxin = di->rxout = 0;
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/* clear rx descriptor ring */
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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memset((void *)di->rxd64, '\0',
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(di->nrxd * sizeof(dma64dd_t)));
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@ -846,18 +810,16 @@ static void _dma_rxinit(dma_info_t *di)
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if (di->aligndesc_4k)
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_dma_ddtable_init(di, DMA_RX, di->rxdpa);
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} else
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ASSERT(0);
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}
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static void _dma_rxenable(dma_info_t *di)
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{
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uint dmactrlflags = di->hnddma.dmactrlflags;
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u32 control;
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DMA_TRACE(("%s: dma_rxenable\n", di->name));
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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u32 control =
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control =
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(R_REG(di->osh, &di->d64rxregs->control) & D64_RC_AE) |
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D64_RC_RE;
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@ -869,8 +831,6 @@ static void _dma_rxenable(dma_info_t *di)
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W_REG(di->osh, &di->d64rxregs->control,
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((di->rxoffset << D64_RC_RO_SHIFT) | control));
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} else
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ASSERT(0);
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}
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static void
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@ -936,14 +896,11 @@ static void *BCMFASTPATH _dma_rx(dma_info_t *di)
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if (resid > 0) {
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uint cur;
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ASSERT(p == NULL);
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cur = (DMA64_ENAB(di) && DMA64_MODE(di)) ?
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cur =
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B2I(((R_REG(di->osh, &di->d64rxregs->status0) &
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D64_RS0_CD_MASK) -
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di->rcvptrbase) & D64_RS0_CD_MASK,
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dma64dd_t) : B2I(R_REG(di->osh,
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&di->d32rxregs->
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status) & RS_CD_MASK,
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dma32dd_t);
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dma64dd_t);
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DMA_ERROR(("_dma_rx, rxin %d rxout %d, hw_curr %d\n",
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di->rxin, di->rxout, cur));
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}
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@ -1005,15 +962,11 @@ static bool BCMFASTPATH _dma_rxfill(dma_info_t *di)
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if (p == NULL) {
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DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n",
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di->name));
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if (i == 0) {
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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if (dma64_rxidle(di)) {
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DMA_ERROR(("%s: rxfill64: ring is empty !\n", di->name));
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if (i == 0 && dma64_rxidle(di)) {
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DMA_ERROR(("%s: rxfill64: ring is empty !\n",
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di->name));
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ring_empty = true;
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}
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} else
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ASSERT(0);
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}
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di->hnddma.rxnobuf++;
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break;
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}
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@ -1041,25 +994,19 @@ static bool BCMFASTPATH _dma_rxfill(dma_info_t *di)
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/* reset flags for each descriptor */
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flags = 0;
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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if (rxout == (di->nrxd - 1))
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flags = D64_CTRL1_EOT;
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dma64_dd_upd(di, di->rxd64, pa, rxout, &flags,
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di->rxbufsize);
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} else
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ASSERT(0);
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rxout = NEXTRXD(rxout);
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}
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di->rxout = rxout;
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/* update the chip lastdscr pointer */
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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W_REG(di->osh, &di->d64rxregs->ptr,
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di->rcvptrbase + I2B(rxout, dma64dd_t));
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} else
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ASSERT(0);
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return ring_empty;
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}
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@ -1072,13 +1019,10 @@ static void *_dma_peeknexttxp(dma_info_t *di)
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if (di->ntxd == 0)
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return NULL;
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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end =
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B2I(((R_REG(di->osh, &di->d64txregs->status0) &
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D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
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dma64dd_t);
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} else
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ASSERT(0);
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for (i = di->txin; i != end; i = NEXTTXD(i))
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if (di->txp[i])
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@ -1095,13 +1039,10 @@ static void *_dma_peeknextrxp(dma_info_t *di)
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if (di->nrxd == 0)
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return NULL;
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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end =
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B2I(((R_REG(di->osh, &di->d64rxregs->status0) &
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D64_RS0_CD_MASK) - di->rcvptrbase) & D64_RS0_CD_MASK,
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dma64dd_t);
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} else
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ASSERT(0);
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for (i = di->rxin; i != end; i = NEXTRXD(i))
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if (di->rxp[i])
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@ -1125,10 +1066,7 @@ static void *BCMFASTPATH _dma_getnextrxp(dma_info_t *di, bool forceall)
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if (di->nrxd == 0)
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return NULL;
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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return dma64_getnextrxp(di, forceall);
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} else
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ASSERT(0);
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}
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static void _dma_txblock(dma_info_t *di)
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@ -1150,13 +1088,10 @@ static uint _dma_txpending(dma_info_t *di)
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{
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uint curr;
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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curr =
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B2I(((R_REG(di->osh, &di->d64txregs->status0) &
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D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
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dma64dd_t);
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} else
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ASSERT(0);
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return NTXDACTIVE(curr, di->txout);
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}
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@ -1169,10 +1104,7 @@ static uint _dma_txcommitted(dma_info_t *di)
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if (txin == di->txout)
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return 0;
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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ptr = B2I(R_REG(di->osh, &di->d64txregs->ptr), dma64dd_t);
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} else
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ASSERT(0);
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return NTXDACTIVE(di->txin, ptr);
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}
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@ -1208,7 +1140,6 @@ static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags)
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if (dmactrlflags & DMA_CTRL_PEN) {
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u32 control;
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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control = R_REG(di->osh, &di->d64txregs->control);
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W_REG(di->osh, &di->d64txregs->control,
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control | D64_XC_PD);
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@ -1222,8 +1153,6 @@ static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags)
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/* Not supported, don't allow it to be enabled */
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dmactrlflags &= ~DMA_CTRL_PEN;
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}
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} else
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ASSERT(0);
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}
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di->hnddma.dmactrlflags = dmactrlflags;
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@ -2561,3 +2490,4 @@ uint dma_addrwidth(si_t *sih, void *dmaregs)
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/* Fallthru */
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return DMADDRWIDTH_30;
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}
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