evie/android_kernel_oneplus_msm8998
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ARM: dts: msm: update the smmu device node configuration for msmfalcon

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Update the SMMU device node configuration for correct operation of SMMU
on msmfalcon.

Change-Id: I29fa8f488df800d38f6403646e58a19e555ba1cd
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
This commit is contained in:
Charan Teja Reddy 2016-12-01 15:52:12 +05:30
parent 69352ff8b4
commit 37e0cf7dc9
1 changed files with 2 additions and 7 deletions
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9
arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi
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@ -13,7 +13,6 @@
#include <dt-bindings/clock/qcom,gcc-msmfalcon.h>
#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/msm/msm-bus-ids.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
@ -61,7 +60,6 @@
};
lpass_q6_smmu: arm,smmu-lpass_q6@5100000 {
status = "disabled";
compatible = "qcom,smmu-v2";
reg = <0x5100000 0x40000>;
#iommu-cells = <1>;
@ -94,11 +92,11 @@
};
mmss_bimc_smmu: arm,smmu-mmss@cd00000 {
status = "disabled";
compatible = "qcom,smmu-v2";
reg = <0xcd00000 0x40000>;
#iommu-cells = <1>;
qcom,register-save;
qcom,no-smr-check;
qcom,skip-init;
#global-interrupts = <2>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
@ -129,7 +127,7 @@
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
vdd-supply = <&gdsc_bimc_smmu>;
clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>,
<&clock_gcc MMSSNOC_AXI_CLK>,
<&clock_rpmcc MMSSNOC_AXI_CLK>,
<&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
clock-names = "mmss_mnoc_ahb_clk",
@ -137,11 +135,9 @@
"mmss_bimc_smmu_ahb_clk",
"mmss_bimc_smmu_axi_clk";
#clock-cells = <1>;
qcom,bus-master-id = <MSM_BUS_MNOC_BIMC_MAS>;
};
kgsl_smmu: arm,smmu-kgsl@5040000 {
status = "disabled";
compatible = "qcom,smmu-v2";
reg = <0x5040000 0x10000>;
#iommu-cells = <1>;
@ -170,7 +166,6 @@
};
turing_q6_smmu: arm,smmu-turing_q6@5180000 {
status = "disabled";
compatible = "qcom,smmu-v2";
reg = <0x5180000 0x40000>;
#iommu-cells = <1>;