diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
index 33e8c9c4993d..c43a52ba6b3a 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
@@ -736,7 +736,7 @@
 				"dp_link_src", "dp_vco_div",
 				"extpclk_src";
 		clocks = <&clock_gcc clk_cxo_clk_src>,
-			 <&clock_gcc clk_gpll0_out_main>,
+			 <&clock_gcc clk_gcc_mmss_gpll0_clk>,
 			 <&clock_gcc clk_gcc_mmss_gpll0_div_clk>,
 			 <&mdss_dsi0_pll clk_dsi0pll_pclk_mux>,
 			 <&mdss_dsi1_pll clk_dsi1pll_pclk_mux>,
@@ -755,7 +755,7 @@
 		vdd_dig-supply = <&pmcobalt_s1_level>;
 		clock-names = "xo_ao", "gpll0";
 		clocks = <&clock_gcc clk_cxo_clk_src_ao>,
-			<&clock_gcc clk_gpll0_out_main>;
+			<&clock_gcc clk_gcc_gpu_gpll0_clk>;
 		#clock-cells = <1>;
 	};
 
diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c
index 7299863ff42b..c539d57c0d0d 100644
--- a/drivers/clk/msm/clock-gcc-cobalt.c
+++ b/drivers/clk/msm/clock-gcc-cobalt.c
@@ -164,6 +164,20 @@ static struct pll_vote_clk gpll0_ao = {
 
 DEFINE_EXT_CLK(gpll0_out_main, &gpll0.c);
 
+static struct local_vote_clk gcc_mmss_gpll0_clk = {
+	.cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
+	.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
+	.en_mask = BIT(1),
+	.base = &virt_base,
+	.halt_check = DELAY,
+	.c = {
+		.dbg_name = "gcc_mmss_gpll0_clk",
+		.parent = &gpll0.c,
+		.ops = &clk_ops_vote,
+		CLK_INIT(gcc_mmss_gpll0_clk.c),
+	},
+};
+
 static struct local_vote_clk gcc_mmss_gpll0_div_clk = {
 	.cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
 	.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
@@ -178,6 +192,34 @@ static struct local_vote_clk gcc_mmss_gpll0_div_clk = {
 	},
 };
 
+static struct local_vote_clk gcc_gpu_gpll0_clk = {
+	.cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
+	.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
+	.en_mask = BIT(4),
+	.base = &virt_base,
+	.halt_check = DELAY,
+	.c = {
+		.dbg_name = "gcc_gpu_gpll0_clk",
+		.parent = &gpll0.c,
+		.ops = &clk_ops_vote,
+		CLK_INIT(gcc_gpu_gpll0_clk.c),
+	},
+};
+
+static struct local_vote_clk gcc_gpu_gpll0_div_clk = {
+	.cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
+	.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
+	.en_mask = BIT(3),
+	.base = &virt_base,
+	.halt_check = DELAY,
+	.c = {
+		.dbg_name = "gcc_gpu_gpll0_div_clk",
+		.parent = &gpll0.c,
+		.ops = &clk_ops_vote,
+		CLK_INIT(gcc_gpu_gpll0_div_clk.c),
+	},
+};
+
 static struct pll_vote_clk gpll4 = {
 	.en_reg = (void __iomem *)GCC_APCS_GPLL_ENA_VOTE,
 	.en_mask = BIT(4),
@@ -2535,7 +2577,10 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = {
 	CLK_LIST(gpll0),
 	CLK_LIST(gpll0_ao),
 	CLK_LIST(gpll0_out_main),
+	CLK_LIST(gcc_mmss_gpll0_clk),
 	CLK_LIST(gcc_mmss_gpll0_div_clk),
+	CLK_LIST(gcc_gpu_gpll0_clk),
+	CLK_LIST(gcc_gpu_gpll0_div_clk),
 	CLK_LIST(gpll4),
 	CLK_LIST(gpll4_out_main),
 	CLK_LIST(hmss_ahb_clk_src),
@@ -2784,6 +2829,10 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
+	/* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
+	writel_relaxed(0x10003, virt_base + GCC_MMSS_MISC);
+	writel_relaxed(0x10003, virt_base + GCC_GPU_MISC);
+
 	/* Hold an active set vote for the cnoc_periph resource */
 	clk_set_rate(&cnoc_periph_keepalive_a_clk.c, 19200000);
 	clk_prepare_enable(&cnoc_periph_keepalive_a_clk.c);
diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h
index 28efd55ea8f6..8b8b3d4d561c 100644
--- a/include/dt-bindings/clock/msm-clocks-cobalt.h
+++ b/include/dt-bindings/clock/msm-clocks-cobalt.h
@@ -99,7 +99,10 @@
 #define clk_gpll0				0x1ebe3bc4
 #define clk_gpll0_out_main			0xe9374de7
 #define clk_gpll0_ao				0xa1368304
+#define clk_gcc_mmss_gpll0_clk			0x8050f008
 #define clk_gcc_mmss_gpll0_div_clk		0xdd06848d
+#define clk_gcc_gpu_gpll0_clk			0xdad7a7a4
+#define clk_gcc_gpu_gpll0_div_clk		0x07d16c6a
 #define clk_gpll4				0xb3b5d85b
 #define clk_gpll4_out_main			0xa9a0ab9d
 #define clk_hmss_ahb_clk_src			0xaec8450f
diff --git a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
index 7ef57256d8f0..16af7a1138cb 100644
--- a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
+++ b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
@@ -232,6 +232,8 @@
 #define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR			0x7D014
 #define GCC_QSPI_AHB_CBCR					0x90004
 #define GCC_QSPI_REF_CBCR					0x90008
+#define GCC_MMSS_MISC						0x0902C
+#define GCC_GPU_MISC						0x71028
 
 #define GPUCC_GPU_PLL0_PLL_MODE					0x00000
 #define GPUCC_GPU_PLL0_USER_CTL_MODE				0x0000C