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ARM: dts: msm: Change pinctrl settings for BLSP1 UART3 for msmcobalt

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Modify the sleep state settings for BLSP1 UART3 pins to optimize power
when the usecase isn't in play.

Change-Id: I1405a8561b1ecb2e3da87ed8b26fb087433a1c11
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
This commit is contained in:
Girish Mahadevan 2016-10-07 12:28:23 -06:00
parent 2ea1cecd04
commit 38c509c566
2 changed files with 76 additions and 20 deletions
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6
arch/arm/boot/dts/qcom/msmcobalt-blsp.dtsi
View file

@ -736,8 +736,10 @@
clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>,
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp1_uart3_sleep>;
pinctrl-1 = <&blsp1_uart3_active>;
pinctrl-0 = <&blsp1_uart3_tx_sleep>, <&blsp1_uart3_rxcts_sleep>,
<&blsp1_uart3_rfr_sleep>;
pinctrl-1 = <&blsp1_uart3_tx_active>,
<&blsp1_uart3_rxcts_active>, <&blsp1_uart3_rfr_active>;
qcom,msm-bus,name = "buart3";
qcom,msm-bus,num-cases = <2>;

90
arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi
View file

@ -1223,29 +1223,83 @@
};
};
blsp1_uart3_active: blsp1_uart3_active {
mux {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "blsp_uart3_a";
blsp1_uart3: blsp1_uart3 {
blsp1_uart3_tx_active: blsp1_uart3_tx_active {
mux {
pins = "gpio45";
function = "blsp_uart3_a";
};
config {
pins = "gpio45";
drive-strength = <2>;
bias-disable;
};
};
config {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
drive-strength = <2>;
bias-disable;
};
};
blsp1_uart3_tx_sleep: blsp1_uart3_tx_sleep {
mux {
pins = "gpio45";
function = "gpio";
};
blsp1_uart3_sleep: blsp1_uart3_sleep {
mux {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "gpio";
config {
pins = "gpio45";
drive-strength = <2>;
bias-pull-up;
};
};
config {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
drive-strength = <2>;
bias-pull-up;
blsp1_uart3_rxcts_active: blsp1_uart3_rxcts_active {
mux {
pins = "gpio46", "gpio47";
function = "blsp_uart3_a";
};
config {
pins = "gpio46", "gpio47";
drive-strength = <2>;
bias-disable;
};
};
blsp1_uart3_rxcts_sleep: blsp1_uart3_rxcts_sleep {
mux {
pins = "gpio46", "gpio47";
function = "gpio";
};
config {
pins = "gpio46", "gpio47";
drive-strength = <2>;
bias-no-pull;
};
};
blsp1_uart3_rfr_active: blsp1_uart3_rfr_active {
mux {
pins = "gpio48";
function = "blsp_uart3_a";
};
config {
pins = "gpio48";
drive-strength = <2>;
bias-disable;
};
};
blsp1_uart3_rfr_sleep: blsp1_uart3_rfr_sleep {
mux {
pins = "gpio48";
function = "gpio";
};
config {
pins = "gpio48";
drive-strength = <2>;
bias-no-pull;
};
};
};