USB: PHY: Remove TCSR register based clk_scheme usage

On newer platform TCSR register based clk_scheme usage is not
available. Hence remove its usage from QUSB and QMP PHY drivers.

Signed-off-by: Mayank Rana <mrana@codeaurora.org>

Documentation/devicetree/bindings/usb/msm-phy.txt

@@ -111,8 +111,6 @@ Required properties:
 
 Optional properties:
  - reg: Additional register set of address and length to control QMP PHY
-   "tcsr_phy_clk_scheme_sel": Read phy clk scheme single ended vs
-   differential to determine the value to write to QSERDES_COM_SYSCLK_EN_SEL.
  - qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
    the USB PHY and the controller must rely on external VBUS notification in
    order to manually relay the notification to the SSPHY.
@@ -162,7 +160,6 @@ Optional properties:
    via the QSCRATCH interface.
    "emu_phy_base" : phy base address used for programming emulation target phy.
    "ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset.
-   "tcsr_phy_clk_scheme_sel": address used to determine QUSB PHY clk source.
  - reg-names: Should be "qscratch_base". The qscratch register bank
    allows us to manipulate QUSB PHY bits eg. to enable D+ pull-up using s/w
    control in device mode. The reg-names property is required if the

drivers/usb/phy/phy-msm-qusb.c

@@ -28,9 +28,6 @@
 #include <linux/usb/phy.h>
 #include <linux/usb/msm_hsusb.h>
 
-/* TCSR_PHY_CLK_SCHEME_SEL bit mask */
-#define PHY_CLK_SCHEME_SEL BIT(0)
-
 #define QUSB2PHY_PLL_STATUS	0x38
 #define QUSB2PHY_PLL_LOCK	BIT(5)
 
@@ -108,7 +105,6 @@ struct qusb_phy {
 	void __iomem		*qscratch_base;
 	void __iomem		*tune2_efuse_reg;
 	void __iomem		*ref_clk_base;
-	void __iomem		*tcsr_phy_clk_scheme_sel;
 
 	struct clk		*ref_clk_src;
 	struct clk		*ref_clk;
@@ -520,19 +516,6 @@ static int qusb_phy_init(struct usb_phy *phy)
 	/* Require to get phy pll lock successfully */
 	usleep_range(150, 160);
 
-	if (qphy->tcsr_phy_clk_scheme_sel) {
-		ret = readl_relaxed(qphy->tcsr_phy_clk_scheme_sel);
-		if (ret & PHY_CLK_SCHEME_SEL) {
-			pr_debug("%s:select single-ended clk src\n",
-				__func__);
-			is_se_clk = true;
-		} else {
-			pr_debug("%s:select differential clk src\n",
-				__func__);
-			is_se_clk = false;
-		}
-	}
-
 	if (!is_se_clk)
 		reset_val &= ~CLK_REF_SEL;
 	else
@@ -856,15 +839,6 @@ static int qusb_phy_probe(struct platform_device *pdev)
 			dev_dbg(dev, "ref_clk_address is not available.\n");
 	}
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-			"tcsr_phy_clk_scheme_sel");
-	if (res) {
-		qphy->tcsr_phy_clk_scheme_sel = devm_ioremap_nocache(dev,
-				res->start, resource_size(res));
-		if (IS_ERR(qphy->tcsr_phy_clk_scheme_sel))
-			dev_dbg(dev, "err reading tcsr_phy_clk_scheme_sel\n");
-	}
-
 	qphy->ref_clk_src = devm_clk_get(dev, "ref_clk_src");
 	if (IS_ERR(qphy->ref_clk_src))
 		dev_dbg(dev, "clk get failed for ref_clk_src\n");

drivers/usb/phy/phy-msm-ssusb-qmp.c

@@ -36,9 +36,6 @@
 /* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */
 #define PHYSTATUS				BIT(6)
 
-/* TCSR_PHY_CLK_SCHEME_SEL bit mask */
-#define PHY_CLK_SCHEME_SEL BIT(0)
-
 /* PCIE_USB3_PHY_AUTONOMOUS_MODE_CTRL bits */
 #define ARCVR_DTCT_EN		BIT(0)
 #define ALFPS_DTCT_EN		BIT(1)
@@ -333,7 +330,6 @@ struct msm_ssphy_qmp {
 	struct usb_phy		phy;
 	void __iomem		*base;
 	void __iomem		*vls_clamp_reg;
-	void __iomem		*tcsr_phy_clk_scheme_sel;
 
 	struct regulator	*vdd;
 	struct regulator	*vdda18;
@@ -491,7 +487,6 @@ static int configure_phy_regs(struct usb_phy *uphy,
 {
 	struct msm_ssphy_qmp *phy = container_of(uphy, struct msm_ssphy_qmp,
 					phy);
-	u32 val;
 	bool diff_clk_sel = true;
 
 	if (!reg) {
@@ -499,15 +494,6 @@ static int configure_phy_regs(struct usb_phy *uphy,
 		return -EINVAL;
 	}
 
-	if (phy->tcsr_phy_clk_scheme_sel) {
-		val = readl_relaxed(phy->tcsr_phy_clk_scheme_sel);
-		if (val & PHY_CLK_SCHEME_SEL) {
-			pr_debug("%s:Single Ended clk scheme is selected\n",
-				__func__);
-			diff_clk_sel = false;
-		}
-	}
-
 	while (reg->offset != -1) {
 		writel_relaxed(diff_clk_sel ?
 				reg->diff_clk_sel_val : reg->se_clk_sel_val,
@@ -957,15 +943,6 @@ static int msm_ssphy_qmp_probe(struct platform_device *pdev)
 		return PTR_ERR(phy->vls_clamp_reg);
 	}
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-			"tcsr_phy_clk_scheme_sel");
-	if (res) {
-		phy->tcsr_phy_clk_scheme_sel = devm_ioremap_nocache(dev,
-				res->start, resource_size(res));
-		if (IS_ERR(phy->tcsr_phy_clk_scheme_sel))
-			dev_dbg(dev, "err reading tcsr_phy_clk_scheme_sel\n");
-	}
-
 	of_get_property(dev->of_node, "qcom,qmp-phy-init-seq", &size);
 	if (size) {
 		if (size % sizeof(*phy->qmp_phy_init_seq)) {