From 399804a90edfd86ac2da1d04a5f7d6045cc61f9c Mon Sep 17 00:00:00 2001 From: Padmanabhan Komanduru Date: Thu, 9 Feb 2017 17:12:33 +0530 Subject: [PATCH] ARM: dts: msm: limit the maximum PCLK supported for DP on SDM660 Update the dtsi property to limit the maximum pixel clock frequency supported on Display Port for SDM660 to 300 MHz. Change-Id: Iaacb08a310debd0d470d2f16c794fe70b09af2f5 Signed-off-by: Padmanabhan Komanduru --- arch/arm/boot/dts/qcom/sdm660-mdss.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi b/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi index b7329121ca49..c5f37acbbb22 100644 --- a/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi @@ -494,7 +494,7 @@ qcom,aux-cfg-settings = [00 13 00 00 0a 28 0a 03 b7 03]; qcom,logical2physical-lane-map = [00 01 02 03]; qcom,phy-register-offset = <0x4>; - qcom,max-pclk-frequency-khz = <593470>; + qcom,max-pclk-frequency-khz = <300000>; qcom,core-supply-entries { #address-cells = <1>;