scsi/phy: Remove orphaned files after renaming
Delete renamed orphan files after rebasing 3.18 ufs driver changes onto 4.4 ufs driver. Change-Id: Id241ad01bbb0fa74e209c66f8a2d97c05088e33b Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This commit is contained in:
Venkat Gopalakrishnan
David Keitel
parent
885a77f0e8
commit
3abbdb57e3
7 changed files with 0 additions and 3174 deletions
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@ -1,41 +0,0 @@
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* MSM Universal Flash Storage (UFS) PHY
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UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
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Each UFS PHY node should have its own node.
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To bind UFS PHY with UFS host controller, the controller node should
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contain a phandle reference to UFS PHY node.
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Required properties:
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- compatible : compatible list, contains "qcom,ufs-phy-qmp-28nm"
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or "qcom,ufs-phy-qmp-20nm" according to the relevant
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phy in use
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- reg : should contain PHY register address space (mandatory),
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device PHY control register map (optional).
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- reg-names : indicates various resources passed to driver (via reg proptery) by name.
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Required "reg-names" is "phy_mem" and "dev_ref_clk_ctrl_mem" is optional.
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- #phy-cells : This property shall be set to 0
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- vdda-phy-supply : phandle to main PHY supply for analog domain
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- vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply
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Optional properties:
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- vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply
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- vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
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Example:
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ufsphy1: ufsphy@0xfc597000 {
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compatible = "qcom,ufs-phy-qmp-28nm";
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reg = <0xfc597000 0x800>, <0xfd512074 0x4>;
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reg-names = "phy_mem", "dev_ref_clk_ctrl_mem";
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#phy-cells = <0>;
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vdda-phy-supply = <&pma8084_l4>;
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vdda-pll-supply = <&pma8084_l12>;
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vdda-phy-max-microamp = <50000>;
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vdda-pll-max-microamp = <1000>;
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};
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ufshc@0xfc598000 {
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...
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phys = <&ufsphy1>;
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};
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@ -1,256 +0,0 @@
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/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "phy-qcom-ufs-qmp-20nm.h"
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#define UFS_PHY_NAME "ufs_phy_qmp_20nm"
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static
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int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
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bool is_rate_B)
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{
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struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
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int tbl_size_A, tbl_size_B;
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u8 major = ufs_qcom_phy->host_ctrl_rev_major;
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u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;
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u16 step = ufs_qcom_phy->host_ctrl_rev_step;
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int err;
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if ((major == 0x1) && (minor == 0x002) && (step == 0x0000)) {
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tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_2_0);
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tbl_A = phy_cal_table_rate_A_1_2_0;
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} else if ((major == 0x1) && (minor == 0x003) && (step == 0x0000)) {
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tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_3_0);
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tbl_A = phy_cal_table_rate_A_1_3_0;
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} else {
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dev_err(ufs_qcom_phy->dev, "%s: Unknown UFS-PHY version, no calibration values\n",
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__func__);
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err = -ENODEV;
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goto out;
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}
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tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
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tbl_B = phy_cal_table_rate_B;
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err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,
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tbl_B, tbl_size_B, is_rate_B);
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if (err)
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dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",
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__func__, err);
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out:
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return err;
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}
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static
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void ufs_qcom_phy_qmp_20nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
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{
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phy_common->quirks =
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UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
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}
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static int ufs_qcom_phy_qmp_20nm_init(struct phy *generic_phy)
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{
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struct ufs_qcom_phy_qmp_20nm *phy = phy_get_drvdata(generic_phy);
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struct ufs_qcom_phy *phy_common = &phy->common_cfg;
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int err = 0;
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err = ufs_qcom_phy_init_clks(generic_phy, phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
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__func__, err);
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goto out;
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}
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err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
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__func__, err);
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goto out;
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}
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ufs_qcom_phy_qmp_20nm_advertise_quirks(phy_common);
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out:
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return err;
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}
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static
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void ufs_qcom_phy_qmp_20nm_power_control(struct ufs_qcom_phy *phy, bool val)
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{
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bool hibern8_exit_after_pwr_collapse = phy->quirks &
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UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
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if (val) {
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writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* Before any transactions involving PHY, ensure PHY knows
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* that it's analog rail is powered ON.
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*/
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mb();
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if (hibern8_exit_after_pwr_collapse) {
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/*
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* Give atleast 1us delay after restoring PHY analog
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* power.
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*/
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usleep_range(1, 2);
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writel_relaxed(0x0A, phy->mmio +
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QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
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writel_relaxed(0x08, phy->mmio +
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QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
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/*
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* Make sure workaround is deactivated before proceeding
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* with normal PHY operations.
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*/
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mb();
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}
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} else {
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if (hibern8_exit_after_pwr_collapse) {
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writel_relaxed(0x0A, phy->mmio +
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QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
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writel_relaxed(0x02, phy->mmio +
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QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
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/*
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* Make sure that above workaround is activated before
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* PHY analog power collapse.
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*/
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mb();
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}
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writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* ensure that PHY knows its PHY analog rail is going
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* to be powered down
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*/
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mb();
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}
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}
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static
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void ufs_qcom_phy_qmp_20nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
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{
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writel_relaxed(val & UFS_PHY_TX_LANE_ENABLE_MASK,
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phy->mmio + UFS_PHY_TX_LANE_ENABLE);
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mb();
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}
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static inline void ufs_qcom_phy_qmp_20nm_start_serdes(struct ufs_qcom_phy *phy)
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{
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u32 tmp;
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tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
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tmp &= ~MASK_SERDES_START;
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tmp |= (1 << OFFSET_SERDES_START);
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writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
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mb();
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}
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static int ufs_qcom_phy_qmp_20nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
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{
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int err = 0;
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u32 val;
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err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
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val, (val & MASK_PCS_READY), 10, 1000000);
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if (err)
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dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
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__func__, err);
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return err;
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}
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static const struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {
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.init = ufs_qcom_phy_qmp_20nm_init,
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.exit = ufs_qcom_phy_exit,
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.power_on = ufs_qcom_phy_power_on,
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.power_off = ufs_qcom_phy_power_off,
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.owner = THIS_MODULE,
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};
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static struct ufs_qcom_phy_specific_ops phy_20nm_ops = {
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.calibrate_phy = ufs_qcom_phy_qmp_20nm_phy_calibrate,
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.start_serdes = ufs_qcom_phy_qmp_20nm_start_serdes,
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.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_20nm_is_pcs_ready,
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.set_tx_lane_enable = ufs_qcom_phy_qmp_20nm_set_tx_lane_enable,
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.power_control = ufs_qcom_phy_qmp_20nm_power_control,
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};
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static int ufs_qcom_phy_qmp_20nm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy;
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struct ufs_qcom_phy_qmp_20nm *phy;
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int err = 0;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy) {
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dev_err(dev, "%s: failed to allocate phy\n", __func__);
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err = -ENOMEM;
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goto out;
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}
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generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
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&ufs_qcom_phy_qmp_20nm_phy_ops, &phy_20nm_ops);
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if (!generic_phy) {
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dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
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__func__);
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err = -EIO;
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goto out;
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}
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phy_set_drvdata(generic_phy, phy);
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strlcpy(phy->common_cfg.name, UFS_PHY_NAME,
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sizeof(phy->common_cfg.name));
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out:
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return err;
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}
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static int ufs_qcom_phy_qmp_20nm_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy = to_phy(dev);
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struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
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int err = 0;
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err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);
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if (err)
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dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",
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__func__, err);
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return err;
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}
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static const struct of_device_id ufs_qcom_phy_qmp_20nm_of_match[] = {
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{.compatible = "qcom,ufs-phy-qmp-20nm"},
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{},
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};
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MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_20nm_of_match);
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static struct platform_driver ufs_qcom_phy_qmp_20nm_driver = {
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.probe = ufs_qcom_phy_qmp_20nm_probe,
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.remove = ufs_qcom_phy_qmp_20nm_remove,
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.driver = {
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.of_match_table = ufs_qcom_phy_qmp_20nm_of_match,
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.name = "ufs_qcom_phy_qmp_20nm",
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},
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};
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module_platform_driver(ufs_qcom_phy_qmp_20nm_driver);
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MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 20nm");
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MODULE_LICENSE("GPL v2");
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@ -1,235 +0,0 @@
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/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef UFS_QCOM_PHY_QMP_20NM_H_
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#define UFS_QCOM_PHY_QMP_20NM_H_
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#include "phy-qcom-ufs-i.h"
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/* QCOM UFS PHY control registers */
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#define COM_OFF(x) (0x000 + x)
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#define PHY_OFF(x) (0xC00 + x)
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#define TX_OFF(n, x) (0x400 + (0x400 * n) + x)
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#define RX_OFF(n, x) (0x600 + (0x400 * n) + x)
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/* UFS PHY PLL block registers */
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#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x0)
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#define QSERDES_COM_PLL_VCOTAIL_EN COM_OFF(0x04)
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#define QSERDES_COM_PLL_CNTRL COM_OFF(0x14)
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#define QSERDES_COM_PLL_IP_SETI COM_OFF(0x24)
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#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL COM_OFF(0x28)
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#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x30)
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#define QSERDES_COM_PLL_CP_SETI COM_OFF(0x34)
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#define QSERDES_COM_PLL_IP_SETP COM_OFF(0x38)
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#define QSERDES_COM_PLL_CP_SETP COM_OFF(0x3C)
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#define QSERDES_COM_SYSCLK_EN_SEL_TXBAND COM_OFF(0x48)
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#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0x4C)
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#define QSERDES_COM_RESETSM_CNTRL2 COM_OFF(0x50)
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#define QSERDES_COM_PLLLOCK_CMP1 COM_OFF(0x90)
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#define QSERDES_COM_PLLLOCK_CMP2 COM_OFF(0x94)
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#define QSERDES_COM_PLLLOCK_CMP3 COM_OFF(0x98)
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#define QSERDES_COM_PLLLOCK_CMP_EN COM_OFF(0x9C)
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#define QSERDES_COM_BGTC COM_OFF(0xA0)
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#define QSERDES_COM_DEC_START1 COM_OFF(0xAC)
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#define QSERDES_COM_PLL_AMP_OS COM_OFF(0xB0)
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#define QSERDES_COM_RES_CODE_UP_OFFSET COM_OFF(0xD8)
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#define QSERDES_COM_RES_CODE_DN_OFFSET COM_OFF(0xDC)
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#define QSERDES_COM_DIV_FRAC_START1 COM_OFF(0x100)
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#define QSERDES_COM_DIV_FRAC_START2 COM_OFF(0x104)
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#define QSERDES_COM_DIV_FRAC_START3 COM_OFF(0x108)
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#define QSERDES_COM_DEC_START2 COM_OFF(0x10C)
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#define QSERDES_COM_PLL_RXTXEPCLK_EN COM_OFF(0x110)
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#define QSERDES_COM_PLL_CRCTRL COM_OFF(0x114)
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#define QSERDES_COM_PLL_CLKEPDIV COM_OFF(0x118)
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/* TX LANE n (0, 1) registers */
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#define QSERDES_TX_EMP_POST1_LVL(n) TX_OFF(n, 0x08)
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#define QSERDES_TX_DRV_LVL(n) TX_OFF(n, 0x0C)
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#define QSERDES_TX_LANE_MODE(n) TX_OFF(n, 0x54)
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/* RX LANE n (0, 1) registers */
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#define QSERDES_RX_CDR_CONTROL1(n) RX_OFF(n, 0x0)
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#define QSERDES_RX_CDR_CONTROL_HALF(n) RX_OFF(n, 0x8)
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#define QSERDES_RX_RX_EQ_GAIN1_LSB(n) RX_OFF(n, 0xA8)
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#define QSERDES_RX_RX_EQ_GAIN1_MSB(n) RX_OFF(n, 0xAC)
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#define QSERDES_RX_RX_EQ_GAIN2_LSB(n) RX_OFF(n, 0xB0)
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#define QSERDES_RX_RX_EQ_GAIN2_MSB(n) RX_OFF(n, 0xB4)
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#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(n) RX_OFF(n, 0xBC)
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#define QSERDES_RX_CDR_CONTROL_QUARTER(n) RX_OFF(n, 0xC)
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#define QSERDES_RX_SIGDET_CNTRL(n) RX_OFF(n, 0x100)
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/* UFS PHY registers */
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#define UFS_PHY_PHY_START PHY_OFF(0x00)
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#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x4)
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#define UFS_PHY_TX_LANE_ENABLE PHY_OFF(0x44)
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#define UFS_PHY_PWM_G1_CLK_DIVIDER PHY_OFF(0x08)
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#define UFS_PHY_PWM_G2_CLK_DIVIDER PHY_OFF(0x0C)
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#define UFS_PHY_PWM_G3_CLK_DIVIDER PHY_OFF(0x10)
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#define UFS_PHY_PWM_G4_CLK_DIVIDER PHY_OFF(0x14)
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#define UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER PHY_OFF(0x34)
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#define UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER PHY_OFF(0x38)
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#define UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER PHY_OFF(0x3C)
|
||||
#define UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER PHY_OFF(0x40)
|
||||
#define UFS_PHY_OMC_STATUS_RDVAL PHY_OFF(0x68)
|
||||
#define UFS_PHY_LINE_RESET_TIME PHY_OFF(0x28)
|
||||
#define UFS_PHY_LINE_RESET_GRANULARITY PHY_OFF(0x2C)
|
||||
#define UFS_PHY_TSYNC_RSYNC_CNTL PHY_OFF(0x48)
|
||||
#define UFS_PHY_PLL_CNTL PHY_OFF(0x50)
|
||||
#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x54)
|
||||
#define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x5C)
|
||||
#define UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL PHY_OFF(0x58)
|
||||
#define UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL PHY_OFF(0x60)
|
||||
#define UFS_PHY_CFG_CHANGE_CNT_VAL PHY_OFF(0x64)
|
||||
#define UFS_PHY_RX_SYNC_WAIT_TIME PHY_OFF(0x6C)
|
||||
#define UFS_PHY_TX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xB4)
|
||||
#define UFS_PHY_RX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xE0)
|
||||
#define UFS_PHY_TX_MIN_STALL_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xB8)
|
||||
#define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xE4)
|
||||
#define UFS_PHY_TX_MIN_SAVE_CONFIG_TIME_CAPABILITY PHY_OFF(0xBC)
|
||||
#define UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY PHY_OFF(0xE8)
|
||||
#define UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY PHY_OFF(0xFC)
|
||||
#define UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY PHY_OFF(0x100)
|
||||
#define UFS_PHY_RX_SIGDET_CTRL3 PHY_OFF(0x14c)
|
||||
#define UFS_PHY_RMMI_ATTR_CTRL PHY_OFF(0x160)
|
||||
#define UFS_PHY_RMMI_RX_CFGUPDT_L1 (1 << 7)
|
||||
#define UFS_PHY_RMMI_TX_CFGUPDT_L1 (1 << 6)
|
||||
#define UFS_PHY_RMMI_CFGWR_L1 (1 << 5)
|
||||
#define UFS_PHY_RMMI_CFGRD_L1 (1 << 4)
|
||||
#define UFS_PHY_RMMI_RX_CFGUPDT_L0 (1 << 3)
|
||||
#define UFS_PHY_RMMI_TX_CFGUPDT_L0 (1 << 2)
|
||||
#define UFS_PHY_RMMI_CFGWR_L0 (1 << 1)
|
||||
#define UFS_PHY_RMMI_CFGRD_L0 (1 << 0)
|
||||
#define UFS_PHY_RMMI_ATTRID PHY_OFF(0x164)
|
||||
#define UFS_PHY_RMMI_ATTRWRVAL PHY_OFF(0x168)
|
||||
#define UFS_PHY_RMMI_ATTRRDVAL_L0_STATUS PHY_OFF(0x16C)
|
||||
#define UFS_PHY_RMMI_ATTRRDVAL_L1_STATUS PHY_OFF(0x170)
|
||||
#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x174)
|
||||
|
||||
#define UFS_PHY_TX_LANE_ENABLE_MASK 0x3
|
||||
|
||||
/*
|
||||
* This structure represents the 20nm specific phy.
|
||||
* common_cfg MUST remain the first field in this structure
|
||||
* in case extra fields are added. This way, when calling
|
||||
* get_ufs_qcom_phy() of generic phy, we can extract the
|
||||
* common phy structure (struct ufs_qcom_phy) out of it
|
||||
* regardless of the relevant specific phy.
|
||||
*/
|
||||
struct ufs_qcom_phy_qmp_20nm {
|
||||
struct ufs_qcom_phy common_cfg;
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_2_0[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL3, 0x0D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(0), 0x2F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(0), 0x20),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(1), 0x2F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(1), 0x20),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3),
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_3_0[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL3, 0x0D),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x2b),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x38),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x3c),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_UP_OFFSET, 0x02),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_DN_OFFSET, 0x02),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x40),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3),
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1e),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -1,749 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "phy-qcom-ufs-i.h"
|
||||
|
||||
#define MAX_PROP_NAME 32
|
||||
#define VDDA_PHY_MIN_UV 1000000
|
||||
#define VDDA_PHY_MAX_UV 1000000
|
||||
#define VDDA_PLL_MIN_UV 1800000
|
||||
#define VDDA_PLL_MAX_UV 1800000
|
||||
#define VDDP_REF_CLK_MIN_UV 1200000
|
||||
#define VDDP_REF_CLK_MAX_UV 1200000
|
||||
|
||||
static int __ufs_qcom_phy_init_vreg(struct phy *, struct ufs_qcom_phy_vreg *,
|
||||
const char *, bool);
|
||||
static int ufs_qcom_phy_init_vreg(struct phy *, struct ufs_qcom_phy_vreg *,
|
||||
const char *);
|
||||
static int ufs_qcom_phy_base_init(struct platform_device *pdev,
|
||||
struct ufs_qcom_phy *phy_common);
|
||||
|
||||
int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
|
||||
struct ufs_qcom_phy_calibration *tbl_A,
|
||||
int tbl_size_A,
|
||||
struct ufs_qcom_phy_calibration *tbl_B,
|
||||
int tbl_size_B, bool is_rate_B)
|
||||
{
|
||||
int i;
|
||||
int ret = 0;
|
||||
|
||||
if (!tbl_A) {
|
||||
dev_err(ufs_qcom_phy->dev, "%s: tbl_A is NULL", __func__);
|
||||
ret = EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (i = 0; i < tbl_size_A; i++)
|
||||
writel_relaxed(tbl_A[i].cfg_value,
|
||||
ufs_qcom_phy->mmio + tbl_A[i].reg_offset);
|
||||
|
||||
/*
|
||||
* In case we would like to work in rate B, we need
|
||||
* to override a registers that were configured in rate A table
|
||||
* with registers of rate B table.
|
||||
* table.
|
||||
*/
|
||||
if (is_rate_B) {
|
||||
if (!tbl_B) {
|
||||
dev_err(ufs_qcom_phy->dev, "%s: tbl_B is NULL",
|
||||
__func__);
|
||||
ret = EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (i = 0; i < tbl_size_B; i++)
|
||||
writel_relaxed(tbl_B[i].cfg_value,
|
||||
ufs_qcom_phy->mmio + tbl_B[i].reg_offset);
|
||||
}
|
||||
|
||||
/* flush buffered writes */
|
||||
mb();
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate);
|
||||
|
||||
struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
|
||||
struct ufs_qcom_phy *common_cfg,
|
||||
const struct phy_ops *ufs_qcom_phy_gen_ops,
|
||||
struct ufs_qcom_phy_specific_ops *phy_spec_ops)
|
||||
{
|
||||
int err;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct phy *generic_phy = NULL;
|
||||
struct phy_provider *phy_provider;
|
||||
|
||||
err = ufs_qcom_phy_base_init(pdev, common_cfg);
|
||||
if (err) {
|
||||
dev_err(dev, "%s: phy base init failed %d\n", __func__, err);
|
||||
goto out;
|
||||
}
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
if (IS_ERR(phy_provider)) {
|
||||
err = PTR_ERR(phy_provider);
|
||||
dev_err(dev, "%s: failed to register phy %d\n", __func__, err);
|
||||
goto out;
|
||||
}
|
||||
|
||||
generic_phy = devm_phy_create(dev, NULL, ufs_qcom_phy_gen_ops);
|
||||
if (IS_ERR(generic_phy)) {
|
||||
err = PTR_ERR(generic_phy);
|
||||
dev_err(dev, "%s: failed to create phy %d\n", __func__, err);
|
||||
generic_phy = NULL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
common_cfg->phy_spec_ops = phy_spec_ops;
|
||||
common_cfg->dev = dev;
|
||||
|
||||
out:
|
||||
return generic_phy;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_generic_probe);
|
||||
|
||||
/*
|
||||
* This assumes the embedded phy structure inside generic_phy is of type
|
||||
* struct ufs_qcom_phy. In order to function properly it's crucial
|
||||
* to keep the embedded struct "struct ufs_qcom_phy common_cfg"
|
||||
* as the first inside generic_phy.
|
||||
*/
|
||||
struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy)
|
||||
{
|
||||
return (struct ufs_qcom_phy *)phy_get_drvdata(generic_phy);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(get_ufs_qcom_phy);
|
||||
|
||||
static
|
||||
int ufs_qcom_phy_base_init(struct platform_device *pdev,
|
||||
struct ufs_qcom_phy *phy_common)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *res;
|
||||
int err = 0;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_mem");
|
||||
phy_common->mmio = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR((void const *)phy_common->mmio)) {
|
||||
err = PTR_ERR((void const *)phy_common->mmio);
|
||||
phy_common->mmio = NULL;
|
||||
dev_err(dev, "%s: ioremap for phy_mem resource failed %d\n",
|
||||
__func__, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
/* "dev_ref_clk_ctrl_mem" is optional resource */
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"dev_ref_clk_ctrl_mem");
|
||||
phy_common->dev_ref_clk_ctrl_mmio = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR((void const *)phy_common->dev_ref_clk_ctrl_mmio))
|
||||
phy_common->dev_ref_clk_ctrl_mmio = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __ufs_qcom_phy_clk_get(struct phy *phy,
|
||||
const char *name, struct clk **clk_out, bool err_print)
|
||||
{
|
||||
struct clk *clk;
|
||||
int err = 0;
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
|
||||
struct device *dev = ufs_qcom_phy->dev;
|
||||
|
||||
clk = devm_clk_get(dev, name);
|
||||
if (IS_ERR(clk)) {
|
||||
err = PTR_ERR(clk);
|
||||
if (err_print)
|
||||
dev_err(dev, "failed to get %s err %d", name, err);
|
||||
} else {
|
||||
*clk_out = clk;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static
|
||||
int ufs_qcom_phy_clk_get(struct phy *phy,
|
||||
const char *name, struct clk **clk_out)
|
||||
{
|
||||
return __ufs_qcom_phy_clk_get(phy, name, clk_out, true);
|
||||
}
|
||||
|
||||
int
|
||||
ufs_qcom_phy_init_clks(struct phy *generic_phy,
|
||||
struct ufs_qcom_phy *phy_common)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = ufs_qcom_phy_clk_get(generic_phy, "tx_iface_clk",
|
||||
&phy_common->tx_iface_clk);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
err = ufs_qcom_phy_clk_get(generic_phy, "rx_iface_clk",
|
||||
&phy_common->rx_iface_clk);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk_src",
|
||||
&phy_common->ref_clk_src);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
/*
|
||||
* "ref_clk_parent" is optional hence don't abort init if it's not
|
||||
* found.
|
||||
*/
|
||||
__ufs_qcom_phy_clk_get(generic_phy, "ref_clk_parent",
|
||||
&phy_common->ref_clk_parent, false);
|
||||
|
||||
err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk",
|
||||
&phy_common->ref_clk);
|
||||
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_clks);
|
||||
|
||||
int
|
||||
ufs_qcom_phy_init_vregulators(struct phy *generic_phy,
|
||||
struct ufs_qcom_phy *phy_common)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vdda_pll,
|
||||
"vdda-pll");
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
err = ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vdda_phy,
|
||||
"vdda-phy");
|
||||
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
/* vddp-ref-clk-* properties are optional */
|
||||
__ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vddp_ref_clk,
|
||||
"vddp-ref-clk", true);
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_vregulators);
|
||||
|
||||
static int __ufs_qcom_phy_init_vreg(struct phy *phy,
|
||||
struct ufs_qcom_phy_vreg *vreg, const char *name, bool optional)
|
||||
{
|
||||
int err = 0;
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
|
||||
struct device *dev = ufs_qcom_phy->dev;
|
||||
|
||||
char prop_name[MAX_PROP_NAME];
|
||||
|
||||
vreg->name = kstrdup(name, GFP_KERNEL);
|
||||
if (!vreg->name) {
|
||||
err = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
vreg->reg = devm_regulator_get(dev, name);
|
||||
if (IS_ERR(vreg->reg)) {
|
||||
err = PTR_ERR(vreg->reg);
|
||||
vreg->reg = NULL;
|
||||
if (!optional)
|
||||
dev_err(dev, "failed to get %s, %d\n", name, err);
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (dev->of_node) {
|
||||
snprintf(prop_name, MAX_PROP_NAME, "%s-max-microamp", name);
|
||||
err = of_property_read_u32(dev->of_node,
|
||||
prop_name, &vreg->max_uA);
|
||||
if (err && err != -EINVAL) {
|
||||
dev_err(dev, "%s: failed to read %s\n",
|
||||
__func__, prop_name);
|
||||
goto out;
|
||||
} else if (err == -EINVAL || !vreg->max_uA) {
|
||||
if (regulator_count_voltages(vreg->reg) > 0) {
|
||||
dev_err(dev, "%s: %s is mandatory\n",
|
||||
__func__, prop_name);
|
||||
goto out;
|
||||
}
|
||||
err = 0;
|
||||
}
|
||||
snprintf(prop_name, MAX_PROP_NAME, "%s-always-on", name);
|
||||
if (of_get_property(dev->of_node, prop_name, NULL))
|
||||
vreg->is_always_on = true;
|
||||
else
|
||||
vreg->is_always_on = false;
|
||||
}
|
||||
|
||||
if (!strcmp(name, "vdda-pll")) {
|
||||
vreg->max_uV = VDDA_PLL_MAX_UV;
|
||||
vreg->min_uV = VDDA_PLL_MIN_UV;
|
||||
} else if (!strcmp(name, "vdda-phy")) {
|
||||
vreg->max_uV = VDDA_PHY_MAX_UV;
|
||||
vreg->min_uV = VDDA_PHY_MIN_UV;
|
||||
} else if (!strcmp(name, "vddp-ref-clk")) {
|
||||
vreg->max_uV = VDDP_REF_CLK_MAX_UV;
|
||||
vreg->min_uV = VDDP_REF_CLK_MIN_UV;
|
||||
}
|
||||
|
||||
out:
|
||||
if (err)
|
||||
kfree(vreg->name);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int ufs_qcom_phy_init_vreg(struct phy *phy,
|
||||
struct ufs_qcom_phy_vreg *vreg, const char *name)
|
||||
{
|
||||
return __ufs_qcom_phy_init_vreg(phy, vreg, name, false);
|
||||
}
|
||||
|
||||
static
|
||||
int ufs_qcom_phy_cfg_vreg(struct phy *phy,
|
||||
struct ufs_qcom_phy_vreg *vreg, bool on)
|
||||
{
|
||||
int ret = 0;
|
||||
struct regulator *reg = vreg->reg;
|
||||
const char *name = vreg->name;
|
||||
int min_uV;
|
||||
int uA_load;
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
|
||||
struct device *dev = ufs_qcom_phy->dev;
|
||||
|
||||
BUG_ON(!vreg);
|
||||
|
||||
if (regulator_count_voltages(reg) > 0) {
|
||||
min_uV = on ? vreg->min_uV : 0;
|
||||
ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
|
||||
if (ret) {
|
||||
dev_err(dev, "%s: %s set voltage failed, err=%d\n",
|
||||
__func__, name, ret);
|
||||
goto out;
|
||||
}
|
||||
uA_load = on ? vreg->max_uA : 0;
|
||||
ret = regulator_set_load(reg, uA_load);
|
||||
if (ret >= 0) {
|
||||
/*
|
||||
* regulator_set_load() returns new regulator
|
||||
* mode upon success.
|
||||
*/
|
||||
ret = 0;
|
||||
} else {
|
||||
dev_err(dev, "%s: %s set optimum mode(uA_load=%d) failed, err=%d\n",
|
||||
__func__, name, uA_load, ret);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static
|
||||
int ufs_qcom_phy_enable_vreg(struct phy *phy,
|
||||
struct ufs_qcom_phy_vreg *vreg)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
|
||||
struct device *dev = ufs_qcom_phy->dev;
|
||||
int ret = 0;
|
||||
|
||||
if (!vreg || vreg->enabled)
|
||||
goto out;
|
||||
|
||||
ret = ufs_qcom_phy_cfg_vreg(phy, vreg, true);
|
||||
if (ret) {
|
||||
dev_err(dev, "%s: ufs_qcom_phy_cfg_vreg() failed, err=%d\n",
|
||||
__func__, ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = regulator_enable(vreg->reg);
|
||||
if (ret) {
|
||||
dev_err(dev, "%s: enable failed, err=%d\n",
|
||||
__func__, ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
vreg->enabled = true;
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ufs_qcom_phy_enable_ref_clk(struct phy *generic_phy)
|
||||
{
|
||||
int ret = 0;
|
||||
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
if (phy->is_ref_clk_enabled)
|
||||
goto out;
|
||||
|
||||
/*
|
||||
* reference clock is propagated in a daisy-chained manner from
|
||||
* source to phy, so ungate them at each stage.
|
||||
*/
|
||||
ret = clk_prepare_enable(phy->ref_clk_src);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "%s: ref_clk_src enable failed %d\n",
|
||||
__func__, ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* "ref_clk_parent" is optional clock hence make sure that clk reference
|
||||
* is available before trying to enable the clock.
|
||||
*/
|
||||
if (phy->ref_clk_parent) {
|
||||
ret = clk_prepare_enable(phy->ref_clk_parent);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "%s: ref_clk_parent enable failed %d\n",
|
||||
__func__, ret);
|
||||
goto out_disable_src;
|
||||
}
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(phy->ref_clk);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "%s: ref_clk enable failed %d\n",
|
||||
__func__, ret);
|
||||
goto out_disable_parent;
|
||||
}
|
||||
|
||||
phy->is_ref_clk_enabled = true;
|
||||
goto out;
|
||||
|
||||
out_disable_parent:
|
||||
if (phy->ref_clk_parent)
|
||||
clk_disable_unprepare(phy->ref_clk_parent);
|
||||
out_disable_src:
|
||||
clk_disable_unprepare(phy->ref_clk_src);
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_ref_clk);
|
||||
|
||||
static
|
||||
int ufs_qcom_phy_disable_vreg(struct phy *phy,
|
||||
struct ufs_qcom_phy_vreg *vreg)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
|
||||
struct device *dev = ufs_qcom_phy->dev;
|
||||
int ret = 0;
|
||||
|
||||
if (!vreg || !vreg->enabled || vreg->is_always_on)
|
||||
goto out;
|
||||
|
||||
ret = regulator_disable(vreg->reg);
|
||||
|
||||
if (!ret) {
|
||||
/* ignore errors on applying disable config */
|
||||
ufs_qcom_phy_cfg_vreg(phy, vreg, false);
|
||||
vreg->enabled = false;
|
||||
} else {
|
||||
dev_err(dev, "%s: %s disable failed, err=%d\n",
|
||||
__func__, vreg->name, ret);
|
||||
}
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
void ufs_qcom_phy_disable_ref_clk(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
if (phy->is_ref_clk_enabled) {
|
||||
clk_disable_unprepare(phy->ref_clk);
|
||||
/*
|
||||
* "ref_clk_parent" is optional clock hence make sure that clk
|
||||
* reference is available before trying to disable the clock.
|
||||
*/
|
||||
if (phy->ref_clk_parent)
|
||||
clk_disable_unprepare(phy->ref_clk_parent);
|
||||
clk_disable_unprepare(phy->ref_clk_src);
|
||||
phy->is_ref_clk_enabled = false;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_ref_clk);
|
||||
|
||||
#define UFS_REF_CLK_EN (1 << 5)
|
||||
|
||||
static void ufs_qcom_phy_dev_ref_clk_ctrl(struct phy *generic_phy, bool enable)
|
||||
{
|
||||
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
if (phy->dev_ref_clk_ctrl_mmio &&
|
||||
(enable ^ phy->is_dev_ref_clk_enabled)) {
|
||||
u32 temp = readl_relaxed(phy->dev_ref_clk_ctrl_mmio);
|
||||
|
||||
if (enable)
|
||||
temp |= UFS_REF_CLK_EN;
|
||||
else
|
||||
temp &= ~UFS_REF_CLK_EN;
|
||||
|
||||
/*
|
||||
* If we are here to disable this clock immediately after
|
||||
* entering into hibern8, we need to make sure that device
|
||||
* ref_clk is active atleast 1us after the hibern8 enter.
|
||||
*/
|
||||
if (!enable)
|
||||
udelay(1);
|
||||
|
||||
writel_relaxed(temp, phy->dev_ref_clk_ctrl_mmio);
|
||||
/* ensure that ref_clk is enabled/disabled before we return */
|
||||
wmb();
|
||||
/*
|
||||
* If we call hibern8 exit after this, we need to make sure that
|
||||
* device ref_clk is stable for atleast 1us before the hibern8
|
||||
* exit command.
|
||||
*/
|
||||
if (enable)
|
||||
udelay(1);
|
||||
|
||||
phy->is_dev_ref_clk_enabled = enable;
|
||||
}
|
||||
}
|
||||
|
||||
void ufs_qcom_phy_enable_dev_ref_clk(struct phy *generic_phy)
|
||||
{
|
||||
ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, true);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_dev_ref_clk);
|
||||
|
||||
void ufs_qcom_phy_disable_dev_ref_clk(struct phy *generic_phy)
|
||||
{
|
||||
ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, false);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_dev_ref_clk);
|
||||
|
||||
/* Turn ON M-PHY RMMI interface clocks */
|
||||
int ufs_qcom_phy_enable_iface_clk(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
|
||||
int ret = 0;
|
||||
|
||||
if (phy->is_iface_clk_enabled)
|
||||
goto out;
|
||||
|
||||
ret = clk_prepare_enable(phy->tx_iface_clk);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "%s: tx_iface_clk enable failed %d\n",
|
||||
__func__, ret);
|
||||
goto out;
|
||||
}
|
||||
ret = clk_prepare_enable(phy->rx_iface_clk);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(phy->tx_iface_clk);
|
||||
dev_err(phy->dev, "%s: rx_iface_clk enable failed %d. disabling also tx_iface_clk\n",
|
||||
__func__, ret);
|
||||
goto out;
|
||||
}
|
||||
phy->is_iface_clk_enabled = true;
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_iface_clk);
|
||||
|
||||
/* Turn OFF M-PHY RMMI interface clocks */
|
||||
void ufs_qcom_phy_disable_iface_clk(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
if (phy->is_iface_clk_enabled) {
|
||||
clk_disable_unprepare(phy->tx_iface_clk);
|
||||
clk_disable_unprepare(phy->rx_iface_clk);
|
||||
phy->is_iface_clk_enabled = false;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_iface_clk);
|
||||
|
||||
int ufs_qcom_phy_start_serdes(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
|
||||
int ret = 0;
|
||||
|
||||
if (!ufs_qcom_phy->phy_spec_ops->start_serdes) {
|
||||
dev_err(ufs_qcom_phy->dev, "%s: start_serdes() callback is not supported\n",
|
||||
__func__);
|
||||
ret = -ENOTSUPP;
|
||||
} else {
|
||||
ufs_qcom_phy->phy_spec_ops->start_serdes(ufs_qcom_phy);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_start_serdes);
|
||||
|
||||
int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
|
||||
int ret = 0;
|
||||
|
||||
if (!ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable) {
|
||||
dev_err(ufs_qcom_phy->dev, "%s: set_tx_lane_enable() callback is not supported\n",
|
||||
__func__);
|
||||
ret = -ENOTSUPP;
|
||||
} else {
|
||||
ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable(ufs_qcom_phy,
|
||||
tx_lanes);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_set_tx_lane_enable);
|
||||
|
||||
void ufs_qcom_phy_save_controller_version(struct phy *generic_phy,
|
||||
u8 major, u16 minor, u16 step)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
ufs_qcom_phy->host_ctrl_rev_major = major;
|
||||
ufs_qcom_phy->host_ctrl_rev_minor = minor;
|
||||
ufs_qcom_phy->host_ctrl_rev_step = step;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_save_controller_version);
|
||||
|
||||
int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
|
||||
int ret = 0;
|
||||
|
||||
if (!ufs_qcom_phy->phy_spec_ops->calibrate_phy) {
|
||||
dev_err(ufs_qcom_phy->dev, "%s: calibrate_phy() callback is not supported\n",
|
||||
__func__);
|
||||
ret = -ENOTSUPP;
|
||||
} else {
|
||||
ret = ufs_qcom_phy->phy_spec_ops->
|
||||
calibrate_phy(ufs_qcom_phy, is_rate_B);
|
||||
if (ret)
|
||||
dev_err(ufs_qcom_phy->dev, "%s: calibrate_phy() failed %d\n",
|
||||
__func__, ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate_phy);
|
||||
|
||||
int ufs_qcom_phy_remove(struct phy *generic_phy,
|
||||
struct ufs_qcom_phy *ufs_qcom_phy)
|
||||
{
|
||||
phy_power_off(generic_phy);
|
||||
|
||||
kfree(ufs_qcom_phy->vdda_pll.name);
|
||||
kfree(ufs_qcom_phy->vdda_phy.name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_remove);
|
||||
|
||||
int ufs_qcom_phy_exit(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
if (ufs_qcom_phy->is_powered_on)
|
||||
phy_power_off(generic_phy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_exit);
|
||||
|
||||
int ufs_qcom_phy_is_pcs_ready(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
if (!ufs_qcom_phy->phy_spec_ops->is_physical_coding_sublayer_ready) {
|
||||
dev_err(ufs_qcom_phy->dev, "%s: is_physical_coding_sublayer_ready() callback is not supported\n",
|
||||
__func__);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
return ufs_qcom_phy->phy_spec_ops->
|
||||
is_physical_coding_sublayer_ready(ufs_qcom_phy);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_is_pcs_ready);
|
||||
|
||||
int ufs_qcom_phy_power_on(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
|
||||
struct device *dev = phy_common->dev;
|
||||
int err;
|
||||
|
||||
err = ufs_qcom_phy_enable_vreg(generic_phy, &phy_common->vdda_phy);
|
||||
if (err) {
|
||||
dev_err(dev, "%s enable vdda_phy failed, err=%d\n",
|
||||
__func__, err);
|
||||
goto out;
|
||||
}
|
||||
|
||||
phy_common->phy_spec_ops->power_control(phy_common, true);
|
||||
|
||||
/* vdda_pll also enables ref clock LDOs so enable it first */
|
||||
err = ufs_qcom_phy_enable_vreg(generic_phy, &phy_common->vdda_pll);
|
||||
if (err) {
|
||||
dev_err(dev, "%s enable vdda_pll failed, err=%d\n",
|
||||
__func__, err);
|
||||
goto out_disable_phy;
|
||||
}
|
||||
|
||||
err = ufs_qcom_phy_enable_ref_clk(generic_phy);
|
||||
if (err) {
|
||||
dev_err(dev, "%s enable phy ref clock failed, err=%d\n",
|
||||
__func__, err);
|
||||
goto out_disable_pll;
|
||||
}
|
||||
|
||||
/* enable device PHY ref_clk pad rail */
|
||||
if (phy_common->vddp_ref_clk.reg) {
|
||||
err = ufs_qcom_phy_enable_vreg(generic_phy,
|
||||
&phy_common->vddp_ref_clk);
|
||||
if (err) {
|
||||
dev_err(dev, "%s enable vddp_ref_clk failed, err=%d\n",
|
||||
__func__, err);
|
||||
goto out_disable_ref_clk;
|
||||
}
|
||||
}
|
||||
|
||||
phy_common->is_powered_on = true;
|
||||
goto out;
|
||||
|
||||
out_disable_ref_clk:
|
||||
ufs_qcom_phy_disable_ref_clk(generic_phy);
|
||||
out_disable_pll:
|
||||
ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_pll);
|
||||
out_disable_phy:
|
||||
ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_phy);
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_on);
|
||||
|
||||
int ufs_qcom_phy_power_off(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
phy_common->phy_spec_ops->power_control(phy_common, false);
|
||||
|
||||
if (phy_common->vddp_ref_clk.reg)
|
||||
ufs_qcom_phy_disable_vreg(generic_phy,
|
||||
&phy_common->vddp_ref_clk);
|
||||
ufs_qcom_phy_disable_ref_clk(generic_phy);
|
||||
|
||||
ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_pll);
|
||||
ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_phy);
|
||||
phy_common->is_powered_on = false;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_off);
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,258 +0,0 @@
|
|||
/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef UFS_QCOM_H_
|
||||
#define UFS_QCOM_H_
|
||||
|
||||
#define MAX_UFS_QCOM_HOSTS 1
|
||||
#define MAX_U32 (~(u32)0)
|
||||
#define MPHY_TX_FSM_STATE 0x41
|
||||
#define TX_FSM_HIBERN8 0x1
|
||||
#define HBRN8_POLL_TOUT_MS 100
|
||||
#define DEFAULT_CLK_RATE_HZ 1000000
|
||||
#define BUS_VECTOR_NAME_LEN 32
|
||||
|
||||
#define UFS_HW_VER_MAJOR_SHFT (28)
|
||||
#define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT)
|
||||
#define UFS_HW_VER_MINOR_SHFT (16)
|
||||
#define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT)
|
||||
#define UFS_HW_VER_STEP_SHFT (0)
|
||||
#define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT)
|
||||
|
||||
/* vendor specific pre-defined parameters */
|
||||
#define SLOW 1
|
||||
#define FAST 2
|
||||
|
||||
#define UFS_QCOM_LIMIT_NUM_LANES_RX 2
|
||||
#define UFS_QCOM_LIMIT_NUM_LANES_TX 2
|
||||
#define UFS_QCOM_LIMIT_HSGEAR_RX UFS_HS_G3
|
||||
#define UFS_QCOM_LIMIT_HSGEAR_TX UFS_HS_G3
|
||||
#define UFS_QCOM_LIMIT_PWMGEAR_RX UFS_PWM_G4
|
||||
#define UFS_QCOM_LIMIT_PWMGEAR_TX UFS_PWM_G4
|
||||
#define UFS_QCOM_LIMIT_RX_PWR_PWM SLOW_MODE
|
||||
#define UFS_QCOM_LIMIT_TX_PWR_PWM SLOW_MODE
|
||||
#define UFS_QCOM_LIMIT_RX_PWR_HS FAST_MODE
|
||||
#define UFS_QCOM_LIMIT_TX_PWR_HS FAST_MODE
|
||||
#define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B
|
||||
#define UFS_QCOM_LIMIT_DESIRED_MODE FAST
|
||||
|
||||
/* QCOM UFS host controller vendor specific registers */
|
||||
enum {
|
||||
REG_UFS_SYS1CLK_1US = 0xC0,
|
||||
REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
|
||||
REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
|
||||
REG_UFS_PA_ERR_CODE = 0xCC,
|
||||
REG_UFS_RETRY_TIMER_REG = 0xD0,
|
||||
REG_UFS_PA_LINK_STARTUP_TIMER = 0xD8,
|
||||
REG_UFS_CFG1 = 0xDC,
|
||||
REG_UFS_CFG2 = 0xE0,
|
||||
REG_UFS_HW_VERSION = 0xE4,
|
||||
|
||||
UFS_TEST_BUS = 0xE8,
|
||||
UFS_TEST_BUS_CTRL_0 = 0xEC,
|
||||
UFS_TEST_BUS_CTRL_1 = 0xF0,
|
||||
UFS_TEST_BUS_CTRL_2 = 0xF4,
|
||||
UFS_UNIPRO_CFG = 0xF8,
|
||||
|
||||
/*
|
||||
* QCOM UFS host controller vendor specific registers
|
||||
* added in HW Version 3.0.0
|
||||
*/
|
||||
UFS_AH8_CFG = 0xFC,
|
||||
};
|
||||
|
||||
/* QCOM UFS host controller vendor specific debug registers */
|
||||
enum {
|
||||
UFS_DBG_RD_REG_UAWM = 0x100,
|
||||
UFS_DBG_RD_REG_UARM = 0x200,
|
||||
UFS_DBG_RD_REG_TXUC = 0x300,
|
||||
UFS_DBG_RD_REG_RXUC = 0x400,
|
||||
UFS_DBG_RD_REG_DFC = 0x500,
|
||||
UFS_DBG_RD_REG_TRLUT = 0x600,
|
||||
UFS_DBG_RD_REG_TMRLUT = 0x700,
|
||||
UFS_UFS_DBG_RD_REG_OCSC = 0x800,
|
||||
|
||||
UFS_UFS_DBG_RD_DESC_RAM = 0x1500,
|
||||
UFS_UFS_DBG_RD_PRDT_RAM = 0x1700,
|
||||
UFS_UFS_DBG_RD_RESP_RAM = 0x1800,
|
||||
UFS_UFS_DBG_RD_EDTL_RAM = 0x1900,
|
||||
};
|
||||
|
||||
#define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x)
|
||||
#define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x)
|
||||
|
||||
/* bit definitions for REG_UFS_CFG1 register */
|
||||
#define QUNIPRO_SEL UFS_BIT(0)
|
||||
#define TEST_BUS_EN BIT(18)
|
||||
#define TEST_BUS_SEL GENMASK(22, 19)
|
||||
|
||||
/* bit definitions for REG_UFS_CFG2 register */
|
||||
#define UAWM_HW_CGC_EN (1 << 0)
|
||||
#define UARM_HW_CGC_EN (1 << 1)
|
||||
#define TXUC_HW_CGC_EN (1 << 2)
|
||||
#define RXUC_HW_CGC_EN (1 << 3)
|
||||
#define DFC_HW_CGC_EN (1 << 4)
|
||||
#define TRLUT_HW_CGC_EN (1 << 5)
|
||||
#define TMRLUT_HW_CGC_EN (1 << 6)
|
||||
#define OCSC_HW_CGC_EN (1 << 7)
|
||||
|
||||
/* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
|
||||
#define TEST_BUS_SUB_SEL_MASK 0x1F /* All XXX_SEL fields are 5 bits wide */
|
||||
|
||||
#define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
|
||||
TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
|
||||
DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\
|
||||
TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
|
||||
|
||||
/* bit offset */
|
||||
enum {
|
||||
OFFSET_UFS_PHY_SOFT_RESET = 1,
|
||||
OFFSET_CLK_NS_REG = 10,
|
||||
};
|
||||
|
||||
/* bit masks */
|
||||
enum {
|
||||
MASK_UFS_PHY_SOFT_RESET = 0x2,
|
||||
MASK_TX_SYMBOL_CLK_1US_REG = 0x3FF,
|
||||
MASK_CLK_NS_REG = 0xFFFC00,
|
||||
};
|
||||
|
||||
enum ufs_qcom_phy_init_type {
|
||||
UFS_PHY_INIT_FULL,
|
||||
UFS_PHY_INIT_CFG_RESTORE,
|
||||
};
|
||||
|
||||
/* QCOM UFS debug print bit mask */
|
||||
#define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0)
|
||||
#define UFS_QCOM_DBG_PRINT_ICE_REGS_EN BIT(1)
|
||||
#define UFS_QCOM_DBG_PRINT_TEST_BUS_EN BIT(2)
|
||||
|
||||
#define UFS_QCOM_DBG_PRINT_ALL \
|
||||
(UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_ICE_REGS_EN | \
|
||||
UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
|
||||
|
||||
/* QUniPro Vendor specific attributes */
|
||||
#define DME_VS_CORE_CLK_CTRL 0xD002
|
||||
/* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
|
||||
#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8)
|
||||
#define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF
|
||||
|
||||
static inline void
|
||||
ufs_qcom_get_controller_revision(struct ufs_hba *hba,
|
||||
u8 *major, u16 *minor, u16 *step)
|
||||
{
|
||||
u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
|
||||
|
||||
*major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT;
|
||||
*minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT;
|
||||
*step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT;
|
||||
};
|
||||
|
||||
static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
|
||||
{
|
||||
ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
|
||||
1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
|
||||
|
||||
/*
|
||||
* Make sure assertion of ufs phy reset is written to
|
||||
* register before returning
|
||||
*/
|
||||
mb();
|
||||
}
|
||||
|
||||
static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
|
||||
{
|
||||
ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
|
||||
0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
|
||||
|
||||
/*
|
||||
* Make sure de-assertion of ufs phy reset is written to
|
||||
* register before returning
|
||||
*/
|
||||
mb();
|
||||
}
|
||||
|
||||
struct ufs_qcom_bus_vote {
|
||||
uint32_t client_handle;
|
||||
uint32_t curr_vote;
|
||||
int min_bw_vote;
|
||||
int max_bw_vote;
|
||||
int saved_vote;
|
||||
bool is_max_bw_needed;
|
||||
struct device_attribute max_bus_bw;
|
||||
};
|
||||
|
||||
/* Host controller hardware version: major.minor.step */
|
||||
struct ufs_hw_version {
|
||||
u16 step;
|
||||
u16 minor;
|
||||
u8 major;
|
||||
};
|
||||
|
||||
struct ufs_qcom_testbus {
|
||||
u8 select_major;
|
||||
u8 select_minor;
|
||||
};
|
||||
|
||||
struct ufs_qcom_host {
|
||||
/*
|
||||
* Set this capability if host controller supports the QUniPro mode
|
||||
* and if driver wants the Host controller to operate in QUniPro mode.
|
||||
* Note: By default this capability will be kept enabled if host
|
||||
* controller supports the QUniPro mode.
|
||||
*/
|
||||
#define UFS_QCOM_CAP_QUNIPRO UFS_BIT(0)
|
||||
|
||||
/*
|
||||
* Set this capability if host controller can retain the secure
|
||||
* configuration even after UFS controller core power collapse.
|
||||
*/
|
||||
#define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE UFS_BIT(1)
|
||||
u32 caps;
|
||||
|
||||
struct phy *generic_phy;
|
||||
struct ufs_hba *hba;
|
||||
struct ufs_qcom_bus_vote bus_vote;
|
||||
struct ufs_pa_layer_attr dev_req_params;
|
||||
struct clk *rx_l0_sync_clk;
|
||||
struct clk *tx_l0_sync_clk;
|
||||
struct clk *rx_l1_sync_clk;
|
||||
struct clk *tx_l1_sync_clk;
|
||||
bool is_lane_clks_enabled;
|
||||
|
||||
void __iomem *dev_ref_clk_ctrl_mmio;
|
||||
bool is_dev_ref_clk_enabled;
|
||||
struct ufs_hw_version hw_ver;
|
||||
|
||||
u32 dev_ref_clk_en_mask;
|
||||
|
||||
/* Bitmask for enabling debug prints */
|
||||
u32 dbg_print_en;
|
||||
struct ufs_qcom_testbus testbus;
|
||||
};
|
||||
|
||||
#define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba)
|
||||
#define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba)
|
||||
#define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
|
||||
|
||||
int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
|
||||
|
||||
static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host)
|
||||
{
|
||||
if (host->caps & UFS_QCOM_CAP_QUNIPRO)
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
#endif /* UFS_QCOM_H_ */
|
||||
|
|
@ -1,59 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PHY_QCOM_UFS_H_
|
||||
#define PHY_QCOM_UFS_H_
|
||||
|
||||
#include "phy.h"
|
||||
|
||||
/**
|
||||
* ufs_qcom_phy_enable_ref_clk() - Enable the phy
|
||||
* ref clock.
|
||||
* @phy: reference to a generic phy
|
||||
*
|
||||
* returns 0 for success, and non-zero for error.
|
||||
*/
|
||||
int ufs_qcom_phy_enable_ref_clk(struct phy *phy);
|
||||
|
||||
/**
|
||||
* ufs_qcom_phy_disable_ref_clk() - Disable the phy
|
||||
* ref clock.
|
||||
* @phy: reference to a generic phy.
|
||||
*/
|
||||
void ufs_qcom_phy_disable_ref_clk(struct phy *phy);
|
||||
|
||||
/**
|
||||
* ufs_qcom_phy_enable_dev_ref_clk() - Enable the device
|
||||
* ref clock.
|
||||
* @phy: reference to a generic phy.
|
||||
*/
|
||||
void ufs_qcom_phy_enable_dev_ref_clk(struct phy *phy);
|
||||
|
||||
/**
|
||||
* ufs_qcom_phy_disable_dev_ref_clk() - Disable the device
|
||||
* ref clock.
|
||||
* @phy: reference to a generic phy.
|
||||
*/
|
||||
void ufs_qcom_phy_disable_dev_ref_clk(struct phy *phy);
|
||||
|
||||
int ufs_qcom_phy_enable_iface_clk(struct phy *phy);
|
||||
void ufs_qcom_phy_disable_iface_clk(struct phy *phy);
|
||||
int ufs_qcom_phy_start_serdes(struct phy *phy);
|
||||
int ufs_qcom_phy_set_tx_lane_enable(struct phy *phy, u32 tx_lanes);
|
||||
int ufs_qcom_phy_calibrate_phy(struct phy *phy, bool is_rate_B);
|
||||
int ufs_qcom_phy_is_pcs_ready(struct phy *phy);
|
||||
void ufs_qcom_phy_save_controller_version(struct phy *phy,
|
||||
u8 major, u16 minor, u16 step);
|
||||
|
||||
#endif /* PHY_QCOM_UFS_H_ */
|
||||
Loading…
Add table
Reference in a new issue