evie/android_kernel_oneplus_msm8998
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ARM: dts: msm: add mdss smmu register range for msm8996

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Add mdss smmu context bank register range for
msm8996 target.

Change-Id: I863f7e57cce9fa12e0d8a603ac50c42775d62414
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This commit is contained in:
Dhaval Patel 2016-03-18 14:47:42 -07:00 • committed by Kyle Yan
parent fdef8552e6
commit 3c8a08cef8
1 changed files with 24 additions and 0 deletions
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24
arch/arm/boot/dts/qcom/msm8996-mdss.dtsi
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@ -20,6 +20,9 @@
interrupts = <0 83 0>;
vdd-supply = <&gdsc_mdss>;
#address-cells = <1>;
#size-cells = <1>;
/* Bus Scale Settings */
qcom,msm-bus,name = "mdss_mdp";
qcom,msm-bus,num-cases = <3>;
@ -199,6 +202,19 @@
"PP_0", "PP_1", "PP_4",
"DSC_0", "DSC_1";
qcom,regs-dump-xin-id-mdp = <0xff
0xff 0xff 0xff 0xff 0xff
0x0 0x0 0x4 0x4
0x8 0x8 0xc 0xc
0x1 0x1 0x5 0x5
0x9 0x9 0xd 0xd
0x2 0xa
0x7 0x7
0xff 0xff 0xff
0xff 0xff 0xff
0xff 0xff
0x3 0xb 0x6>;
/* buffer parameters to calculate prefill bandwidth */
qcom,mdss-prefill-outstanding-buffer-bytes = <0>;
qcom,mdss-prefill-y-buffer-bytes = <0>;
@ -221,6 +237,8 @@
smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb {
compatible = "qcom,smmu_mdp_unsec";
iommus = <&mdp_smmu 0>;
reg = <0x00d08000 0xd00>;
reg-names = "mmu_cb";
gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>;
clocks = <&clock_mmss clk_smmu_mdp_ahb_clk>,
<&clock_mmss clk_mmagic_mdss_axi_clk>,
@ -232,6 +250,8 @@
smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
compatible = "qcom,smmu_rot_unsec";
iommus = <&rot_smmu 0>;
reg = <0x00d09000 0xd00>;
reg-names = "mmu_cb";
gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>;
clocks = <&clock_mmss clk_smmu_rot_ahb_clk>,
<&clock_mmss clk_mmagic_mdss_axi_clk>,
@ -243,6 +263,8 @@
smmu_mdp_sec: qcom,smmu_mdp_sec_cb {
compatible = "qcom,smmu_mdp_sec";
iommus = <&mdp_smmu 1>;
reg = <0x00d0a000 0xd00>;
reg-names = "mmu_cb";
gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>;
clocks = <&clock_mmss clk_smmu_mdp_ahb_clk>,
<&clock_mmss clk_mmagic_mdss_axi_clk>,
@ -254,6 +276,8 @@
smmu_rot_sec: qcom,smmu_rot_sec_cb {
compatible = "qcom,smmu_rot_sec";
iommus = <&rot_smmu 1>;
reg = <0x00d0b000 0xd00>;
reg-names = "mmu_cb";
gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>;
clocks = <&clock_mmss clk_smmu_rot_ahb_clk>,
<&clock_mmss clk_mmagic_mdss_axi_clk>,