ARM: dts: msm: rename mdss_mdp to sde_kms and add HDMI TX device node
Rename mdss_mdp to sde_kms in the device tree to reflect the new display DRM driver terminology and add support for HDMI TX device node Change-Id: Ide5dc6a5939945a3e993eca650c66a56f3955140 Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
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3 changed files with 80 additions and 4 deletions
22
Documentation/devicetree/bindings/drm/msm/hdmi-display.txt
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Documentation/devicetree/bindings/drm/msm/hdmi-display.txt
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@ -0,0 +1,22 @@
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Qualcomm Technologies,Inc. Adreno/Snapdragon hdmi display manager
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Required properties:
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- compatible: "qcom,hdmi-display"
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- label: label of this display manager
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Optional properties:
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- qcom,display-type: display type of this manager. It could be "primary",
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"secondary", "tertiary", etc.
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Example:
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/ {
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...
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hdmi_display: qcom,hdmi-display {
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compatible = "qcom,hdmi-display";
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label = "hdmi_display";
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qcom,display-type = "secondary";
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};
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};
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@ -17,8 +17,15 @@
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cell-index = <0>;
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label = "wb_display";
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};
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sde_hdmi: qcom,hdmi-display {
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compatible = "qcom,hdmi-display";
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label = "sde_hdmi";
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qcom,display-type = "secondary";
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};
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};
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&mdss_mdp {
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connectors = <&sde_wb>;
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&sde_kms {
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connectors = <&sde_hdmi_tx &sde_hdmi &sde_wb>;
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};
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@ -11,7 +11,7 @@
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*/
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&soc {
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mdss_mdp: qcom,mdss_mdp@c900000 {
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sde_kms: qcom,sde_kms@c900000 {
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compatible = "qcom,sde-kms";
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reg = <0x0c900000 0x90000>,
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<0x0c9b0000 0x1040>;
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@ -136,7 +136,7 @@
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};
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};
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smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb {
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smmu_kms_unsec: qcom,smmu_kms_unsec_cb {
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compatible = "qcom,smmu_mdp_unsec";
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iommus = <&mmss_smmu 0>;
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};
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<1 590 0 320000>;
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};
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};
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sde_hdmi_tx: qcom,hdmi_tx_8998@c9a0000 {
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cell-index = <0>;
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compatible = "qcom,hdmi-tx-8998";
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reg = <0xc9a0000 0x50c>,
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<0x780000 0x621c>,
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<0xc9e0000 0x28>;
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reg-names = "core_physical", "qfprom_physical", "hdcp_physical";
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interrupt-parent = <&sde_kms>;
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interrupts = <8 0>;
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qcom,hdmi-tx-ddc-clk-gpio = <&tlmm 32 0>;
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qcom,hdmi-tx-ddc-data-gpio = <&tlmm 33 0>;
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qcom,hdmi-tx-hpd-gpio = <&tlmm 34 0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&mdss_hdmi_hpd_active
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&mdss_hdmi_ddc_active
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&mdss_hdmi_cec_active>;
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pinctrl-1 = <&mdss_hdmi_hpd_suspend
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&mdss_hdmi_ddc_suspend
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&mdss_hdmi_cec_suspend>;
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hpd-gdsc-supply = <&gdsc_mdss>;
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qcom,supply-names = "hpd-gdsc";
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qcom,min-voltage-level = <0>;
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qcom,max-voltage-level = <0>;
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qcom,enable-load = <0>;
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qcom,disable-load = <0>;
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qcom,msm_ext_disp = <&msm_ext_disp>;
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clocks = <&clock_mmss clk_mmss_mnoc_ahb_clk>,
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<&clock_mmss clk_mmss_mdss_ahb_clk>,
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<&clock_mmss clk_mmss_mdss_hdmi_clk>,
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<&clock_mmss clk_mmss_mdss_mdp_clk>,
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<&clock_mmss clk_mmss_mdss_hdmi_dp_ahb_clk>,
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<&clock_mmss clk_mmss_mdss_extpclk_clk>,
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<&clock_mmss clk_mmss_mnoc_ahb_clk>,
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<&clock_mmss clk_mmss_misc_ahb_clk>,
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<&clock_mmss clk_mmss_mdss_axi_clk>;
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clock-names = "hpd_mnoc_clk", "hpd_iface_clk",
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"hpd_core_clk", "hpd_mdp_core_clk",
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"hpd_alt_iface_clk", "core_extp_clk",
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"mnoc_clk","hpd_misc_ahb_clk",
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"hpd_bus_clk";
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/*qcom,mdss-fb-map = <&mdss_fb2>;*/
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qcom,pluggable;
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};
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};
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#include "msm8998-sde-display.dtsi"
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