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ASoC: sdm660_cdc: Fix HPH CnP and kernel panic issue on sdm660-internal

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Pop is observed after we start playback on hph.
This is because we do not enable both compander
channels at the same time which is not according to
qcrg. Amplitude of pop gets reduced after
corresponding change is made.
Also kernel panic is observed during SSR. This is because
DSP does not get sufficient time to bring up LPASS after SSR.
An increase in ADSP Ready timeout resolves the issue.

CRs-Fixed: 2101404
Change-Id: Iaea0f5060cdd87754e074ecbba18b5045cd4351a
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
This commit is contained in:
Vatsal Bucha 2017-09-11 14:13:27 +05:30
parent d3c53d2a43
commit 3e3ba94fb5
2 changed files with 31 additions and 5 deletions
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4
sound/soc/codecs/sdm660_cdc/msm-analog-cdc.c
View file

@ -49,10 +49,10 @@
#define BUS_DOWN 1
/*
* 50 Milliseconds sufficient for DSP bring up in the lpass
* 200 Milliseconds sufficient for DSP bring up in the lpass
* after Sub System Restart
*/
#define ADSP_STATE_READY_TIMEOUT_MS 50
#define ADSP_STATE_READY_TIMEOUT_MS 200
#define EAR_PMD 0
#define EAR_PMU 1

32
sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c
View file

@ -215,6 +215,7 @@ static int msm_dig_cdc_codec_config_compander(struct snd_soc_codec *codec,
{
struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec);
int comp_ch_bits_set = 0x03;
int comp_ch_value;
dev_dbg(codec->dev, "%s: event %d shift %d, enabled %d\n",
__func__, event, interp_n,
@ -234,15 +235,40 @@ static int msm_dig_cdc_codec_config_compander(struct snd_soc_codec *codec,
dig_cdc->set_compander_mode(dig_cdc->handle, 0x00);
return 0;
};
comp_ch_value = snd_soc_read(codec,
MSM89XX_CDC_CORE_COMP0_B1_CTL);
if (interp_n == 0) {
if ((comp_ch_value & 0x02) == 0x02) {
dev_dbg(codec->dev,
"%s comp ch already enabled\n",
__func__);
return 0;
}
}
if (interp_n == 1) {
if ((comp_ch_value & 0x01) == 0x01) {
dev_dbg(codec->dev,
"%s comp ch already enabled\n",
__func__);
return 0;
}
}
dig_cdc->set_compander_mode(dig_cdc->handle, 0x08);
/* Enable Compander Clock */
snd_soc_update_bits(codec,
MSM89XX_CDC_CORE_COMP0_B2_CTL, 0x0F, 0x09);
snd_soc_update_bits(codec,
MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x01, 0x01);
snd_soc_update_bits(codec,
MSM89XX_CDC_CORE_COMP0_B1_CTL,
1 << interp_n, 1 << interp_n);
if (dig_cdc->comp_enabled[MSM89XX_RX1]) {
snd_soc_update_bits(codec,
MSM89XX_CDC_CORE_COMP0_B1_CTL,
0x02, 0x02);
}
if (dig_cdc->comp_enabled[MSM89XX_RX2]) {
snd_soc_update_bits(codec,
MSM89XX_CDC_CORE_COMP0_B1_CTL,
0x01, 0x01);
}
snd_soc_update_bits(codec,
MSM89XX_CDC_CORE_COMP0_B3_CTL, 0xFF, 0x01);
snd_soc_update_bits(codec,