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powerpc/8xx: Remove loading of r10 at end of FixupDAR

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Since commit 2321f33790, r10 is not used anymore
after FixupDAR. There is therefore no need to set it up with the value of DAR.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
LEROY Christophe 2014-08-29 11:14:37 +02:00 • committed by Scott Wood
parent 92625d491e
commit 3e43640346
1 changed files with 3 additions and 4 deletions
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7
arch/powerpc/kernel/head_8xx.S
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@ -498,7 +498,7 @@ DataTLBError:
mfspr r10, SPRN_DAR mfspr r10, SPRN_DAR
cmpwi cr0, r10, 0x00f0 cmpwi cr0, r10, 0x00f0
beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR */ DARFixed:/* Return from dcbx instruction bug workaround */
#ifdef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0) lwz r3, 8(r0)
#endif #endif
@ -527,7 +527,7 @@ DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR
/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
* by decoding the registers used by the dcbx instruction and adding them. * by decoding the registers used by the dcbx instruction and adding them.
* DAR is set to the calculated address and r10 also holds the EA on exit. * DAR is set to the calculated address.
*/ */
/* define if you don't want to use self modifying code */ /* define if you don't want to use self modifying code */
#define NO_SELF_MODIFYING_CODE #define NO_SELF_MODIFYING_CODE
@ -567,8 +567,7 @@ FixupDAR:/* Entry point for dcbx workaround. */
beq+ 142f beq+ 142f
cmpwi cr0, r10, 1964 /* Is icbi? */ cmpwi cr0, r10, 1964 /* Is icbi? */
beq+ 142f beq+ 142f
141: mfspr r10, SPRN_DAR /* r10 must hold DAR at exit */ 141: b DARFixed /* Nope, go back to normal TLB processing */
b DARFixed /* Nope, go back to normal TLB processing */
144: mfspr r10, SPRN_DSISR 144: mfspr r10, SPRN_DSISR
rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */