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clk: tegra: move from a lock bit idx to a lock mask

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PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Peter De Schrijver 2013-04-03 17:40:40 +03:00 • committed by Stephen Warren
parent 0b6525acd1
commit 3e72771e21
4 changed files with 25 additions and 25 deletions
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6
drivers/clk/tegra/clk-pll.c
View file

@ -119,7 +119,7 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
{ {
int i; int i;
u32 val, lock_bit; u32 val, lock_mask;
void __iomem *lock_addr; void __iomem *lock_addr;
if (!(pll->flags & TEGRA_PLL_USE_LOCK)) { if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
@ -133,11 +133,11 @@ static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
else else
lock_addr += pll->params->base_reg; lock_addr += pll->params->base_reg;
lock_bit = BIT(pll->params->lock_bit_idx); lock_mask = pll->params->lock_mask;
for (i = 0; i < pll->params->lock_delay; i++) { for (i = 0; i < pll->params->lock_delay; i++) {
val = readl_relaxed(lock_addr); val = readl_relaxed(lock_addr);
if (val & lock_bit) { if ((val & lock_mask) == lock_mask) {
udelay(PLL_POST_LOCK_DELAY); udelay(PLL_POST_LOCK_DELAY);
return 0; return 0;
} }

20
drivers/clk/tegra/clk-tegra20.c
View file

@ -86,8 +86,8 @@
#define PLLE_BASE 0xe8 #define PLLE_BASE 0xe8
#define PLLE_MISC 0xec #define PLLE_MISC 0xec
#define PLL_BASE_LOCK 27 #define PLL_BASE_LOCK BIT(27)
#define PLLE_MISC_LOCK 11 #define PLLE_MISC_LOCK BIT(11)
#define PLL_MISC_LOCK_ENABLE 18 #define PLL_MISC_LOCK_ENABLE 18
#define PLLDU_MISC_LOCK_ENABLE 22 #define PLLDU_MISC_LOCK_ENABLE 22
@ -380,7 +380,7 @@ static struct tegra_clk_pll_params pll_c_params = {
.vco_max = 1400000000, .vco_max = 1400000000,
.base_reg = PLLC_BASE, .base_reg = PLLC_BASE,
.misc_reg = PLLC_MISC, .misc_reg = PLLC_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
}; };
@ -394,7 +394,7 @@ static struct tegra_clk_pll_params pll_m_params = {
.vco_max = 1200000000, .vco_max = 1200000000,
.base_reg = PLLM_BASE, .base_reg = PLLM_BASE,
.misc_reg = PLLM_MISC, .misc_reg = PLLM_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
}; };
@ -408,7 +408,7 @@ static struct tegra_clk_pll_params pll_p_params = {
.vco_max = 1400000000, .vco_max = 1400000000,
.base_reg = PLLP_BASE, .base_reg = PLLP_BASE,
.misc_reg = PLLP_MISC, .misc_reg = PLLP_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
}; };
@ -422,7 +422,7 @@ static struct tegra_clk_pll_params pll_a_params = {
.vco_max = 1400000000, .vco_max = 1400000000,
.base_reg = PLLA_BASE, .base_reg = PLLA_BASE,
.misc_reg = PLLA_MISC, .misc_reg = PLLA_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
}; };
@ -436,7 +436,7 @@ static struct tegra_clk_pll_params pll_d_params = {
.vco_max = 1000000000, .vco_max = 1000000000,
.base_reg = PLLD_BASE, .base_reg = PLLD_BASE,
.misc_reg = PLLD_MISC, .misc_reg = PLLD_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000, .lock_delay = 1000,
}; };
@ -456,7 +456,7 @@ static struct tegra_clk_pll_params pll_u_params = {
.vco_max = 960000000, .vco_max = 960000000,
.base_reg = PLLU_BASE, .base_reg = PLLU_BASE,
.misc_reg = PLLU_MISC, .misc_reg = PLLU_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000, .lock_delay = 1000,
.pdiv_tohw = pllu_p, .pdiv_tohw = pllu_p,
@ -471,7 +471,7 @@ static struct tegra_clk_pll_params pll_x_params = {
.vco_max = 1200000000, .vco_max = 1200000000,
.base_reg = PLLX_BASE, .base_reg = PLLX_BASE,
.misc_reg = PLLX_MISC, .misc_reg = PLLX_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
}; };
@ -485,7 +485,7 @@ static struct tegra_clk_pll_params pll_e_params = {
.vco_max = 0, .vco_max = 0,
.base_reg = PLLE_BASE, .base_reg = PLLE_BASE,
.misc_reg = PLLE_MISC, .misc_reg = PLLE_MISC,
.lock_bit_idx = PLLE_MISC_LOCK, .lock_mask = PLLE_MISC_LOCK,
.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
.lock_delay = 0, .lock_delay = 0,
}; };

22
drivers/clk/tegra/clk-tegra30.c
View file

@ -116,8 +116,8 @@
#define PLLDU_MISC_LOCK_ENABLE 22 #define PLLDU_MISC_LOCK_ENABLE 22
#define PLLE_MISC_LOCK_ENABLE 9 #define PLLE_MISC_LOCK_ENABLE 9
#define PLL_BASE_LOCK 27 #define PLL_BASE_LOCK BIT(27)
#define PLLE_MISC_LOCK 11 #define PLLE_MISC_LOCK BIT(11)
#define PLLE_AUX 0x48c #define PLLE_AUX 0x48c
#define PLLC_OUT 0x84 #define PLLC_OUT 0x84
@ -559,7 +559,7 @@ static struct tegra_clk_pll_params pll_c_params = {
.vco_max = 1400000000, .vco_max = 1400000000,
.base_reg = PLLC_BASE, .base_reg = PLLC_BASE,
.misc_reg = PLLC_MISC, .misc_reg = PLLC_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
}; };
@ -573,7 +573,7 @@ static struct tegra_clk_pll_params pll_m_params = {
.vco_max = 1200000000, .vco_max = 1200000000,
.base_reg = PLLM_BASE, .base_reg = PLLM_BASE,
.misc_reg = PLLM_MISC, .misc_reg = PLLM_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
}; };
@ -587,7 +587,7 @@ static struct tegra_clk_pll_params pll_p_params = {
.vco_max = 1400000000, .vco_max = 1400000000,
.base_reg = PLLP_BASE, .base_reg = PLLP_BASE,
.misc_reg = PLLP_MISC, .misc_reg = PLLP_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
}; };
@ -601,7 +601,7 @@ static struct tegra_clk_pll_params pll_a_params = {
.vco_max = 1400000000, .vco_max = 1400000000,
.base_reg = PLLA_BASE, .base_reg = PLLA_BASE,
.misc_reg = PLLA_MISC, .misc_reg = PLLA_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
}; };
@ -615,7 +615,7 @@ static struct tegra_clk_pll_params pll_d_params = {
.vco_max = 1000000000, .vco_max = 1000000000,
.base_reg = PLLD_BASE, .base_reg = PLLD_BASE,
.misc_reg = PLLD_MISC, .misc_reg = PLLD_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000, .lock_delay = 1000,
}; };
@ -629,7 +629,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
.vco_max = 1000000000, .vco_max = 1000000000,
.base_reg = PLLD2_BASE, .base_reg = PLLD2_BASE,
.misc_reg = PLLD2_MISC, .misc_reg = PLLD2_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000, .lock_delay = 1000,
}; };
@ -643,7 +643,7 @@ static struct tegra_clk_pll_params pll_u_params = {
.vco_max = 960000000, .vco_max = 960000000,
.base_reg = PLLU_BASE, .base_reg = PLLU_BASE,
.misc_reg = PLLU_MISC, .misc_reg = PLLU_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000, .lock_delay = 1000,
.pdiv_tohw = pllu_p, .pdiv_tohw = pllu_p,
@ -658,7 +658,7 @@ static struct tegra_clk_pll_params pll_x_params = {
.vco_max = 1700000000, .vco_max = 1700000000,
.base_reg = PLLX_BASE, .base_reg = PLLX_BASE,
.misc_reg = PLLX_MISC, .misc_reg = PLLX_MISC,
.lock_bit_idx = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
}; };
@ -672,7 +672,7 @@ static struct tegra_clk_pll_params pll_e_params = {
.vco_max = 2400000000U, .vco_max = 2400000000U,
.base_reg = PLLE_BASE, .base_reg = PLLE_BASE,
.misc_reg = PLLE_MISC, .misc_reg = PLLE_MISC,
.lock_bit_idx = PLLE_MISC_LOCK, .lock_mask = PLLE_MISC_LOCK,
.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
}; };

2
drivers/clk/tegra/clk.h
View file

@ -154,7 +154,7 @@ struct tegra_clk_pll_params {
u32 base_reg; u32 base_reg;
u32 misc_reg; u32 misc_reg;
u32 lock_reg; u32 lock_reg;
u32 lock_bit_idx; u32 lock_mask;
u32 lock_enable_bit_idx; u32 lock_enable_bit_idx;
int lock_delay; int lock_delay;
int max_p; int max_p;