clk: msm: clock-gcc-cobalt: Remove support for gcc_bimc_hmss_axi_clk

The gcc_bimc_hmss_axi_clk will be configured outside of HLOS.
The linux clock driver does not need to manually enable it.

CRs-Fixed: 1012646
Change-Id: Ib0b848fb410f4bf266b09cefed0e8bce7292d2ec
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
This commit is contained in:
Deepak Katragadda 2016-06-30 17:11:49 -07:00
parent ea475748ca
commit 3ec715adbe
3 changed files with 1 additions and 17 deletions

View file

@ -1698,19 +1698,6 @@ static struct branch_clk gcc_gpu_iref_clk = {
},
};
static struct local_vote_clk gcc_bimc_hmss_axi_clk = {
.cbcr_reg = GCC_BIMC_HMSS_AXI_CBCR,
.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(22),
.base = &virt_base,
.c = {
.dbg_name = "gcc_bimc_hmss_axi_clk",
.always_on = true,
.ops = &clk_ops_vote,
CLK_INIT(gcc_bimc_hmss_axi_clk.c),
},
};
static struct local_vote_clk gcc_hmss_ahb_clk = {
.cbcr_reg = GCC_HMSS_AHB_CBCR,
.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE,
@ -2439,7 +2426,7 @@ static struct mux_clk gcc_debug_mux = {
{ &ce1_clk.c, 0x0097 },
{ &gcc_ce1_axi_m_clk.c, 0x0098 },
{ &gcc_ce1_ahb_m_clk.c, 0x0099 },
{ &gcc_bimc_hmss_axi_clk.c, 0x00bb },
{ &measure_only_bimc_hmss_axi_clk.c, 0x00bb },
{ &gcc_bimc_gfx_clk.c, 0x00ac },
{ &gcc_hmss_ahb_clk.c, 0x00ba },
{ &gcc_hmss_rbcpr_clk.c, 0x00bc },
@ -2661,7 +2648,6 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = {
CLK_LIST(gcc_gpu_cfg_ahb_clk),
CLK_LIST(gcc_gpu_snoc_dvm_gfx_clk),
CLK_LIST(gcc_gpu_iref_clk),
CLK_LIST(gcc_bimc_hmss_axi_clk),
CLK_LIST(gcc_hmss_ahb_clk),
CLK_LIST(gcc_hmss_dvm_bus_clk),
CLK_LIST(gcc_hmss_rbcpr_clk),

View file

@ -197,7 +197,6 @@
#define clk_gcc_gpu_snoc_dvm_gfx_clk 0xc9147451
#define clk_gcc_gpu_bimc_gfx_clk 0x3909459b
#define clk_gcc_gpu_bimc_gfx_src_clk 0x377cb748
#define clk_gcc_bimc_hmss_axi_clk 0x84653931
#define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57
#define clk_gcc_gpu_iref_clk 0xfd82abad
#define clk_gcc_hmss_ahb_clk 0x62818713

View file

@ -171,7 +171,6 @@
#define GCC_GPU_CFG_AHB_CBCR 0x71004
#define GCC_GPU_SNOC_DVM_GFX_CBCR 0x71018
#define GCC_GPU_IREF_EN 0x88010
#define GCC_BIMC_HMSS_AXI_CBCR 0x48004
#define GCC_HMSS_AHB_CBCR 0x48000
#define GCC_HMSS_DVM_BUS_CBCR 0x4808C
#define GCC_HMSS_RBCPR_CBCR 0x48008