evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

ARM: dts: msm: use VDD_GFX CPR regulator for GPU clock on msmcobalt

Browse source 
Switch the GPU clock to use the gfx_vreg CPR regulator device for
vdd_gpucc-supply.  This ensures that the VDD_GFX operating
voltage ends up as low as possible.  Also switch the gdsc_gpu_gx
GDSC regulator to use the gfx_vreg regulator for parent-supply.

Add and use a stub regulator for the GFX clock vdd_gpucc-supply
on sim and rumi targets since gfx_vreg may not be usable on these
targets for certain hardware and bootloader combinations.

Change-Id: Ic6536cb90da928ea82d4575922bdf3cb153e5a27
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
This commit is contained in:
David Collins 2016-03-29 15:46:01 -07:00 • committed by Bryan Huntsman
parent deb0522330
commit 3ee8625f41
3 changed files with 45 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi
View file

@ -58,6 +58,24 @@
status = "ok";
};
/ {
gfx_stub_vreg: regulator-gfx-stub {
compatible = "qcom,stub-regulator";
regulator-name = "gfx_stub_corner";
qcom,hpm-min-load = <100000>;
regulator-min-microvolt = <1>;
regulator-max-microvolt = <6>;
};
};
&clock_gfx {
vdd_gpucc-supply = <&gfx_stub_vreg>;
};
&gdsc_gpu_gx {
parent-supply = <&gfx_stub_vreg>;
};
&clock_cpu {
qcom,cc-factor = <10>;
qcom,osm-clk-rate = <2000000>;

18
arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi
View file

@ -33,3 +33,21 @@
status = "ok";
};
/ {
gfx_stub_vreg: regulator-gfx-stub {
compatible = "qcom,stub-regulator";
regulator-name = "gfx_stub_corner";
qcom,hpm-min-load = <100000>;
regulator-min-microvolt = <1>;
regulator-max-microvolt = <6>;
};
};
&clock_gfx {
vdd_gpucc-supply = <&gfx_stub_vreg>;
};
&gdsc_gpu_gx {
parent-supply = <&gfx_stub_vreg>;
};

18
arch/arm/boot/dts/qcom/msmcobalt.dtsi
View file

@ -613,18 +613,18 @@
compatible = "qcom,gfxcc-cobalt";
reg = <0x5065000 0x9000>;
reg-names = "cc_base";
vdd_gpucc-supply = <&pm8005_s1>;
vdd_gpucc-supply = <&gfx_vreg>;
vdd_mx-supply = <&pmcobalt_s9_level>;
vdd_gpu_mx-supply = <&pmcobalt_s9_level>;
qcom,gfx3d_clk_src-opp-store-vcorner = <&msm_gpu>;
qcom,gfxfreq-speedbin0 =
< 0 0 0 >,
< 171000000 520000 RPM_SMD_REGULATOR_LEVEL_SVS >,
< 251000000 570000 RPM_SMD_REGULATOR_LEVEL_SVS >,
< 332000000 630000 RPM_SMD_REGULATOR_LEVEL_SVS >,
< 403000000 680000 RPM_SMD_REGULATOR_LEVEL_SVS >,
< 504000000 745000 RPM_SMD_REGULATOR_LEVEL_NOM >,
< 650000000 855000 RPM_SMD_REGULATOR_LEVEL_TURBO >;
< 0 0 0 >,
< 171000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >,
< 251000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >,
< 332000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >,
< 403000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >,
< 504000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >,
< 650000000 6 RPM_SMD_REGULATOR_LEVEL_TURBO >;
qcom,gfxfreq-mx-speedbin0 =
< 0 0 >,
< 171000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
@ -2146,7 +2146,7 @@
<&clock_gfx clk_gpucc_gfx3d_clk>,
<&clock_gfx clk_gfx3d_clk_src>;
qcom,force-enable-root-clk;
parent-supply = <&pm8005_s1>;
parent-supply = <&gfx_vreg>;
status = "ok";
};