scsi: ufs-qcom: implement pre and post notification for clock scaling
QUniPro controller requires additional configuration before and after clock scaling, this change adds the support for it. Change-Id: I0add27ff3ab54f72b8b79e1e554541c2e492a4c8 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This commit is contained in:
Subhash Jadavani
David Keitel
parent
1811e9b0bb
commit
413d97dd2a
2 changed files with 123 additions and 9 deletions
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@ -63,6 +63,8 @@ static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
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static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
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static int ufs_qcom_update_sec_cfg(struct ufs_hba *hba, bool restore_sec_cfg);
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static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
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static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
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u32 clk_cycles);
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static void ufs_qcom_dump_regs(struct ufs_hba *hba, int offset, int len,
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char *prefix)
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@ -546,6 +548,16 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, bool status)
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/* make sure RX LineCfg is enabled before link startup */
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err = ufs_qcom_phy_ctrl_rx_linecfg(phy, true);
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if (err)
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goto out;
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if (ufs_qcom_cap_qunipro(host))
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/*
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* set unipro core clock cycles to 150 & clear clock
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* divider
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*/
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err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
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150);
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break;
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case POST_CHANGE:
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ufs_qcom_link_startup_post_change(hba);
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@ -1386,22 +1398,118 @@ static void ufs_qcom_exit(struct ufs_hba *hba)
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phy_power_off(host->generic_phy);
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}
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static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
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u32 clk_cycles)
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{
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int err;
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u32 core_clk_ctrl_reg;
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int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
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bool scale_up, bool status)
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if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
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return -EINVAL;
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err = ufshcd_dme_get(hba,
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UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
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&core_clk_ctrl_reg);
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if (err)
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goto out;
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core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
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core_clk_ctrl_reg |= clk_cycles;
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/* Clear CORE_CLK_DIV_EN */
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core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
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err = ufshcd_dme_set(hba,
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UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
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core_clk_ctrl_reg);
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out:
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return err;
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}
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static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
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{
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/* nothing to do as of now */
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return 0;
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}
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static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
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{
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struct ufs_qcom_host *host = hba->priv;
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if (!ufs_qcom_cap_qunipro(host))
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return 0;
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/* set unipro core clock cycles to 150 and clear clock divider */
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return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
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}
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static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
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{
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struct ufs_qcom_host *host = hba->priv;
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int err;
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u32 core_clk_ctrl_reg;
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if (!ufs_qcom_cap_qunipro(host))
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return 0;
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err = ufshcd_dme_get(hba,
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UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
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&core_clk_ctrl_reg);
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/* make sure CORE_CLK_DIV_EN is cleared */
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if (!err &&
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(core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
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core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
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err = ufshcd_dme_set(hba,
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UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
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core_clk_ctrl_reg);
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}
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return err;
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}
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static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
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{
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struct ufs_qcom_host *host = hba->priv;
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if (!ufs_qcom_cap_qunipro(host))
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return 0;
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/* set unipro core clock cycles to 75 and clear clock divider */
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return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
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}
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static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
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bool scale_up, bool status)
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{
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struct ufs_qcom_host *host = hba->priv;
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struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
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int err = 0;
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if (!dev_req_params)
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return 0;
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if (status == PRE_CHANGE) {
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if (scale_up)
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err = ufs_qcom_clk_scale_up_pre_change(hba);
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else
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err = ufs_qcom_clk_scale_down_pre_change(hba);
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} else {
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if (scale_up)
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err = ufs_qcom_clk_scale_up_post_change(hba);
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else
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err = ufs_qcom_clk_scale_down_post_change(hba);
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ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
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dev_req_params->pwr_rx,
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dev_req_params->hs_rate, false);
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ufs_qcom_update_bus_bw_vote(host);
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if (err || !dev_req_params)
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goto out;
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return 0;
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ufs_qcom_cfg_timers(hba,
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dev_req_params->gear_rx,
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dev_req_params->pwr_rx,
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dev_req_params->hs_rate,
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false);
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ufs_qcom_update_bus_bw_vote(host);
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}
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out:
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return err;
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}
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/*
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@ -141,6 +141,12 @@ struct ufs_qcom_phy_vreg {
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(UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_ICE_REGS_EN | \
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UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
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/* QUniPro Vendor specific attributes */
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#define DME_VS_CORE_CLK_CTRL 0xD002
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/* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
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#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8)
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#define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF
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static inline void
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ufs_qcom_get_controller_revision(struct ufs_hba *hba,
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u8 *major, u16 *minor, u16 *step)
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