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cirrusfb: fix threshold register mask for Laguna chips

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Fix threshold register mask for Laguna chips otherwise some 8bpp modes are
garbled after selecting a 24bpp mode.

Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Krzysztof Helt 2009-03-31 15:25:17 -07:00 • committed by Linus Torvalds
parent df3aafd57d
commit 4242a23c9e
1 changed files with 1 additions and 1 deletions
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2
drivers/video/cirrusfb.c
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@ -875,7 +875,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
threshold = fb_readw(cinfo->laguna_mmio + 0xea); threshold = fb_readw(cinfo->laguna_mmio + 0xea);
control &= ~0x6800; control &= ~0x6800;
format = 0; format = 0;
threshold &= 0xffe0 & 0x3fbf; threshold &= 0xffc0 & 0x3fbf;
} }
if (nom) { if (nom) {
tmp = den << 1; tmp = den << 1;