staging: gma500: Moorestown does its setup differently
Grovel the firmware via the Moorestown interfaces and read the other bits off the fuses. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Alan Cox
Greg Kroah-Hartman
parent
e68e8c711b
commit
427096db84
1 changed files with 213 additions and 28 deletions
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@ -320,6 +320,210 @@ static void psb_do_takedown(struct drm_device *dev)
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}
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void mrst_get_fuse_settings(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
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uint32_t fuse_value = 0;
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uint32_t fuse_value_tmp = 0;
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#define FB_REG06 0xD0810600
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#define FB_MIPI_DISABLE (1 << 11)
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#define FB_REG09 0xD0810900
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#define FB_REG09 0xD0810900
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#define FB_SKU_MASK 0x7000
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#define FB_SKU_SHIFT 12
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#define FB_SKU_100 0
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#define FB_SKU_100L 1
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#define FB_SKU_83 2
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pci_write_config_dword(pci_root, 0xD0, FB_REG06);
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pci_read_config_dword(pci_root, 0xD4, &fuse_value);
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dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
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DRM_INFO("internal display is %s\n",
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dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
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/*prevent Runtime suspend at start*/
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if (dev_priv->iLVDS_enable) {
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dev_priv->is_lvds_on = true;
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dev_priv->is_mipi_on = false;
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}
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else {
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dev_priv->is_mipi_on = true;
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dev_priv->is_lvds_on = false;
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}
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dev_priv->video_device_fuse = fuse_value;
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pci_write_config_dword(pci_root, 0xD0, FB_REG09);
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pci_read_config_dword(pci_root, 0xD4, &fuse_value);
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DRM_INFO("SKU values is 0x%x. \n", fuse_value);
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fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
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dev_priv->fuse_reg_value = fuse_value;
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switch (fuse_value_tmp) {
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case FB_SKU_100:
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dev_priv->core_freq = 200;
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break;
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case FB_SKU_100L:
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dev_priv->core_freq = 100;
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break;
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case FB_SKU_83:
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dev_priv->core_freq = 166;
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break;
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default:
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DRM_ERROR("Invalid SKU values, SKU value = 0x%08x\n", fuse_value_tmp);
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dev_priv->core_freq = 0;
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}
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DRM_INFO("LNC core clk is %dMHz.\n", dev_priv->core_freq);
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pci_dev_put(pci_root);
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}
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void mid_get_pci_revID (struct drm_psb_private *dev_priv)
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{
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uint32_t platform_rev_id = 0;
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struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
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/*get the revison ID, B0:D2:F0;0x08 */
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pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
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dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
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pci_dev_put(pci_gfx_root);
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PSB_DEBUG_ENTRY("platform_rev_id is %x\n", dev_priv->platform_rev_id);
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}
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void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
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{
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struct mrst_vbt *vbt = &dev_priv->vbt_data;
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u32 platform_config_address;
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u16 new_size;
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u8 *vbt_virtual;
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u8 bpi;
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u8 number_desc = 0;
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struct mrst_timing_info *dp_ti = &dev_priv->gct_data.DTD;
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struct gct_r10_timing_info ti;
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void *pGCT;
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struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
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/*get the address of the platform config vbt, B0:D2:F0;0xFC */
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pci_read_config_dword(pci_gfx_root, 0xFC, &platform_config_address);
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pci_dev_put(pci_gfx_root);
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DRM_INFO("drm platform config address is %x\n",
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platform_config_address);
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/* check for platform config address == 0. */
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/* this means fw doesn't support vbt */
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if (platform_config_address == 0) {
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vbt->size = 0;
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return;
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}
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/* get the virtual address of the vbt */
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vbt_virtual = ioremap(platform_config_address, sizeof(*vbt));
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memcpy(vbt, vbt_virtual, sizeof(*vbt));
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iounmap(vbt_virtual); /* Free virtual address space */
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printk(KERN_ALERT "GCT revision is %x\n", vbt->revision);
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switch (vbt->revision) {
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case 0:
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vbt->mrst_gct = NULL;
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vbt->mrst_gct = \
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ioremap(platform_config_address + sizeof(*vbt) - 4,
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vbt->size - sizeof(*vbt) + 4);
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pGCT = vbt->mrst_gct;
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bpi = ((struct mrst_gct_v1 *)pGCT)->PD.BootPanelIndex;
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dev_priv->gct_data.bpi = bpi;
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dev_priv->gct_data.pt =
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((struct mrst_gct_v1 *)pGCT)->PD.PanelType;
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memcpy(&dev_priv->gct_data.DTD,
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&((struct mrst_gct_v1 *)pGCT)->panel[bpi].DTD,
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sizeof(struct mrst_timing_info));
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dev_priv->gct_data.Panel_Port_Control =
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((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
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dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
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((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
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break;
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case 1:
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vbt->mrst_gct = NULL;
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vbt->mrst_gct = \
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ioremap(platform_config_address + sizeof(*vbt) - 4,
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vbt->size - sizeof(*vbt) + 4);
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pGCT = vbt->mrst_gct;
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bpi = ((struct mrst_gct_v2 *)pGCT)->PD.BootPanelIndex;
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dev_priv->gct_data.bpi = bpi;
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dev_priv->gct_data.pt =
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((struct mrst_gct_v2 *)pGCT)->PD.PanelType;
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memcpy(&dev_priv->gct_data.DTD,
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&((struct mrst_gct_v2 *)pGCT)->panel[bpi].DTD,
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sizeof(struct mrst_timing_info));
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dev_priv->gct_data.Panel_Port_Control =
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((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
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dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
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((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
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break;
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case 0x10:
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/*header definition changed from rev 01 (v2) to rev 10h. */
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/*so, some values have changed location*/
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new_size = vbt->checksum; /*checksum contains lo size byte*/
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/*LSB of mrst_gct contains hi size byte*/
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new_size |= ((0xff & (unsigned int)vbt->mrst_gct)) << 8;
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vbt->checksum = vbt->size; /*size contains the checksum*/
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if (new_size > 0xff)
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vbt->size = 0xff; /*restrict size to 255*/
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else
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vbt->size = new_size;
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/* number of descriptors defined in the GCT */
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number_desc = ((0xff00 & (unsigned int)vbt->mrst_gct)) >> 8;
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bpi = ((0xff0000 & (unsigned int)vbt->mrst_gct)) >> 16;
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vbt->mrst_gct = NULL;
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vbt->mrst_gct = \
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ioremap(platform_config_address + GCT_R10_HEADER_SIZE,
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GCT_R10_DISPLAY_DESC_SIZE * number_desc);
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pGCT = vbt->mrst_gct;
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pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
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dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
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/*copy the GCT display timings into a temp structure*/
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memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
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/*now copy the temp struct into the dev_priv->gct_data*/
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dp_ti->pixel_clock = ti.pixel_clock;
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dp_ti->hactive_hi = ti.hactive_hi;
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dp_ti->hactive_lo = ti.hactive_lo;
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dp_ti->hblank_hi = ti.hblank_hi;
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dp_ti->hblank_lo = ti.hblank_lo;
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dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
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dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
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dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
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dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
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dp_ti->vactive_hi = ti.vactive_hi;
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dp_ti->vactive_lo = ti.vactive_lo;
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dp_ti->vblank_hi = ti.vblank_hi;
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dp_ti->vblank_lo = ti.vblank_lo;
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dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
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dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
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dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
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dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
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/*mov the MIPI_Display_Descriptor data from GCT to dev priv*/
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dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
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*((u8 *)pGCT + 0x0d);
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dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
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(*((u8 *)pGCT + 0x0e)) << 8;
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break;
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default:
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printk(KERN_ERR "Unknown revision of GCT!\n");
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vbt->size = 0;
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}
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}
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static void psb_get_core_freq(struct drm_device *dev)
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{
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uint32_t clock;
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@ -358,31 +562,6 @@ static void psb_get_core_freq(struct drm_device *dev)
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}
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}
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#define FB_REG06 0xD0810600
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#define FB_TOPAZ_DISABLE BIT0
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#define FB_MIPI_DISABLE BIT11
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#define FB_REG09 0xD0810900
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#define FB_SKU_MASK (BIT12|BIT13|BIT14)
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#define FB_SKU_SHIFT 12
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#define FB_SKU_100 0
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#define FB_SKU_100L 1
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#define FB_SKU_83 2
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bool mid_get_pci_revID(struct drm_psb_private *dev_priv)
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{
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uint32_t platform_rev_id = 0;
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struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
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/*get the revison ID, B0:D2:F0;0x08 */
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pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
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dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
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pci_dev_put(pci_gfx_root);
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PSB_DEBUG_ENTRY("platform_rev_id is %x\n",
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dev_priv->platform_rev_id);
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return true;
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}
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static int psb_do_init(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv =
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@ -634,9 +813,15 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
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if (!dev_priv->sgx_reg)
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goto out_err;
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psb_get_core_freq(dev);
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psb_intel_opregion_init(dev);
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psb_intel_init_bios(dev);
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if (IS_MRST(dev)) {
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mrst_get_fuse_settings(dev);
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mrst_get_vbt_data(dev_priv);
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mid_get_pci_revID(dev_priv);
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} else {
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psb_get_core_freq(dev);
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psb_intel_opregion_init(dev);
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psb_intel_init_bios(dev);
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}
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PSB_DEBUG_INIT("Init TTM fence and BO driver\n");
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