mmc: sdhci-msm: remove support for Qualcomm chipsets
The upstream sdhci-msm driver has diverged, removing the upstream version to recreate our internal tree from msm-3.18 to msm-4.4. Change-Id: I952b08667177272fdc30fea79b445f96a3fc2182 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This commit is contained in:
parent
97b7bbc9ea
commit
42b23b9bcd
3 changed files with 6 additions and 683 deletions
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@ -404,18 +404,13 @@ config MMC_ATMELMCI
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If unsure, say N.
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config MMC_SDHCI_MSM
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tristate "Qualcomm SDHCI Controller Support"
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depends on ARCH_QCOM || ARCH_MSM || (ARM && COMPILE_TEST)
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depends on MMC_SDHCI_PLTFM
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config MMC_MSM
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tristate "Qualcomm SDCC Controller Support"
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depends on MMC && (ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50)
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help
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This selects the Secure Digital Host Controller Interface (SDHCI)
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support present in Qualcomm SOCs. The controller supports
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SD/MMC/SDIO devices.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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This provides support for the SD/MMC cell found in the
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MSM and QSD SOCs from Qualcomm. The controller also has
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support for SDIO devices.
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config MMC_MXC
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tristate "Freescale i.MX21/27/31 or MPC512x Multimedia Card support"
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@ -73,7 +73,6 @@ obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
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obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
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obj-$(CONFIG_MMC_SDHCI_BCM2835) += sdhci-bcm2835.o
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obj-$(CONFIG_MMC_SDHCI_IPROC) += sdhci-iproc.o
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obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
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obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o
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ifeq ($(CONFIG_CB710_DEBUG),y)
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@ -1,671 +0,0 @@
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/*
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* drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
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*
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* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/delay.h>
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#include <linux/mmc/mmc.h>
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#include <linux/slab.h>
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#include "sdhci-pltfm.h"
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#define CORE_MCI_VERSION 0x50
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#define CORE_VERSION_MAJOR_SHIFT 28
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#define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
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#define CORE_VERSION_MINOR_MASK 0xff
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#define CORE_HC_MODE 0x78
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#define HC_MODE_EN 0x1
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#define CORE_POWER 0x0
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#define CORE_SW_RST BIT(7)
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#define CORE_HC_SELECT_IN_EN (1 << 18)
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#define CORE_HC_SELECT_IN_MASK (7 << 19)
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#define MAX_PHASES 16
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#define CORE_DLL_LOCK BIT(7)
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#define CORE_DLL_EN BIT(16)
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#define CORE_CDR_EN BIT(17)
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#define CORE_CK_OUT_EN BIT(18)
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#define CORE_CDR_EXT_EN BIT(19)
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#define CORE_DLL_PDN BIT(29)
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#define CORE_DLL_RST BIT(30)
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#define CORE_DLL_CONFIG 0x100
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#define CORE_DLL_STATUS 0x108
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#define CORE_VENDOR_SPEC 0x10c
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#define CORE_CLK_PWRSAVE BIT(1)
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#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
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#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
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#define CORE_8_BIT_SUPPORT (1 << 18)
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#define CORE_3_0V_SUPPORT (1 << 25)
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#define CDR_SELEXT_SHIFT 20
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#define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
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#define CMUX_SHIFT_PHASE_SHIFT 24
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#define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
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struct sdhci_msm_host {
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struct platform_device *pdev;
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void __iomem *core_mem; /* MSM SDCC mapped address */
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struct clk *clk; /* main SD/MMC bus clock */
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struct clk *pclk; /* SDHC peripheral bus clock */
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struct clk *bus_clk; /* SDHC bus voter clock */
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struct mmc_host *mmc;
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struct sdhci_pltfm_data sdhci_msm_pdata;
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struct regulator *vdd;
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struct regulator *vdd_io;
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};
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/* Platform specific tuning */
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static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
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{
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u32 wait_cnt = 50;
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u8 ck_out_en;
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struct mmc_host *mmc = host->mmc;
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/* Poll for CK_OUT_EN bit. max. poll time = 50us */
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ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
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CORE_CK_OUT_EN);
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while (ck_out_en != poll) {
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if (--wait_cnt == 0) {
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dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
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mmc_hostname(mmc), poll);
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return -ETIMEDOUT;
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}
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udelay(1);
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ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
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CORE_CK_OUT_EN);
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}
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return 0;
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}
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static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
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{
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int rc;
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static const u8 grey_coded_phase_table[] = {
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0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
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0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
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};
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unsigned long flags;
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u32 config;
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struct mmc_host *mmc = host->mmc;
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spin_lock_irqsave(&host->lock, flags);
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config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
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config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
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config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
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writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
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/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
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rc = msm_dll_poll_ck_out_en(host, 0);
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if (rc)
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goto err_out;
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/*
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* Write the selected DLL clock output phase (0 ... 15)
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* to CDR_SELEXT bit field of DLL_CONFIG register.
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*/
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config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
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config &= ~CDR_SELEXT_MASK;
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config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
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writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
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/* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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| CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
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/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
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rc = msm_dll_poll_ck_out_en(host, 1);
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if (rc)
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goto err_out;
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config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
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config |= CORE_CDR_EN;
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config &= ~CORE_CDR_EXT_EN;
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writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
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goto out;
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err_out:
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dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
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mmc_hostname(mmc), phase);
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out:
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spin_unlock_irqrestore(&host->lock, flags);
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return rc;
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}
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/*
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* Find out the greatest range of consecuitive selected
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* DLL clock output phases that can be used as sampling
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* setting for SD3.0 UHS-I card read operation (in SDR104
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* timing mode) or for eMMC4.5 card read operation (in HS200
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* timing mode).
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* Select the 3/4 of the range and configure the DLL with the
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* selected DLL clock output phase.
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*/
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static int msm_find_most_appropriate_phase(struct sdhci_host *host,
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u8 *phase_table, u8 total_phases)
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{
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int ret;
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u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
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u8 phases_per_row[MAX_PHASES] = { 0 };
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int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
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int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
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bool phase_0_found = false, phase_15_found = false;
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struct mmc_host *mmc = host->mmc;
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if (!total_phases || (total_phases > MAX_PHASES)) {
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dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
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mmc_hostname(mmc), total_phases);
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return -EINVAL;
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}
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for (cnt = 0; cnt < total_phases; cnt++) {
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ranges[row_index][col_index] = phase_table[cnt];
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phases_per_row[row_index] += 1;
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col_index++;
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if ((cnt + 1) == total_phases) {
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continue;
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/* check if next phase in phase_table is consecutive or not */
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} else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
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row_index++;
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col_index = 0;
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}
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}
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if (row_index >= MAX_PHASES)
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return -EINVAL;
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/* Check if phase-0 is present in first valid window? */
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if (!ranges[0][0]) {
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phase_0_found = true;
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phase_0_raw_index = 0;
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/* Check if cycle exist between 2 valid windows */
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for (cnt = 1; cnt <= row_index; cnt++) {
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if (phases_per_row[cnt]) {
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for (i = 0; i < phases_per_row[cnt]; i++) {
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if (ranges[cnt][i] == 15) {
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phase_15_found = true;
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phase_15_raw_index = cnt;
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break;
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}
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}
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}
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}
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}
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/* If 2 valid windows form cycle then merge them as single window */
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if (phase_0_found && phase_15_found) {
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/* number of phases in raw where phase 0 is present */
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u8 phases_0 = phases_per_row[phase_0_raw_index];
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/* number of phases in raw where phase 15 is present */
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u8 phases_15 = phases_per_row[phase_15_raw_index];
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if (phases_0 + phases_15 >= MAX_PHASES)
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/*
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* If there are more than 1 phase windows then total
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* number of phases in both the windows should not be
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* more than or equal to MAX_PHASES.
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*/
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return -EINVAL;
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/* Merge 2 cyclic windows */
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i = phases_15;
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for (cnt = 0; cnt < phases_0; cnt++) {
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ranges[phase_15_raw_index][i] =
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ranges[phase_0_raw_index][cnt];
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if (++i >= MAX_PHASES)
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break;
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}
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phases_per_row[phase_0_raw_index] = 0;
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phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
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}
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for (cnt = 0; cnt <= row_index; cnt++) {
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if (phases_per_row[cnt] > curr_max) {
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curr_max = phases_per_row[cnt];
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selected_row_index = cnt;
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}
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}
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i = (curr_max * 3) / 4;
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if (i)
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i--;
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ret = ranges[selected_row_index][i];
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if (ret >= MAX_PHASES) {
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ret = -EINVAL;
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dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
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mmc_hostname(mmc), ret);
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}
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return ret;
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}
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static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
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{
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u32 mclk_freq = 0, config;
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/* Program the MCLK value to MCLK_FREQ bit field */
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if (host->clock <= 112000000)
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mclk_freq = 0;
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else if (host->clock <= 125000000)
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mclk_freq = 1;
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else if (host->clock <= 137000000)
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mclk_freq = 2;
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else if (host->clock <= 150000000)
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mclk_freq = 3;
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else if (host->clock <= 162000000)
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mclk_freq = 4;
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else if (host->clock <= 175000000)
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mclk_freq = 5;
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else if (host->clock <= 187000000)
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mclk_freq = 6;
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else if (host->clock <= 200000000)
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mclk_freq = 7;
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config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
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config &= ~CMUX_SHIFT_PHASE_MASK;
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config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
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writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
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}
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/* Initialize the DLL (Programmable Delay Line) */
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static int msm_init_cm_dll(struct sdhci_host *host)
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{
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struct mmc_host *mmc = host->mmc;
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int wait_cnt = 50;
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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/*
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* Make sure that clock is always enabled when DLL
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* tuning is in progress. Keeping PWRSAVE ON may
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* turn off the clock.
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*/
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
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& ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC);
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/* Write 1 to DLL_RST bit of DLL_CONFIG register */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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| CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
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/* Write 1 to DLL_PDN bit of DLL_CONFIG register */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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| CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
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msm_cm_dll_set_freq(host);
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/* Write 0 to DLL_RST bit of DLL_CONFIG register */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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& ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
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/* Write 0 to DLL_PDN bit of DLL_CONFIG register */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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& ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
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/* Set DLL_EN bit to 1. */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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| CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG);
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/* Set CK_OUT_EN bit to 1. */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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| CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
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/* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
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while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
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CORE_DLL_LOCK)) {
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/* max. wait for 50us sec for LOCK bit to be set */
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if (--wait_cnt == 0) {
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dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
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mmc_hostname(mmc));
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spin_unlock_irqrestore(&host->lock, flags);
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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spin_unlock_irqrestore(&host->lock, flags);
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return 0;
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}
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static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
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{
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int tuning_seq_cnt = 3;
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u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
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int rc;
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struct mmc_host *mmc = host->mmc;
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struct mmc_ios ios = host->mmc->ios;
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/*
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* Tuning is required for SDR104, HS200 and HS400 cards and
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* if clock frequency is greater than 100MHz in these modes.
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*/
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if (host->clock <= 100 * 1000 * 1000 ||
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!((ios.timing == MMC_TIMING_MMC_HS200) ||
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(ios.timing == MMC_TIMING_UHS_SDR104)))
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return 0;
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retry:
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/* First of all reset the tuning block */
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rc = msm_init_cm_dll(host);
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if (rc)
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return rc;
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phase = 0;
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do {
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/* Set the phase in delay line hw block */
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rc = msm_config_cm_dll_phase(host, phase);
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if (rc)
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return rc;
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rc = mmc_send_tuning(mmc, opcode, NULL);
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if (!rc) {
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/* Tuning is successful at this tuning point */
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tuned_phases[tuned_phase_cnt++] = phase;
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dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
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mmc_hostname(mmc), phase);
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}
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} while (++phase < ARRAY_SIZE(tuned_phases));
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if (tuned_phase_cnt) {
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rc = msm_find_most_appropriate_phase(host, tuned_phases,
|
||||
tuned_phase_cnt);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
else
|
||||
phase = rc;
|
||||
|
||||
/*
|
||||
* Finally set the selected phase in delay
|
||||
* line hw block.
|
||||
*/
|
||||
rc = msm_config_cm_dll_phase(host, phase);
|
||||
if (rc)
|
||||
return rc;
|
||||
dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
|
||||
mmc_hostname(mmc), phase);
|
||||
} else {
|
||||
if (--tuning_seq_cnt)
|
||||
goto retry;
|
||||
/* Tuning failed */
|
||||
dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
|
||||
mmc_hostname(mmc));
|
||||
rc = -EIO;
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static const struct of_device_id sdhci_msm_dt_match[] = {
|
||||
{ .compatible = "qcom,sdhci-msm" },
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
|
||||
|
||||
static struct sdhci_ops sdhci_msm_ops = {
|
||||
.platform_execute_tuning = sdhci_msm_execute_tuning,
|
||||
.reset = sdhci_reset,
|
||||
.set_clock = sdhci_set_clock,
|
||||
.set_bus_width = sdhci_set_bus_width,
|
||||
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
||||
};
|
||||
|
||||
static int sdhci_msm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sdhci_host *host;
|
||||
struct sdhci_pltfm_host *pltfm_host;
|
||||
struct sdhci_msm_host *msm_host;
|
||||
struct resource *core_memres;
|
||||
int ret;
|
||||
u16 host_version, core_minor;
|
||||
u32 core_version, caps;
|
||||
u8 core_major;
|
||||
|
||||
msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
|
||||
if (!msm_host)
|
||||
return -ENOMEM;
|
||||
|
||||
msm_host->sdhci_msm_pdata.ops = &sdhci_msm_ops;
|
||||
host = sdhci_pltfm_init(pdev, &msm_host->sdhci_msm_pdata, 0);
|
||||
if (IS_ERR(host))
|
||||
return PTR_ERR(host);
|
||||
|
||||
pltfm_host = sdhci_priv(host);
|
||||
pltfm_host->priv = msm_host;
|
||||
msm_host->mmc = host->mmc;
|
||||
msm_host->pdev = pdev;
|
||||
|
||||
ret = mmc_of_parse(host->mmc);
|
||||
if (ret)
|
||||
goto pltfm_free;
|
||||
|
||||
sdhci_get_of_property(pdev);
|
||||
|
||||
msm_host->vdd = devm_regulator_get(&pdev->dev, "vdd");
|
||||
if (IS_ERR(msm_host->vdd)) {
|
||||
ret = PTR_ERR(msm_host->vdd);
|
||||
dev_err(&pdev->dev, "VDD regulator setup failed (%d)\n", ret);
|
||||
goto pltfm_free;
|
||||
}
|
||||
|
||||
msm_host->vdd_io = devm_regulator_get(&pdev->dev, "vdd-io");
|
||||
if (IS_ERR(msm_host->vdd_io)) {
|
||||
ret = PTR_ERR(msm_host->vdd_io);
|
||||
dev_err(&pdev->dev, "VDD-IO regulator setup failed (%d)\n", ret);
|
||||
goto pltfm_free;
|
||||
}
|
||||
|
||||
ret = regulator_set_optimum_mode(msm_host->vdd, 500000);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "VDD setting current load failed (%d)\n", ret);
|
||||
goto pltfm_free;
|
||||
}
|
||||
|
||||
ret = regulator_set_optimum_mode(msm_host->vdd_io, 154000);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "VDD-IO setting current load failed (%d)\n", ret);
|
||||
goto pltfm_free;
|
||||
}
|
||||
|
||||
ret = regulator_set_voltage(msm_host->vdd, 2950000, 2950000);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "VDD setting voltage failed (%d)\n", ret);
|
||||
goto pltfm_free;
|
||||
}
|
||||
|
||||
ret = regulator_set_voltage(msm_host->vdd_io, 1800000, 1800000);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "VDD-IO setting voltage failed (%d)\n", ret);
|
||||
goto pltfm_free;
|
||||
}
|
||||
|
||||
ret = regulator_enable(msm_host->vdd);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "VDD enabling regulator failed (%d)\n", ret);
|
||||
goto pltfm_free;
|
||||
}
|
||||
|
||||
ret = regulator_enable(msm_host->vdd_io);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "VDD-IO enabling regulator failed (%d)\n", ret);
|
||||
goto reg_vdd_disable;
|
||||
}
|
||||
|
||||
/* Setup SDCC bus voter clock. */
|
||||
msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
|
||||
if (!IS_ERR(msm_host->bus_clk)) {
|
||||
/* Vote for max. clk rate for max. performance */
|
||||
ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
|
||||
if (ret)
|
||||
goto reg_vdd_io_disable;
|
||||
ret = clk_prepare_enable(msm_host->bus_clk);
|
||||
if (ret)
|
||||
goto reg_vdd_io_disable;
|
||||
}
|
||||
|
||||
/* Setup main peripheral bus clock */
|
||||
msm_host->pclk = devm_clk_get(&pdev->dev, "iface_clk");
|
||||
if (IS_ERR(msm_host->pclk)) {
|
||||
ret = PTR_ERR(msm_host->pclk);
|
||||
dev_err(&pdev->dev, "Perpheral clk setup failed (%d)\n", ret);
|
||||
goto bus_clk_disable;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(msm_host->pclk);
|
||||
if (ret)
|
||||
goto bus_clk_disable;
|
||||
|
||||
/* Setup SDC MMC clock */
|
||||
msm_host->clk = devm_clk_get(&pdev->dev, "core_clk");
|
||||
if (IS_ERR(msm_host->clk)) {
|
||||
ret = PTR_ERR(msm_host->clk);
|
||||
dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
|
||||
goto pclk_disable;
|
||||
}
|
||||
|
||||
/* Vote for maximum clock rate for maximum performance */
|
||||
ret = clk_set_rate(msm_host->clk, INT_MAX);
|
||||
if (ret)
|
||||
dev_warn(&pdev->dev, "core clock boost failed\n");
|
||||
|
||||
ret = clk_prepare_enable(msm_host->clk);
|
||||
if (ret)
|
||||
goto pclk_disable;
|
||||
|
||||
core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
|
||||
|
||||
if (IS_ERR(msm_host->core_mem)) {
|
||||
dev_err(&pdev->dev, "Failed to remap registers\n");
|
||||
ret = PTR_ERR(msm_host->core_mem);
|
||||
goto clk_disable;
|
||||
}
|
||||
|
||||
/* Disable mode selection via the vendor specific register */
|
||||
writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
|
||||
& ~CORE_HC_SELECT_IN_EN
|
||||
& ~CORE_HC_SELECT_IN_MASK),
|
||||
host->ioaddr + CORE_VENDOR_SPEC);
|
||||
|
||||
/* Reset the core and Enable SDHC mode */
|
||||
writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |
|
||||
CORE_SW_RST, msm_host->core_mem + CORE_POWER);
|
||||
|
||||
/* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
|
||||
usleep_range(1000, 5000);
|
||||
if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) {
|
||||
dev_err(&pdev->dev, "Stuck in reset\n");
|
||||
ret = -ETIMEDOUT;
|
||||
goto clk_disable;
|
||||
}
|
||||
|
||||
/* Set HC_MODE_EN bit in HC_MODE register */
|
||||
writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
|
||||
|
||||
writel_relaxed((readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES) |
|
||||
CORE_3_0V_SUPPORT | CORE_8_BIT_SUPPORT),
|
||||
host->ioaddr + CORE_VENDOR_SPEC_CAPABILITIES0);
|
||||
|
||||
host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
|
||||
host->quirks |= SDHCI_QUIRK_SINGLE_POWER_WRITE;
|
||||
host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
|
||||
|
||||
host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
|
||||
dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
|
||||
host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
|
||||
SDHCI_VENDOR_VER_SHIFT));
|
||||
|
||||
core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
|
||||
core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
|
||||
CORE_VERSION_MAJOR_SHIFT;
|
||||
core_minor = core_version & CORE_VERSION_MINOR_MASK;
|
||||
dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
|
||||
core_version, core_major, core_minor);
|
||||
|
||||
/*
|
||||
* Support for some capabilities is not advertised by newer
|
||||
* controller versions and must be explicitly enabled.
|
||||
*/
|
||||
if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
|
||||
caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
|
||||
caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
|
||||
writel_relaxed(caps, host->ioaddr +
|
||||
CORE_VENDOR_SPEC_CAPABILITIES0);
|
||||
}
|
||||
|
||||
ret = sdhci_add_host(host);
|
||||
if (ret)
|
||||
goto clk_disable;
|
||||
|
||||
return 0;
|
||||
|
||||
clk_disable:
|
||||
clk_disable_unprepare(msm_host->clk);
|
||||
pclk_disable:
|
||||
clk_disable_unprepare(msm_host->pclk);
|
||||
bus_clk_disable:
|
||||
if (!IS_ERR(msm_host->bus_clk))
|
||||
clk_disable_unprepare(msm_host->bus_clk);
|
||||
reg_vdd_io_disable:
|
||||
regulator_disable(msm_host->vdd_io);
|
||||
reg_vdd_disable:
|
||||
regulator_disable(msm_host->vdd);
|
||||
pltfm_free:
|
||||
sdhci_pltfm_free(pdev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sdhci_msm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sdhci_host *host = platform_get_drvdata(pdev);
|
||||
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
||||
struct sdhci_msm_host *msm_host = pltfm_host->priv;
|
||||
int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
|
||||
0xffffffff);
|
||||
|
||||
sdhci_remove_host(host, dead);
|
||||
sdhci_pltfm_free(pdev);
|
||||
clk_disable_unprepare(msm_host->clk);
|
||||
clk_disable_unprepare(msm_host->pclk);
|
||||
if (!IS_ERR(msm_host->bus_clk))
|
||||
clk_disable_unprepare(msm_host->bus_clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver sdhci_msm_driver = {
|
||||
.probe = sdhci_msm_probe,
|
||||
.remove = sdhci_msm_remove,
|
||||
.driver = {
|
||||
.name = "sdhci_msm",
|
||||
.of_match_table = sdhci_msm_dt_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(sdhci_msm_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
|
||||
MODULE_LICENSE("GPL v2");
|
Loading…
Add table
Reference in a new issue