evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

staging: comedi: ni_tio: tidy up Gi_Second_Gate_Bits

Browse source 
Convert this enum into defines and rename the CamelCase symbols.

For aesthetics, move the new defines so they are associated with
the register define.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten 2014-07-28 10:26:52 -07:00 • committed by Greg Kroah-Hartman
parent 36d80f4a54
commit 4359dcf356
2 changed files with 25 additions and 42 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

44
drivers/staging/comedi/drivers/ni_tio.c
View file

@ -267,8 +267,7 @@ static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter)
clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
break;
case NI_M_TIMEBASE_3_CLK:
if (counter_dev->regs[second_gate_reg] &
Gi_Source_Subselect_Bit)
if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
clock_source =
NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
else
@ -278,8 +277,7 @@ static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter)
clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
break;
case NI_M_NEXT_GATE_CLK:
if (counter_dev->regs[second_gate_reg] &
Gi_Source_Subselect_Bit)
if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
else
clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
@ -666,12 +664,12 @@ static void ni_tio_set_source_subselect(struct ni_gpct *counter,
/* Gi_Source_Subselect is zero */
case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
counter_dev->regs[second_gate_reg] &= ~Gi_Source_Subselect_Bit;
counter_dev->regs[second_gate_reg] &= ~GI_SRC_SUBSEL;
break;
/* Gi_Source_Subselect is one */
case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
counter_dev->regs[second_gate_reg] |= Gi_Source_Subselect_Bit;
counter_dev->regs[second_gate_reg] |= GI_SRC_SUBSEL;
break;
/* Gi_Source_Subselect doesn't matter */
default:
@ -863,9 +861,9 @@ static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
break;
return -EINVAL;
}
counter_dev->regs[gate2_reg] |= Gi_Second_Gate_Mode_Bit;
counter_dev->regs[gate2_reg] &= ~Gi_Second_Gate_Select_Mask;
counter_dev->regs[gate2_reg] |= Gi_Second_Gate_Select_Bits(gate2_sel);
counter_dev->regs[gate2_reg] |= GI_GATE2_MODE;
counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK;
counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel);
write_register(counter, counter_dev->regs[gate2_reg], gate2_reg);
return 0;
}
@ -887,9 +885,9 @@ static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
gate2_sel = chan & 0x1f;
break;
}
counter_dev->regs[gate2_reg] |= Gi_Second_Gate_Mode_Bit;
counter_dev->regs[gate2_reg] &= ~Gi_Second_Gate_Select_Mask;
counter_dev->regs[gate2_reg] |= Gi_Second_Gate_Select_Bits(gate2_sel);
counter_dev->regs[gate2_reg] |= GI_GATE2_MODE;
counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK;
counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel);
write_register(counter, counter_dev->regs[gate2_reg], gate2_reg);
return 0;
}
@ -934,19 +932,15 @@ int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
return -EINVAL;
if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
counter_dev->regs[gate2_reg] &=
~Gi_Second_Gate_Mode_Bit;
counter_dev->regs[gate2_reg] &= ~GI_GATE2_MODE;
write_register(counter, counter_dev->regs[gate2_reg],
gate2_reg);
return 0;
}
if (gate_source & CR_INVERT) {
counter_dev->regs[gate2_reg] |=
Gi_Second_Gate_Polarity_Bit;
} else {
counter_dev->regs[gate2_reg] &=
~Gi_Second_Gate_Polarity_Bit;
}
if (gate_source & CR_INVERT)
counter_dev->regs[gate2_reg] |= GI_GATE2_POL_INVERT;
else
counter_dev->regs[gate2_reg] &= ~GI_GATE2_POL_INVERT;
switch (counter_dev->variant) {
case ni_gpct_variant_m_series:
return ni_m_set_gate2(counter, gate_source);
@ -1157,14 +1151,12 @@ static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
break;
case 1:
if ((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED ||
!(counter_dev->regs[gate2_reg] & Gi_Second_Gate_Mode_Bit)) {
!(counter_dev->regs[gate2_reg] & GI_GATE2_MODE)) {
*gate_source = NI_GPCT_DISABLED_GATE_SELECT;
return 0;
}
gate = counter_dev->regs[gate2_reg];
gate &= Gi_Second_Gate_Select_Mask;
gate >>= Gi_Second_Gate_Select_Shift;
gate = GI_BITS_TO_GATE2(counter_dev->regs[gate2_reg]);
switch (counter_dev->variant) {
case ni_gpct_variant_e_series:
@ -1176,7 +1168,7 @@ static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
*gate_source = ni_660x_gate2_to_generic_gate(gate);
break;
}
if (counter_dev->regs[gate2_reg] & Gi_Second_Gate_Polarity_Bit)
if (counter_dev->regs[gate2_reg] & GI_GATE2_POL_INVERT)
*gate_source |= CR_INVERT;
/* second gate can't have edge/level mode set independently */
if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)

23
drivers/staging/comedi/drivers/ni_tio_internal.h
View file

@ -109,6 +109,13 @@
#define GI_660X_PRESCALE_X2 (1 << 14)
#define GI_M_PRESCALE_X2 (1 << 15)
#define NITIO_GATE2_REG(x) (NITIO_G0_GATE2 + (x))
#define GI_GATE2_MODE (1 << 0)
#define GI_BITS_TO_GATE2(x) (((x) >> 7) & 0x1f)
#define GI_GATE2_SEL(x) (((x) & 0x1f) << 7)
#define GI_GATE2_SEL_MASK (0x1f << 7)
#define GI_GATE2_POL_INVERT (1 << 13)
#define GI_GATE2_SUBSEL (1 << 14)
#define GI_SRC_SUBSEL (1 << 15)
#define NITIO_SHARED_STATUS_REG(x) (NITIO_G01_STATUS + ((x) / 2))
#define NITIO_RESET_REG(x) (NITIO_G01_RESET + ((x) / 2))
#define NITIO_STATUS1_REG(x) (NITIO_G01_STATUS1 + ((x) / 2))
@ -120,22 +127,6 @@
#define NITIO_STATUS_REG(x) (NITIO_G0_STATUS + (x))
#define NITIO_INT_ENA_REG(x) (NITIO_G0_INT_ENA + (x))
#define Gi_Second_Gate_Select_Shift 7
/*FIXME: m-series has a second gate subselect bit */
/*FIXME: m-series second gate sources are undocumented (by NI)*/
enum Gi_Second_Gate_Bits {
Gi_Second_Gate_Mode_Bit = 0x1,
Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
Gi_Second_Gate_Polarity_Bit = 0x2000,
Gi_Second_Gate_Subselect_Bit = 0x4000, /* m-series only */
Gi_Source_Subselect_Bit = 0x8000 /* m-series only */
};
static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select)
{
return (second_gate_select << Gi_Second_Gate_Select_Shift) &
Gi_Second_Gate_Select_Mask;
}
enum Gxx_Status_Bits {
G0_Save_Bit = 0x1,
G1_Save_Bit = 0x2,