ARM: dts: msm: Add SPSS SSR support for MSMCOBALT.

Add register offsets read during secure processor SSR for MSMCOBALT.

CRs-Fixed: 979349
Change-Id: I14504819e04c3e952fcdbceba5a20f876b92ae88
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
This commit is contained in:
Puja Gupta 2016-02-19 11:29:40 -08:00 committed by Jeevan Shriram
parent 7e9330a50a
commit 438d5e6664

View file

@ -1910,9 +1910,10 @@
reg = <0x1d0101c 0x4>, reg = <0x1d0101c 0x4>,
<0x1d01024 0x4>, <0x1d01024 0x4>,
<0x1d01028 0x4>, <0x1d01028 0x4>,
<0x1d0103c 0x4>; <0x1d0103c 0x4>,
<0x1d02030 0x4>;
reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", reg-names = "sp2soc_irq_status", "sp2soc_irq_clr",
"sp2soc_irq_mask","rmb_err"; "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2";
interrupts = <0 352 1>; interrupts = <0 352 1>;
vdd_cx-supply = <&pmcobalt_s1_level>; vdd_cx-supply = <&pmcobalt_s1_level>;
@ -1929,7 +1930,7 @@
qcom,proxy-timeout-ms = <10000>; qcom,proxy-timeout-ms = <10000>;
qcom,firmware-name = "spss"; qcom,firmware-name = "spss";
memory-region = <&peripheral_mem>; memory-region = <&peripheral_mem>;
qcom,spss-scsr-bits = <0 1 2 3 16 17 24 25>; qcom,spss-scsr-bits = <24 25>;
}; };
qcom,msm-rtb { qcom,msm-rtb {