ARM: dts: msm: Add SPSS SSR support for MSMCOBALT.
Add register offsets read during secure processor SSR for MSMCOBALT. CRs-Fixed: 979349 Change-Id: I14504819e04c3e952fcdbceba5a20f876b92ae88 Signed-off-by: Puja Gupta <pujag@codeaurora.org>
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1 changed files with 4 additions and 3 deletions
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@ -1910,9 +1910,10 @@
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reg = <0x1d0101c 0x4>,
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reg = <0x1d0101c 0x4>,
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<0x1d01024 0x4>,
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<0x1d01024 0x4>,
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<0x1d01028 0x4>,
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<0x1d01028 0x4>,
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<0x1d0103c 0x4>;
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<0x1d0103c 0x4>,
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<0x1d02030 0x4>;
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reg-names = "sp2soc_irq_status", "sp2soc_irq_clr",
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reg-names = "sp2soc_irq_status", "sp2soc_irq_clr",
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"sp2soc_irq_mask","rmb_err";
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"sp2soc_irq_mask", "rmb_err", "rmb_err_spare2";
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interrupts = <0 352 1>;
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interrupts = <0 352 1>;
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vdd_cx-supply = <&pmcobalt_s1_level>;
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vdd_cx-supply = <&pmcobalt_s1_level>;
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@ -1929,7 +1930,7 @@
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qcom,proxy-timeout-ms = <10000>;
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qcom,proxy-timeout-ms = <10000>;
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qcom,firmware-name = "spss";
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qcom,firmware-name = "spss";
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memory-region = <&peripheral_mem>;
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memory-region = <&peripheral_mem>;
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qcom,spss-scsr-bits = <0 1 2 3 16 17 24 25>;
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qcom,spss-scsr-bits = <24 25>;
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};
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};
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qcom,msm-rtb {
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qcom,msm-rtb {
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