Merge branch 'staging-next' into Linux 3.1
This was done to resolve a conflict in the drivers/staging/comedi/drivers/ni_labpc.c file that resolved a build bugfix in Linus's tree with a "better" bugfix that was in the staging-next tree that resolved the issue in a more complete manner. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
commit
43a3beb6da
834 changed files with 104277 additions and 230821 deletions
14
MAINTAINERS
14
MAINTAINERS
|
@ -6134,7 +6134,7 @@ S: Maintained
|
|||
|
||||
STAGING SUBSYSTEM
|
||||
M: Greg Kroah-Hartman <gregkh@suse.de>
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git
|
||||
L: devel@driverdev.osuosl.org
|
||||
S: Maintained
|
||||
F: drivers/staging/
|
||||
|
@ -6181,6 +6181,11 @@ M: David Rowe <david@rowetel.com>
|
|||
S: Odd Fixes
|
||||
F: drivers/staging/echo/
|
||||
|
||||
STAGING - ET131X NETWORK DRIVER
|
||||
M: Mark Einon <mark.einon@gmail.com>
|
||||
S: Odd Fixes
|
||||
F: drivers/staging/et131x/
|
||||
|
||||
STAGING - FLARION FT1000 DRIVERS
|
||||
M: Marek Belisko <marek.belisko@gmail.com>
|
||||
S: Odd Fixes
|
||||
|
@ -6209,6 +6214,13 @@ W: http://www.lirc.org/
|
|||
S: Odd Fixes
|
||||
F: drivers/staging/lirc/
|
||||
|
||||
STAGING - NVIDIA COMPLIANT EMBEDDED CONTROLLER INTERFACE (nvec)
|
||||
M: Julian Andres Klode <jak@jak-linux.org>
|
||||
M: Marc Dietrich <marvin24@gmx.de>
|
||||
L: ac100@lists.launchpad.net (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: drivers/staging/nvec/
|
||||
|
||||
STAGING - OLPC SECONDARY DISPLAY CONTROLLER (DCON)
|
||||
M: Andres Salomon <dilinger@queued.net>
|
||||
M: Chris Ball <cjb@laptop.org>
|
||||
|
|
|
@ -189,5 +189,6 @@
|
|||
#define HV_STATUS_INVALID_HYPERCALL_CODE 2
|
||||
#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
|
||||
#define HV_STATUS_INVALID_ALIGNMENT 4
|
||||
#define HV_STATUS_INSUFFICIENT_BUFFERS 19
|
||||
|
||||
#endif
|
||||
|
|
|
@ -130,4 +130,6 @@ source "drivers/iommu/Kconfig"
|
|||
|
||||
source "drivers/virt/Kconfig"
|
||||
|
||||
source "drivers/hv/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -127,3 +127,5 @@ obj-$(CONFIG_IOMMU_SUPPORT) += iommu/
|
|||
|
||||
# Virtualization drivers
|
||||
obj-$(CONFIG_VIRT_DRIVERS) += virt/
|
||||
obj-$(CONFIG_HYPERV) += hv/
|
||||
|
||||
|
|
|
@ -1,613 +0,0 @@
|
|||
/*
|
||||
* atari_SCC.h: Definitions for the Am8530 Serial Communications Controller
|
||||
*
|
||||
* Copyright 1994 Roman Hodek <Roman.Hodek@informatik.uni-erlangen.de>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _SCC_H
|
||||
#define _SCC_H
|
||||
|
||||
#include <linux/delay.h>
|
||||
|
||||
/* Special configuration ioctls for the Atari SCC5380 Serial
|
||||
* Communications Controller
|
||||
*/
|
||||
|
||||
/* ioctl command codes */
|
||||
|
||||
#define TIOCGATSCC 0x54c0 /* get SCC configuration */
|
||||
#define TIOCSATSCC 0x54c1 /* set SCC configuration */
|
||||
#define TIOCDATSCC 0x54c2 /* reset configuration to defaults */
|
||||
|
||||
/* Clock sources */
|
||||
|
||||
#define CLK_RTxC 0
|
||||
#define CLK_TRxC 1
|
||||
#define CLK_PCLK 2
|
||||
|
||||
/* baud_bases for the common clocks in the Atari. These are the real
|
||||
* frequencies divided by 16.
|
||||
*/
|
||||
|
||||
#define SCC_BAUD_BASE_TIMC 19200 /* 0.3072 MHz from TT-MFP, Timer C */
|
||||
#define SCC_BAUD_BASE_BCLK 153600 /* 2.4576 MHz */
|
||||
#define SCC_BAUD_BASE_PCLK4 229500 /* 3.6720 MHz */
|
||||
#define SCC_BAUD_BASE_PCLK 503374 /* 8.0539763 MHz */
|
||||
#define SCC_BAUD_BASE_NONE 0 /* for not connected or unused
|
||||
* clock sources */
|
||||
|
||||
/* The SCC clock configuration structure */
|
||||
|
||||
struct scc_clock_config {
|
||||
unsigned RTxC_base; /* base_baud of RTxC */
|
||||
unsigned TRxC_base; /* base_baud of TRxC */
|
||||
unsigned PCLK_base; /* base_baud of PCLK, both channels! */
|
||||
struct {
|
||||
unsigned clksrc; /* CLK_RTxC, CLK_TRxC or CLK_PCLK */
|
||||
unsigned divisor; /* divisor for base baud, valid values:
|
||||
* see below */
|
||||
} baud_table[17]; /* For 50, 75, 110, 135, 150, 200, 300,
|
||||
* 600, 1200, 1800, 2400, 4800, 9600,
|
||||
* 19200, 38400, 57600 and 115200 bps.
|
||||
* The last two could be replaced by
|
||||
* other rates > 38400 if they're not
|
||||
* possible.
|
||||
*/
|
||||
};
|
||||
|
||||
/* The following divisors are valid:
|
||||
*
|
||||
* - CLK_RTxC: 1 or even (1, 2 and 4 are the direct modes, > 4 use
|
||||
* the BRG)
|
||||
*
|
||||
* - CLK_TRxC: 1, 2 or 4 (no BRG, only direct modes possible)
|
||||
*
|
||||
* - CLK_PCLK: >= 4 and even (no direct modes, only BRG)
|
||||
*
|
||||
*/
|
||||
|
||||
struct scc_port {
|
||||
struct gs_port gs;
|
||||
volatile unsigned char *ctrlp;
|
||||
volatile unsigned char *datap;
|
||||
int x_char; /* xon/xoff character */
|
||||
int c_dcd;
|
||||
int channel;
|
||||
struct scc_port *port_a; /* Reference to port A and B */
|
||||
struct scc_port *port_b; /* structs for reg access */
|
||||
};
|
||||
|
||||
#define SCC_MAGIC 0x52696368
|
||||
|
||||
/***********************************************************************/
|
||||
/* */
|
||||
/* Register Names */
|
||||
/* */
|
||||
/***********************************************************************/
|
||||
|
||||
/* The SCC documentation gives no explicit names to the registers,
|
||||
* they're just called WR0..15 and RR0..15. To make the source code
|
||||
* better readable and make the transparent write reg read access (see
|
||||
* below) possible, I christen them here with self-invented names.
|
||||
* Note that (real) read registers are assigned numbers 16..31. WR7'
|
||||
* has number 33.
|
||||
*/
|
||||
|
||||
#define COMMAND_REG 0 /* wo */
|
||||
#define INT_AND_DMA_REG 1 /* wo */
|
||||
#define INT_VECTOR_REG 2 /* rw, common to both channels */
|
||||
#define RX_CTRL_REG 3 /* rw */
|
||||
#define AUX1_CTRL_REG 4 /* rw */
|
||||
#define TX_CTRL_REG 5 /* rw */
|
||||
#define SYNC_ADR_REG 6 /* wo */
|
||||
#define SYNC_CHAR_REG 7 /* wo */
|
||||
#define SDLC_OPTION_REG 33 /* wo */
|
||||
#define TX_DATA_REG 8 /* wo */
|
||||
#define MASTER_INT_CTRL 9 /* wo, common to both channels */
|
||||
#define AUX2_CTRL_REG 10 /* rw */
|
||||
#define CLK_CTRL_REG 11 /* wo */
|
||||
#define TIMER_LOW_REG 12 /* rw */
|
||||
#define TIMER_HIGH_REG 13 /* rw */
|
||||
#define DPLL_CTRL_REG 14 /* wo */
|
||||
#define INT_CTRL_REG 15 /* rw */
|
||||
|
||||
#define STATUS_REG 16 /* ro */
|
||||
#define SPCOND_STATUS_REG 17 /* wo */
|
||||
/* RR2 is WR2 for Channel A, Channel B gives vector + current status: */
|
||||
#define CURR_VECTOR_REG 18 /* Ch. B only, Ch. A for rw */
|
||||
#define INT_PENDING_REG 19 /* Channel A only! */
|
||||
/* RR4 is WR4, if b6(MR7') == 1 */
|
||||
/* RR5 is WR5, if b6(MR7') == 1 */
|
||||
#define FS_FIFO_LOW_REG 22 /* ro */
|
||||
#define FS_FIFO_HIGH_REG 23 /* ro */
|
||||
#define RX_DATA_REG 24 /* ro */
|
||||
/* RR9 is WR3, if b6(MR7') == 1 */
|
||||
#define DPLL_STATUS_REG 26 /* ro */
|
||||
/* RR11 is WR10, if b6(MR7') == 1 */
|
||||
/* RR12 is WR12 */
|
||||
/* RR13 is WR13 */
|
||||
/* RR14 not present */
|
||||
/* RR15 is WR15 */
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/* */
|
||||
/* Register Values */
|
||||
/* */
|
||||
/***********************************************************************/
|
||||
|
||||
|
||||
/* WR0: COMMAND_REG "CR" */
|
||||
|
||||
#define CR_RX_CRC_RESET 0x40
|
||||
#define CR_TX_CRC_RESET 0x80
|
||||
#define CR_TX_UNDERRUN_RESET 0xc0
|
||||
|
||||
#define CR_EXTSTAT_RESET 0x10
|
||||
#define CR_SEND_ABORT 0x18
|
||||
#define CR_ENAB_INT_NEXT_RX 0x20
|
||||
#define CR_TX_PENDING_RESET 0x28
|
||||
#define CR_ERROR_RESET 0x30
|
||||
#define CR_HIGHEST_IUS_RESET 0x38
|
||||
|
||||
|
||||
/* WR1: INT_AND_DMA_REG "IDR" */
|
||||
|
||||
#define IDR_EXTSTAT_INT_ENAB 0x01
|
||||
#define IDR_TX_INT_ENAB 0x02
|
||||
#define IDR_PARERR_AS_SPCOND 0x04
|
||||
|
||||
#define IDR_RX_INT_DISAB 0x00
|
||||
#define IDR_RX_INT_FIRST 0x08
|
||||
#define IDR_RX_INT_ALL 0x10
|
||||
#define IDR_RX_INT_SPCOND 0x18
|
||||
#define IDR_RX_INT_MASK 0x18
|
||||
|
||||
#define IDR_WAITREQ_RX 0x20
|
||||
#define IDR_WAITREQ_IS_REQ 0x40
|
||||
#define IDR_WAITREQ_ENAB 0x80
|
||||
|
||||
|
||||
/* WR3: RX_CTRL_REG "RCR" */
|
||||
|
||||
#define RCR_RX_ENAB 0x01
|
||||
#define RCR_DISCARD_SYNC_CHARS 0x02
|
||||
#define RCR_ADDR_SEARCH 0x04
|
||||
#define RCR_CRC_ENAB 0x08
|
||||
#define RCR_SEARCH_MODE 0x10
|
||||
#define RCR_AUTO_ENAB_MODE 0x20
|
||||
|
||||
#define RCR_CHSIZE_MASK 0xc0
|
||||
#define RCR_CHSIZE_5 0x00
|
||||
#define RCR_CHSIZE_6 0x40
|
||||
#define RCR_CHSIZE_7 0x80
|
||||
#define RCR_CHSIZE_8 0xc0
|
||||
|
||||
|
||||
/* WR4: AUX1_CTRL_REG "A1CR" */
|
||||
|
||||
#define A1CR_PARITY_MASK 0x03
|
||||
#define A1CR_PARITY_NONE 0x00
|
||||
#define A1CR_PARITY_ODD 0x01
|
||||
#define A1CR_PARITY_EVEN 0x03
|
||||
|
||||
#define A1CR_MODE_MASK 0x0c
|
||||
#define A1CR_MODE_SYNCR 0x00
|
||||
#define A1CR_MODE_ASYNC_1 0x04
|
||||
#define A1CR_MODE_ASYNC_15 0x08
|
||||
#define A1CR_MODE_ASYNC_2 0x0c
|
||||
|
||||
#define A1CR_SYNCR_MODE_MASK 0x30
|
||||
#define A1CR_SYNCR_MONOSYNC 0x00
|
||||
#define A1CR_SYNCR_BISYNC 0x10
|
||||
#define A1CR_SYNCR_SDLC 0x20
|
||||
#define A1CR_SYNCR_EXTCSYNC 0x30
|
||||
|
||||
#define A1CR_CLKMODE_MASK 0xc0
|
||||
#define A1CR_CLKMODE_x1 0x00
|
||||
#define A1CR_CLKMODE_x16 0x40
|
||||
#define A1CR_CLKMODE_x32 0x80
|
||||
#define A1CR_CLKMODE_x64 0xc0
|
||||
|
||||
|
||||
/* WR5: TX_CTRL_REG "TCR" */
|
||||
|
||||
#define TCR_TX_CRC_ENAB 0x01
|
||||
#define TCR_RTS 0x02
|
||||
#define TCR_USE_CRC_CCITT 0x00
|
||||
#define TCR_USE_CRC_16 0x04
|
||||
#define TCR_TX_ENAB 0x08
|
||||
#define TCR_SEND_BREAK 0x10
|
||||
|
||||
#define TCR_CHSIZE_MASK 0x60
|
||||
#define TCR_CHSIZE_5 0x00
|
||||
#define TCR_CHSIZE_6 0x20
|
||||
#define TCR_CHSIZE_7 0x40
|
||||
#define TCR_CHSIZE_8 0x60
|
||||
|
||||
#define TCR_DTR 0x80
|
||||
|
||||
|
||||
/* WR7': SLDC_OPTION_REG "SOR" */
|
||||
|
||||
#define SOR_AUTO_TX_ENAB 0x01
|
||||
#define SOR_AUTO_EOM_RESET 0x02
|
||||
#define SOR_AUTO_RTS_MODE 0x04
|
||||
#define SOR_NRZI_DISAB_HIGH 0x08
|
||||
#define SOR_ALT_DTRREQ_TIMING 0x10
|
||||
#define SOR_READ_CRC_CHARS 0x20
|
||||
#define SOR_EXTENDED_REG_ACCESS 0x40
|
||||
|
||||
|
||||
/* WR9: MASTER_INT_CTRL "MIC" */
|
||||
|
||||
#define MIC_VEC_INCL_STAT 0x01
|
||||
#define MIC_NO_VECTOR 0x02
|
||||
#define MIC_DISAB_LOWER_CHAIN 0x04
|
||||
#define MIC_MASTER_INT_ENAB 0x08
|
||||
#define MIC_STATUS_HIGH 0x10
|
||||
#define MIC_IGN_INTACK 0x20
|
||||
|
||||
#define MIC_NO_RESET 0x00
|
||||
#define MIC_CH_A_RESET 0x40
|
||||
#define MIC_CH_B_RESET 0x80
|
||||
#define MIC_HARD_RESET 0xc0
|
||||
|
||||
|
||||
/* WR10: AUX2_CTRL_REG "A2CR" */
|
||||
|
||||
#define A2CR_SYNC_6 0x01
|
||||
#define A2CR_LOOP_MODE 0x02
|
||||
#define A2CR_ABORT_ON_UNDERRUN 0x04
|
||||
#define A2CR_MARK_IDLE 0x08
|
||||
#define A2CR_GO_ACTIVE_ON_POLL 0x10
|
||||
|
||||
#define A2CR_CODING_MASK 0x60
|
||||
#define A2CR_CODING_NRZ 0x00
|
||||
#define A2CR_CODING_NRZI 0x20
|
||||
#define A2CR_CODING_FM1 0x40
|
||||
#define A2CR_CODING_FM0 0x60
|
||||
|
||||
#define A2CR_PRESET_CRC_1 0x80
|
||||
|
||||
|
||||
/* WR11: CLK_CTRL_REG "CCR" */
|
||||
|
||||
#define CCR_TRxCOUT_MASK 0x03
|
||||
#define CCR_TRxCOUT_XTAL 0x00
|
||||
#define CCR_TRxCOUT_TXCLK 0x01
|
||||
#define CCR_TRxCOUT_BRG 0x02
|
||||
#define CCR_TRxCOUT_DPLL 0x03
|
||||
|
||||
#define CCR_TRxC_OUTPUT 0x04
|
||||
|
||||
#define CCR_TXCLK_MASK 0x18
|
||||
#define CCR_TXCLK_RTxC 0x00
|
||||
#define CCR_TXCLK_TRxC 0x08
|
||||
#define CCR_TXCLK_BRG 0x10
|
||||
#define CCR_TXCLK_DPLL 0x18
|
||||
|
||||
#define CCR_RXCLK_MASK 0x60
|
||||
#define CCR_RXCLK_RTxC 0x00
|
||||
#define CCR_RXCLK_TRxC 0x20
|
||||
#define CCR_RXCLK_BRG 0x40
|
||||
#define CCR_RXCLK_DPLL 0x60
|
||||
|
||||
#define CCR_RTxC_XTAL 0x80
|
||||
|
||||
|
||||
/* WR14: DPLL_CTRL_REG "DCR" */
|
||||
|
||||
#define DCR_BRG_ENAB 0x01
|
||||
#define DCR_BRG_USE_PCLK 0x02
|
||||
#define DCR_DTRREQ_IS_REQ 0x04
|
||||
#define DCR_AUTO_ECHO 0x08
|
||||
#define DCR_LOCAL_LOOPBACK 0x10
|
||||
|
||||
#define DCR_DPLL_EDGE_SEARCH 0x20
|
||||
#define DCR_DPLL_ERR_RESET 0x40
|
||||
#define DCR_DPLL_DISAB 0x60
|
||||
#define DCR_DPLL_CLK_BRG 0x80
|
||||
#define DCR_DPLL_CLK_RTxC 0xa0
|
||||
#define DCR_DPLL_FM 0xc0
|
||||
#define DCR_DPLL_NRZI 0xe0
|
||||
|
||||
|
||||
/* WR15: INT_CTRL_REG "ICR" */
|
||||
|
||||
#define ICR_OPTIONREG_SELECT 0x01
|
||||
#define ICR_ENAB_BRG_ZERO_INT 0x02
|
||||
#define ICR_USE_FS_FIFO 0x04
|
||||
#define ICR_ENAB_DCD_INT 0x08
|
||||
#define ICR_ENAB_SYNC_INT 0x10
|
||||
#define ICR_ENAB_CTS_INT 0x20
|
||||
#define ICR_ENAB_UNDERRUN_INT 0x40
|
||||
#define ICR_ENAB_BREAK_INT 0x80
|
||||
|
||||
|
||||
/* RR0: STATUS_REG "SR" */
|
||||
|
||||
#define SR_CHAR_AVAIL 0x01
|
||||
#define SR_BRG_ZERO 0x02
|
||||
#define SR_TX_BUF_EMPTY 0x04
|
||||
#define SR_DCD 0x08
|
||||
#define SR_SYNC_ABORT 0x10
|
||||
#define SR_CTS 0x20
|
||||
#define SR_TX_UNDERRUN 0x40
|
||||
#define SR_BREAK 0x80
|
||||
|
||||
|
||||
/* RR1: SPCOND_STATUS_REG "SCSR" */
|
||||
|
||||
#define SCSR_ALL_SENT 0x01
|
||||
#define SCSR_RESIDUAL_MASK 0x0e
|
||||
#define SCSR_PARITY_ERR 0x10
|
||||
#define SCSR_RX_OVERRUN 0x20
|
||||
#define SCSR_CRC_FRAME_ERR 0x40
|
||||
#define SCSR_END_OF_FRAME 0x80
|
||||
|
||||
|
||||
/* RR3: INT_PENDING_REG "IPR" */
|
||||
|
||||
#define IPR_B_EXTSTAT 0x01
|
||||
#define IPR_B_TX 0x02
|
||||
#define IPR_B_RX 0x04
|
||||
#define IPR_A_EXTSTAT 0x08
|
||||
#define IPR_A_TX 0x10
|
||||
#define IPR_A_RX 0x20
|
||||
|
||||
|
||||
/* RR7: FS_FIFO_HIGH_REG "FFHR" */
|
||||
|
||||
#define FFHR_CNT_MASK 0x3f
|
||||
#define FFHR_IS_FROM_FIFO 0x40
|
||||
#define FFHR_FIFO_OVERRUN 0x80
|
||||
|
||||
|
||||
/* RR10: DPLL_STATUS_REG "DSR" */
|
||||
|
||||
#define DSR_ON_LOOP 0x02
|
||||
#define DSR_ON_LOOP_SENDING 0x10
|
||||
#define DSR_TWO_CLK_MISSING 0x40
|
||||
#define DSR_ONE_CLK_MISSING 0x80
|
||||
|
||||
/***********************************************************************/
|
||||
/* */
|
||||
/* Register Access */
|
||||
/* */
|
||||
/***********************************************************************/
|
||||
|
||||
|
||||
/* The SCC needs 3.5 PCLK cycles recovery time between to register
|
||||
* accesses. PCLK runs with 8 MHz on an Atari, so this delay is 3.5 *
|
||||
* 125 ns = 437.5 ns. This is too short for udelay().
|
||||
* 10/16/95: A tstb st_mfp.par_dt_reg takes 600ns (sure?) and thus should be
|
||||
* quite right
|
||||
*/
|
||||
|
||||
#define scc_reg_delay() \
|
||||
do { \
|
||||
if (MACH_IS_MVME16x || MACH_IS_BVME6000 || MACH_IS_MVME147) \
|
||||
__asm__ __volatile__ ( " nop; nop"); \
|
||||
else if (MACH_IS_ATARI) \
|
||||
__asm__ __volatile__ ( "tstb %0" : : "g" (*_scc_del) : "cc" );\
|
||||
} while (0)
|
||||
|
||||
static unsigned char scc_shadow[2][16];
|
||||
|
||||
/* The following functions should relax the somehow complicated
|
||||
* register access of the SCC. _SCCwrite() stores all written values
|
||||
* (except for WR0 and WR8) in shadow registers for later recall. This
|
||||
* removes the burden of remembering written values as needed. The
|
||||
* extra work of storing the value doesn't count, since a delay is
|
||||
* needed after a SCC access anyway. Additionally, _SCCwrite() manages
|
||||
* writes to WR0 and WR8 differently, because these can be accessed
|
||||
* directly with less overhead. Another special case are WR7 and WR7'.
|
||||
* _SCCwrite automatically checks what of this registers is selected
|
||||
* and changes b0 of WR15 if needed.
|
||||
*
|
||||
* _SCCread() for standard read registers is straightforward, except
|
||||
* for RR2 (split into two "virtual" registers: one for the value
|
||||
* written to WR2 (from the shadow) and one for the vector including
|
||||
* status from RR2, Ch. B) and RR3. The latter must be read from
|
||||
* Channel A, because it reads as all zeros on Ch. B. RR0 and RR8 can
|
||||
* be accessed directly as before.
|
||||
*
|
||||
* The two inline function contain complicated switch statements. But
|
||||
* I rely on regno and final_delay being constants, so gcc can reduce
|
||||
* the whole stuff to just some assembler statements.
|
||||
*
|
||||
* _SCCwrite and _SCCread aren't intended to be used directly under
|
||||
* normal circumstances. The macros SCCread[_ND] and SCCwrite[_ND] are
|
||||
* for that purpose. They assume that a local variable 'port' is
|
||||
* declared and pointing to the port's scc_struct entry. The
|
||||
* variants with "_NB" appended should be used if no other SCC
|
||||
* accesses follow immediately (within 0.5 usecs). They just skip the
|
||||
* final delay nops.
|
||||
*
|
||||
* Please note that accesses to SCC registers should only take place
|
||||
* when interrupts are turned off (at least if SCC interrupts are
|
||||
* enabled). Otherwise, an interrupt could interfere with the
|
||||
* two-stage accessing process.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
static __inline__ void _SCCwrite(
|
||||
struct scc_port *port,
|
||||
unsigned char *shadow,
|
||||
volatile unsigned char *_scc_del,
|
||||
int regno,
|
||||
unsigned char val, int final_delay )
|
||||
{
|
||||
switch( regno ) {
|
||||
|
||||
case COMMAND_REG:
|
||||
/* WR0 can be written directly without pointing */
|
||||
*port->ctrlp = val;
|
||||
break;
|
||||
|
||||
case SYNC_CHAR_REG:
|
||||
/* For WR7, first set b0 of WR15 to 0, if needed */
|
||||
if (shadow[INT_CTRL_REG] & ICR_OPTIONREG_SELECT) {
|
||||
*port->ctrlp = 15;
|
||||
shadow[INT_CTRL_REG] &= ~ICR_OPTIONREG_SELECT;
|
||||
scc_reg_delay();
|
||||
*port->ctrlp = shadow[INT_CTRL_REG];
|
||||
scc_reg_delay();
|
||||
}
|
||||
goto normal_case;
|
||||
|
||||
case SDLC_OPTION_REG:
|
||||
/* For WR7', first set b0 of WR15 to 1, if needed */
|
||||
if (!(shadow[INT_CTRL_REG] & ICR_OPTIONREG_SELECT)) {
|
||||
*port->ctrlp = 15;
|
||||
shadow[INT_CTRL_REG] |= ICR_OPTIONREG_SELECT;
|
||||
scc_reg_delay();
|
||||
*port->ctrlp = shadow[INT_CTRL_REG];
|
||||
scc_reg_delay();
|
||||
}
|
||||
*port->ctrlp = 7;
|
||||
shadow[8] = val; /* WR7' shadowed at WR8 */
|
||||
scc_reg_delay();
|
||||
*port->ctrlp = val;
|
||||
break;
|
||||
|
||||
case TX_DATA_REG: /* WR8 */
|
||||
/* TX_DATA_REG can be accessed directly on some h/w */
|
||||
if (MACH_IS_MVME16x || MACH_IS_BVME6000 || MACH_IS_MVME147)
|
||||
{
|
||||
*port->ctrlp = regno;
|
||||
scc_reg_delay();
|
||||
*port->ctrlp = val;
|
||||
}
|
||||
else
|
||||
*port->datap = val;
|
||||
break;
|
||||
|
||||
case MASTER_INT_CTRL:
|
||||
*port->ctrlp = regno;
|
||||
val &= 0x3f; /* bits 6..7 are the reset commands */
|
||||
scc_shadow[0][regno] = val;
|
||||
scc_reg_delay();
|
||||
*port->ctrlp = val;
|
||||
break;
|
||||
|
||||
case DPLL_CTRL_REG:
|
||||
*port->ctrlp = regno;
|
||||
val &= 0x1f; /* bits 5..7 are the DPLL commands */
|
||||
shadow[regno] = val;
|
||||
scc_reg_delay();
|
||||
*port->ctrlp = val;
|
||||
break;
|
||||
|
||||
case 1 ... 6:
|
||||
case 10 ... 13:
|
||||
case 15:
|
||||
normal_case:
|
||||
*port->ctrlp = regno;
|
||||
shadow[regno] = val;
|
||||
scc_reg_delay();
|
||||
*port->ctrlp = val;
|
||||
break;
|
||||
|
||||
default:
|
||||
printk( "Bad SCC write access to WR%d\n", regno );
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
if (final_delay)
|
||||
scc_reg_delay();
|
||||
}
|
||||
|
||||
|
||||
static __inline__ unsigned char _SCCread(
|
||||
struct scc_port *port,
|
||||
unsigned char *shadow,
|
||||
volatile unsigned char *_scc_del,
|
||||
int regno, int final_delay )
|
||||
{
|
||||
unsigned char rv;
|
||||
|
||||
switch( regno ) {
|
||||
|
||||
/* --- real read registers --- */
|
||||
case STATUS_REG:
|
||||
rv = *port->ctrlp;
|
||||
break;
|
||||
|
||||
case INT_PENDING_REG:
|
||||
/* RR3: read only from Channel A! */
|
||||
port = port->port_a;
|
||||
goto normal_case;
|
||||
|
||||
case RX_DATA_REG:
|
||||
/* RR8 can be accessed directly on some h/w */
|
||||
if (MACH_IS_MVME16x || MACH_IS_BVME6000 || MACH_IS_MVME147)
|
||||
{
|
||||
*port->ctrlp = 8;
|
||||
scc_reg_delay();
|
||||
rv = *port->ctrlp;
|
||||
}
|
||||
else
|
||||
rv = *port->datap;
|
||||
break;
|
||||
|
||||
case CURR_VECTOR_REG:
|
||||
/* RR2 (vector including status) from Ch. B */
|
||||
port = port->port_b;
|
||||
goto normal_case;
|
||||
|
||||
/* --- reading write registers: access the shadow --- */
|
||||
case 1 ... 7:
|
||||
case 10 ... 15:
|
||||
return shadow[regno]; /* no final delay! */
|
||||
|
||||
/* WR7' is special, because it is shadowed at the place of WR8 */
|
||||
case SDLC_OPTION_REG:
|
||||
return shadow[8]; /* no final delay! */
|
||||
|
||||
/* WR9 is special too, because it is common for both channels */
|
||||
case MASTER_INT_CTRL:
|
||||
return scc_shadow[0][9]; /* no final delay! */
|
||||
|
||||
default:
|
||||
printk( "Bad SCC read access to %cR%d\n", (regno & 16) ? 'R' : 'W',
|
||||
regno & ~16 );
|
||||
break;
|
||||
|
||||
case SPCOND_STATUS_REG:
|
||||
case FS_FIFO_LOW_REG:
|
||||
case FS_FIFO_HIGH_REG:
|
||||
case DPLL_STATUS_REG:
|
||||
normal_case:
|
||||
*port->ctrlp = regno & 0x0f;
|
||||
scc_reg_delay();
|
||||
rv = *port->ctrlp;
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
if (final_delay)
|
||||
scc_reg_delay();
|
||||
return rv;
|
||||
}
|
||||
|
||||
#define SCC_ACCESS_INIT(port) \
|
||||
unsigned char *_scc_shadow = &scc_shadow[port->channel][0]
|
||||
|
||||
#define SCCwrite(reg,val) _SCCwrite(port,_scc_shadow,scc_del,(reg),(val),1)
|
||||
#define SCCwrite_NB(reg,val) _SCCwrite(port,_scc_shadow,scc_del,(reg),(val),0)
|
||||
#define SCCread(reg) _SCCread(port,_scc_shadow,scc_del,(reg),1)
|
||||
#define SCCread_NB(reg) _SCCread(port,_scc_shadow,scc_del,(reg),0)
|
||||
|
||||
#define SCCmod(reg,and,or) SCCwrite((reg),(SCCread(reg)&(and))|(or))
|
||||
|
||||
#endif /* _SCC_H */
|
14
drivers/hv/Kconfig
Normal file
14
drivers/hv/Kconfig
Normal file
|
@ -0,0 +1,14 @@
|
|||
config HYPERV
|
||||
tristate "Microsoft Hyper-V client drivers"
|
||||
depends on X86 && ACPI && PCI
|
||||
help
|
||||
Select this option to run Linux as a Hyper-V client operating
|
||||
system.
|
||||
|
||||
config HYPERV_UTILS
|
||||
tristate "Microsoft Hyper-V Utilities driver"
|
||||
depends on HYPERV && CONNECTOR && NLS
|
||||
help
|
||||
Select this option to enable the Hyper-V Utilities.
|
||||
|
||||
|
7
drivers/hv/Makefile
Normal file
7
drivers/hv/Makefile
Normal file
|
@ -0,0 +1,7 @@
|
|||
obj-$(CONFIG_HYPERV) += hv_vmbus.o
|
||||
obj-$(CONFIG_HYPERV_UTILS) += hv_utils.o
|
||||
|
||||
hv_vmbus-y := vmbus_drv.o \
|
||||
hv.o connection.o channel.o \
|
||||
channel_mgmt.o ring_buffer.o
|
||||
hv_utils-y := hv_util.o hv_kvp.o
|
|
@ -26,8 +26,8 @@
|
|||
#include <linux/mm.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/hyperv.h>
|
||||
|
||||
#include "hyperv.h"
|
||||
#include "hyperv_vmbus.h"
|
||||
|
||||
#define NUM_PAGES_SPANNED(addr, len) \
|
||||
|
@ -76,15 +76,14 @@ void vmbus_get_debug_info(struct vmbus_channel *channel,
|
|||
struct hv_monitor_page *monitorpage;
|
||||
u8 monitor_group = (u8)channel->offermsg.monitorid / 32;
|
||||
u8 monitor_offset = (u8)channel->offermsg.monitorid % 32;
|
||||
/* u32 monitorBit = 1 << monitorOffset; */
|
||||
|
||||
debuginfo->relid = channel->offermsg.child_relid;
|
||||
debuginfo->state = channel->state;
|
||||
memcpy(&debuginfo->interfacetype,
|
||||
&channel->offermsg.offer.if_type, sizeof(struct hv_guid));
|
||||
&channel->offermsg.offer.if_type, sizeof(uuid_le));
|
||||
memcpy(&debuginfo->interface_instance,
|
||||
&channel->offermsg.offer.if_instance,
|
||||
sizeof(struct hv_guid));
|
||||
sizeof(uuid_le));
|
||||
|
||||
monitorpage = (struct hv_monitor_page *)vmbus_connection.monitor_pages;
|
||||
|
||||
|
@ -119,8 +118,8 @@ int vmbus_open(struct vmbus_channel *newchannel, u32 send_ringbuffer_size,
|
|||
u32 recv_ringbuffer_size, void *userdata, u32 userdatalen,
|
||||
void (*onchannelcallback)(void *context), void *context)
|
||||
{
|
||||
struct vmbus_channel_open_channel *openMsg;
|
||||
struct vmbus_channel_msginfo *openInfo = NULL;
|
||||
struct vmbus_channel_open_channel *open_msg;
|
||||
struct vmbus_channel_msginfo *open_info = NULL;
|
||||
void *in, *out;
|
||||
unsigned long flags;
|
||||
int ret, t, err = 0;
|
||||
|
@ -173,24 +172,24 @@ int vmbus_open(struct vmbus_channel *newchannel, u32 send_ringbuffer_size,
|
|||
}
|
||||
|
||||
/* Create and init the channel open message */
|
||||
openInfo = kmalloc(sizeof(*openInfo) +
|
||||
open_info = kmalloc(sizeof(*open_info) +
|
||||
sizeof(struct vmbus_channel_open_channel),
|
||||
GFP_KERNEL);
|
||||
if (!openInfo) {
|
||||
if (!open_info) {
|
||||
err = -ENOMEM;
|
||||
goto errorout;
|
||||
}
|
||||
|
||||
init_completion(&openInfo->waitevent);
|
||||
init_completion(&open_info->waitevent);
|
||||
|
||||
openMsg = (struct vmbus_channel_open_channel *)openInfo->msg;
|
||||
openMsg->header.msgtype = CHANNELMSG_OPENCHANNEL;
|
||||
openMsg->openid = newchannel->offermsg.child_relid;
|
||||
openMsg->child_relid = newchannel->offermsg.child_relid;
|
||||
openMsg->ringbuffer_gpadlhandle = newchannel->ringbuffer_gpadlhandle;
|
||||
openMsg->downstream_ringbuffer_pageoffset = send_ringbuffer_size >>
|
||||
open_msg = (struct vmbus_channel_open_channel *)open_info->msg;
|
||||
open_msg->header.msgtype = CHANNELMSG_OPENCHANNEL;
|
||||
open_msg->openid = newchannel->offermsg.child_relid;
|
||||
open_msg->child_relid = newchannel->offermsg.child_relid;
|
||||
open_msg->ringbuffer_gpadlhandle = newchannel->ringbuffer_gpadlhandle;
|
||||
open_msg->downstream_ringbuffer_pageoffset = send_ringbuffer_size >>
|
||||
PAGE_SHIFT;
|
||||
openMsg->server_contextarea_gpadlhandle = 0;
|
||||
open_msg->server_contextarea_gpadlhandle = 0;
|
||||
|
||||
if (userdatalen > MAX_USER_DEFINED_BYTES) {
|
||||
err = -EINVAL;
|
||||
|
@ -198,35 +197,35 @@ int vmbus_open(struct vmbus_channel *newchannel, u32 send_ringbuffer_size,
|
|||
}
|
||||
|
||||
if (userdatalen)
|
||||
memcpy(openMsg->userdata, userdata, userdatalen);
|
||||
memcpy(open_msg->userdata, userdata, userdatalen);
|
||||
|
||||
spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
|
||||
list_add_tail(&openInfo->msglistentry,
|
||||
list_add_tail(&open_info->msglistentry,
|
||||
&vmbus_connection.chn_msg_list);
|
||||
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
|
||||
|
||||
ret = vmbus_post_msg(openMsg,
|
||||
ret = vmbus_post_msg(open_msg,
|
||||
sizeof(struct vmbus_channel_open_channel));
|
||||
|
||||
if (ret != 0)
|
||||
goto cleanup;
|
||||
|
||||
t = wait_for_completion_timeout(&openInfo->waitevent, 5*HZ);
|
||||
t = wait_for_completion_timeout(&open_info->waitevent, 5*HZ);
|
||||
if (t == 0) {
|
||||
err = -ETIMEDOUT;
|
||||
goto errorout;
|
||||
}
|
||||
|
||||
|
||||
if (openInfo->response.open_result.status)
|
||||
err = openInfo->response.open_result.status;
|
||||
if (open_info->response.open_result.status)
|
||||
err = open_info->response.open_result.status;
|
||||
|
||||
cleanup:
|
||||
spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
|
||||
list_del(&openInfo->msglistentry);
|
||||
list_del(&open_info->msglistentry);
|
||||
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
|
||||
|
||||
kfree(openInfo);
|
||||
kfree(open_info);
|
||||
return err;
|
||||
|
||||
errorout:
|
||||
|
@ -234,56 +233,11 @@ errorout:
|
|||
hv_ringbuffer_cleanup(&newchannel->inbound);
|
||||
free_pages((unsigned long)out,
|
||||
get_order(send_ringbuffer_size + recv_ringbuffer_size));
|
||||
kfree(openInfo);
|
||||
kfree(open_info);
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(vmbus_open);
|
||||
|
||||
/*
|
||||
* dump_gpadl_body - Dump the gpadl body message to the console for
|
||||
* debugging purposes.
|
||||
*/
|
||||
static void dump_gpadl_body(struct vmbus_channel_gpadl_body *gpadl, u32 len)
|
||||
{
|
||||
int i;
|
||||
int pfncount;
|
||||
|
||||
pfncount = (len - sizeof(struct vmbus_channel_gpadl_body)) /
|
||||
sizeof(u64);
|
||||
|
||||
DPRINT_DBG(VMBUS, "gpadl body - len %d pfn count %d", len, pfncount);
|
||||
|
||||
for (i = 0; i < pfncount; i++)
|
||||
DPRINT_DBG(VMBUS, "gpadl body - %d) pfn %llu",
|
||||
i, gpadl->pfn[i]);
|
||||
}
|
||||
|
||||
/*
|
||||
* dump_gpadl_header - Dump the gpadl header message to the console for
|
||||
* debugging purposes.
|
||||
*/
|
||||
static void dump_gpadl_header(struct vmbus_channel_gpadl_header *gpadl)
|
||||
{
|
||||
int i, j;
|
||||
int pagecount;
|
||||
|
||||
DPRINT_DBG(VMBUS,
|
||||
"gpadl header - relid %d, range count %d, range buflen %d",
|
||||
gpadl->child_relid, gpadl->rangecount, gpadl->range_buflen);
|
||||
for (i = 0; i < gpadl->rangecount; i++) {
|
||||
pagecount = gpadl->range[i].byte_count >> PAGE_SHIFT;
|
||||
pagecount = (pagecount > 26) ? 26 : pagecount;
|
||||
|
||||
DPRINT_DBG(VMBUS, "gpadl range %d - len %d offset %d "
|
||||
"page count %d", i, gpadl->range[i].byte_count,
|
||||
gpadl->range[i].byte_offset, pagecount);
|
||||
|
||||
for (j = 0; j < pagecount; j++)
|
||||
DPRINT_DBG(VMBUS, "%d) pfn %llu", j,
|
||||
gpadl->range[i].pfn_array[j]);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* create_gpadl_header - Creates a gpadl for the specified buffer
|
||||
*/
|
||||
|
@ -437,7 +391,6 @@ int vmbus_establish_gpadl(struct vmbus_channel *channel, void *kbuffer,
|
|||
{
|
||||
struct vmbus_channel_gpadl_header *gpadlmsg;
|
||||
struct vmbus_channel_gpadl_body *gpadl_body;
|
||||
/* struct vmbus_channel_gpadl_created *gpadlCreated; */
|
||||
struct vmbus_channel_msginfo *msginfo = NULL;
|
||||
struct vmbus_channel_msginfo *submsginfo;
|
||||
u32 msgcount;
|
||||
|
@ -461,7 +414,6 @@ int vmbus_establish_gpadl(struct vmbus_channel *channel, void *kbuffer,
|
|||
gpadlmsg->child_relid = channel->offermsg.child_relid;
|
||||
gpadlmsg->gpadl = next_gpadl_handle;
|
||||
|
||||
dump_gpadl_header(gpadlmsg);
|
||||
|
||||
spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
|
||||
list_add_tail(&msginfo->msglistentry,
|
||||
|
@ -485,8 +437,6 @@ int vmbus_establish_gpadl(struct vmbus_channel *channel, void *kbuffer,
|
|||
CHANNELMSG_GPADL_BODY;
|
||||
gpadl_body->gpadl = next_gpadl_handle;
|
||||
|
||||
dump_gpadl_body(gpadl_body, submsginfo->msgsize -
|
||||
sizeof(*submsginfo));
|
||||
ret = vmbus_post_msg(gpadl_body,
|
||||
submsginfo->msgsize -
|
||||
sizeof(*submsginfo));
|
||||
|
@ -522,8 +472,6 @@ int vmbus_teardown_gpadl(struct vmbus_channel *channel, u32 gpadl_handle)
|
|||
unsigned long flags;
|
||||
int ret, t;
|
||||
|
||||
/* ASSERT(gpadl_handle != 0); */
|
||||
|
||||
info = kmalloc(sizeof(*info) +
|
||||
sizeof(struct vmbus_channel_gpadl_teardown), GFP_KERNEL);
|
||||
if (!info)
|
||||
|
@ -565,9 +513,12 @@ void vmbus_close(struct vmbus_channel *channel)
|
|||
{
|
||||
struct vmbus_channel_close_channel *msg;
|
||||
int ret;
|
||||
unsigned long flags;
|
||||
|
||||
/* Stop callback and cancel the timer asap */
|
||||
spin_lock_irqsave(&channel->inbound_lock, flags);
|
||||
channel->onchannel_callback = NULL;
|
||||
spin_unlock_irqrestore(&channel->inbound_lock, flags);
|
||||
|
||||
/* Send a closing message */
|
||||
|
||||
|
@ -787,19 +738,15 @@ int vmbus_recvpacket(struct vmbus_channel *channel, void *buffer,
|
|||
u32 packetlen;
|
||||
u32 userlen;
|
||||
int ret;
|
||||
unsigned long flags;
|
||||
|
||||
*buffer_actual_len = 0;
|
||||
*requestid = 0;
|
||||
|
||||
spin_lock_irqsave(&channel->inbound_lock, flags);
|
||||
|
||||
ret = hv_ringbuffer_peek(&channel->inbound, &desc,
|
||||
sizeof(struct vmpacket_descriptor));
|
||||
if (ret != 0) {
|
||||
spin_unlock_irqrestore(&channel->inbound_lock, flags);
|
||||
if (ret != 0)
|
||||
return 0;
|
||||
}
|
||||
|
||||
packetlen = desc.len8 << 3;
|
||||
userlen = packetlen - (desc.offset8 << 3);
|
||||
|
@ -807,7 +754,6 @@ int vmbus_recvpacket(struct vmbus_channel *channel, void *buffer,
|
|||
*buffer_actual_len = userlen;
|
||||
|
||||
if (userlen > bufferlen) {
|
||||
spin_unlock_irqrestore(&channel->inbound_lock, flags);
|
||||
|
||||
pr_err("Buffer too small - got %d needs %d\n",
|
||||
bufferlen, userlen);
|
||||
|
@ -820,7 +766,6 @@ int vmbus_recvpacket(struct vmbus_channel *channel, void *buffer,
|
|||
ret = hv_ringbuffer_read(&channel->inbound, buffer, userlen,
|
||||
(desc.offset8 << 3));
|
||||
|
||||
spin_unlock_irqrestore(&channel->inbound_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -837,19 +782,15 @@ int vmbus_recvpacket_raw(struct vmbus_channel *channel, void *buffer,
|
|||
u32 packetlen;
|
||||
u32 userlen;
|
||||
int ret;
|
||||
unsigned long flags;
|
||||
|
||||
*buffer_actual_len = 0;
|
||||
*requestid = 0;
|
||||
|
||||
spin_lock_irqsave(&channel->inbound_lock, flags);
|
||||
|
||||
ret = hv_ringbuffer_peek(&channel->inbound, &desc,
|
||||
sizeof(struct vmpacket_descriptor));
|
||||
if (ret != 0) {
|
||||
spin_unlock_irqrestore(&channel->inbound_lock, flags);
|
||||
if (ret != 0)
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
packetlen = desc.len8 << 3;
|
||||
|
@ -858,12 +799,10 @@ int vmbus_recvpacket_raw(struct vmbus_channel *channel, void *buffer,
|
|||
*buffer_actual_len = packetlen;
|
||||
|
||||
if (packetlen > bufferlen) {
|
||||
spin_unlock_irqrestore(&channel->inbound_lock, flags);
|
||||
|
||||
pr_err("Buffer too small - needed %d bytes but "
|
||||
"got space for only %d bytes\n",
|
||||
packetlen, bufferlen);
|
||||
return -2;
|
||||
return -ENOBUFS;
|
||||
}
|
||||
|
||||
*requestid = desc.trans_id;
|
||||
|
@ -871,7 +810,6 @@ int vmbus_recvpacket_raw(struct vmbus_channel *channel, void *buffer,
|
|||
/* Copy over the entire packet to the user buffer */
|
||||
ret = hv_ringbuffer_read(&channel->inbound, buffer, packetlen, 0);
|
||||
|
||||
spin_unlock_irqrestore(&channel->inbound_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(vmbus_recvpacket_raw);
|
|
@ -28,8 +28,8 @@
|
|||
#include <linux/list.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/completion.h>
|
||||
#include <linux/hyperv.h>
|
||||
|
||||
#include "hyperv.h"
|
||||
#include "hyperv_vmbus.h"
|
||||
|
||||
struct vmbus_channel_message_table_entry {
|
||||
|
@ -40,12 +40,12 @@ struct vmbus_channel_message_table_entry {
|
|||
#define MAX_MSG_TYPES 4
|
||||
#define MAX_NUM_DEVICE_CLASSES_SUPPORTED 8
|
||||
|
||||
static const struct hv_guid
|
||||
static const uuid_le
|
||||
supported_device_classes[MAX_NUM_DEVICE_CLASSES_SUPPORTED] = {
|
||||
/* {ba6163d9-04a1-4d29-b605-72e2ffb1dc7f} */
|
||||
/* Storage - SCSI */
|
||||
{
|
||||
.data = {
|
||||
.b = {
|
||||
0xd9, 0x63, 0x61, 0xba, 0xa1, 0x04, 0x29, 0x4d,
|
||||
0xb6, 0x05, 0x72, 0xe2, 0xff, 0xb1, 0xdc, 0x7f
|
||||
}
|
||||
|
@ -54,7 +54,7 @@ static const struct hv_guid
|
|||
/* {F8615163-DF3E-46c5-913F-F2D2F965ED0E} */
|
||||
/* Network */
|
||||
{
|
||||
.data = {
|
||||
.b = {
|
||||
0x63, 0x51, 0x61, 0xF8, 0x3E, 0xDF, 0xc5, 0x46,
|
||||
0x91, 0x3F, 0xF2, 0xD2, 0xF9, 0x65, 0xED, 0x0E
|
||||
}
|
||||
|
@ -63,7 +63,7 @@ static const struct hv_guid
|
|||
/* {CFA8B69E-5B4A-4cc0-B98B-8BA1A1F3F95A} */
|
||||
/* Input */
|
||||
{
|
||||
.data = {
|
||||
.b = {
|
||||
0x9E, 0xB6, 0xA8, 0xCF, 0x4A, 0x5B, 0xc0, 0x4c,
|
||||
0xB9, 0x8B, 0x8B, 0xA1, 0xA1, 0xF3, 0xF9, 0x5A
|
||||
}
|
||||
|
@ -72,7 +72,7 @@ static const struct hv_guid
|
|||
/* {32412632-86cb-44a2-9b5c-50d1417354f5} */
|
||||
/* IDE */
|
||||
{
|
||||
.data = {
|
||||
.b = {
|
||||
0x32, 0x26, 0x41, 0x32, 0xcb, 0x86, 0xa2, 0x44,
|
||||
0x9b, 0x5c, 0x50, 0xd1, 0x41, 0x73, 0x54, 0xf5
|
||||
}
|
||||
|
@ -80,7 +80,7 @@ static const struct hv_guid
|
|||
/* 0E0B6031-5213-4934-818B-38D90CED39DB */
|
||||
/* Shutdown */
|
||||
{
|
||||
.data = {
|
||||
.b = {
|
||||
0x31, 0x60, 0x0B, 0X0E, 0x13, 0x52, 0x34, 0x49,
|
||||
0x81, 0x8B, 0x38, 0XD9, 0x0C, 0xED, 0x39, 0xDB
|
||||
}
|
||||
|
@ -88,7 +88,7 @@ static const struct hv_guid
|
|||
/* {9527E630-D0AE-497b-ADCE-E80AB0175CAF} */
|
||||
/* TimeSync */
|
||||
{
|
||||
.data = {
|
||||
.b = {
|
||||
0x30, 0xe6, 0x27, 0x95, 0xae, 0xd0, 0x7b, 0x49,
|
||||
0xad, 0xce, 0xe8, 0x0a, 0xb0, 0x17, 0x5c, 0xaf
|
||||
}
|
||||
|
@ -96,7 +96,7 @@ static const struct hv_guid
|
|||
/* {57164f39-9115-4e78-ab55-382f3bd5422d} */
|
||||
/* Heartbeat */
|
||||
{
|
||||
.data = {
|
||||
.b = {
|
||||
0x39, 0x4f, 0x16, 0x57, 0x15, 0x91, 0x78, 0x4e,
|
||||
0xab, 0x55, 0x38, 0x2f, 0x3b, 0xd5, 0x42, 0x2d
|
||||
}
|
||||
|
@ -104,7 +104,7 @@ static const struct hv_guid
|
|||
/* {A9A0F4E7-5A45-4d96-B827-8A841E8C03E6} */
|
||||
/* KVP */
|
||||
{
|
||||
.data = {
|
||||
.b = {
|
||||
0xe7, 0xf4, 0xa0, 0xa9, 0x45, 0x5a, 0x96, 0x4d,
|
||||
0xb8, 0x27, 0x8a, 0x84, 0x1e, 0x8c, 0x3, 0xe6
|
||||
}
|
||||
|
@ -114,7 +114,7 @@ static const struct hv_guid
|
|||
|
||||
|
||||
/**
|
||||
* prep_negotiate_resp() - Create default response for Hyper-V Negotiate message
|
||||
* vmbus_prep_negotiate_resp() - Create default response for Hyper-V Negotiate message
|
||||
* @icmsghdrp: Pointer to msg header structure
|
||||
* @icmsg_negotiate: Pointer to negotiate message structure
|
||||
* @buf: Raw buffer channel data
|
||||
|
@ -128,9 +128,8 @@ static const struct hv_guid
|
|||
*
|
||||
* Mainly used by Hyper-V drivers.
|
||||
*/
|
||||
void prep_negotiate_resp(struct icmsg_hdr *icmsghdrp,
|
||||
struct icmsg_negotiate *negop,
|
||||
u8 *buf)
|
||||
void vmbus_prep_negotiate_resp(struct icmsg_hdr *icmsghdrp,
|
||||
struct icmsg_negotiate *negop, u8 *buf)
|
||||
{
|
||||
if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {
|
||||
icmsghdrp->icmsgsize = 0x10;
|
||||
|
@ -156,119 +155,7 @@ void prep_negotiate_resp(struct icmsg_hdr *icmsghdrp,
|
|||
negop->icmsg_vercnt = 1;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(prep_negotiate_resp);
|
||||
|
||||
/**
|
||||
* chn_cb_negotiate() - Default handler for non IDE/SCSI/NETWORK
|
||||
* Hyper-V requests
|
||||
* @context: Pointer to argument structure.
|
||||
*
|
||||
* Set up the default handler for non device driver specific requests
|
||||
* from Hyper-V. This stub responds to the default negotiate messages
|
||||
* that come in for every non IDE/SCSI/Network request.
|
||||
* This behavior is normally overwritten in the hv_utils driver. That
|
||||
* driver handles requests like graceful shutdown, heartbeats etc.
|
||||
*
|
||||
* Mainly used by Hyper-V drivers.
|
||||
*/
|
||||
void chn_cb_negotiate(void *context)
|
||||
{
|
||||
struct vmbus_channel *channel = context;
|
||||
u8 *buf;
|
||||
u32 buflen, recvlen;
|
||||
u64 requestid;
|
||||
|
||||
struct icmsg_hdr *icmsghdrp;
|
||||
struct icmsg_negotiate *negop = NULL;
|
||||
|
||||
if (channel->util_index >= 0) {
|
||||
/*
|
||||
* This is a properly initialized util channel.
|
||||
* Route this callback appropriately and setup state
|
||||
* so that we don't need to reroute again.
|
||||
*/
|
||||
if (hv_cb_utils[channel->util_index].callback != NULL) {
|
||||
/*
|
||||
* The util driver has established a handler for
|
||||
* this service; do the magic.
|
||||
*/
|
||||
channel->onchannel_callback =
|
||||
hv_cb_utils[channel->util_index].callback;
|
||||
(hv_cb_utils[channel->util_index].callback)(channel);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
buflen = PAGE_SIZE;
|
||||
buf = kmalloc(buflen, GFP_ATOMIC);
|
||||
|
||||
vmbus_recvpacket(channel, buf, buflen, &recvlen, &requestid);
|
||||
|
||||
if (recvlen > 0) {
|
||||
icmsghdrp = (struct icmsg_hdr *)&buf[
|
||||
sizeof(struct vmbuspipe_hdr)];
|
||||
|
||||
prep_negotiate_resp(icmsghdrp, negop, buf);
|
||||
|
||||
icmsghdrp->icflags = ICMSGHDRFLAG_TRANSACTION
|
||||
| ICMSGHDRFLAG_RESPONSE;
|
||||
|
||||
vmbus_sendpacket(channel, buf,
|
||||
recvlen, requestid,
|
||||
VM_PKT_DATA_INBAND, 0);
|
||||
}
|
||||
|
||||
kfree(buf);
|
||||
}
|
||||
EXPORT_SYMBOL(chn_cb_negotiate);
|
||||
|
||||
/*
|
||||
* Function table used for message responses for non IDE/SCSI/Network type
|
||||
* messages. (Such as KVP/Shutdown etc)
|
||||
*/
|
||||
struct hyperv_service_callback hv_cb_utils[MAX_MSG_TYPES] = {
|
||||
/* 0E0B6031-5213-4934-818B-38D90CED39DB */
|
||||
/* Shutdown */
|
||||
{
|
||||
.msg_type = HV_SHUTDOWN_MSG,
|
||||
.data = {
|
||||
0x31, 0x60, 0x0B, 0X0E, 0x13, 0x52, 0x34, 0x49,
|
||||
0x81, 0x8B, 0x38, 0XD9, 0x0C, 0xED, 0x39, 0xDB
|
||||
},
|
||||
.log_msg = "Shutdown channel functionality initialized"
|
||||
},
|
||||
|
||||
/* {9527E630-D0AE-497b-ADCE-E80AB0175CAF} */
|
||||
/* TimeSync */
|
||||
{
|
||||
.msg_type = HV_TIMESYNC_MSG,
|
||||
.data = {
|
||||
0x30, 0xe6, 0x27, 0x95, 0xae, 0xd0, 0x7b, 0x49,
|
||||
0xad, 0xce, 0xe8, 0x0a, 0xb0, 0x17, 0x5c, 0xaf
|
||||
},
|
||||
.log_msg = "Timesync channel functionality initialized"
|
||||
},
|
||||
/* {57164f39-9115-4e78-ab55-382f3bd5422d} */
|
||||
/* Heartbeat */
|
||||
{
|
||||
.msg_type = HV_HEARTBEAT_MSG,
|
||||
.data = {
|
||||
0x39, 0x4f, 0x16, 0x57, 0x15, 0x91, 0x78, 0x4e,
|
||||
0xab, 0x55, 0x38, 0x2f, 0x3b, 0xd5, 0x42, 0x2d
|
||||
},
|
||||
.log_msg = "Heartbeat channel functionality initialized"
|
||||
},
|
||||
/* {A9A0F4E7-5A45-4d96-B827-8A841E8C03E6} */
|
||||
/* KVP */
|
||||
{
|
||||
.data = {
|
||||
0xe7, 0xf4, 0xa0, 0xa9, 0x45, 0x5a, 0x96, 0x4d,
|
||||
0xb8, 0x27, 0x8a, 0x84, 0x1e, 0x8c, 0x3, 0xe6
|
||||
},
|
||||
.log_msg = "KVP channel functionality initialized"
|
||||
},
|
||||
};
|
||||
EXPORT_SYMBOL(hv_cb_utils);
|
||||
EXPORT_SYMBOL_GPL(vmbus_prep_negotiate_resp);
|
||||
|
||||
/*
|
||||
* alloc_channel - Allocate and initialize a vmbus channel object
|
||||
|
@ -309,7 +196,7 @@ static void release_channel(struct work_struct *work)
|
|||
/*
|
||||
* free_channel - Release the resources used by the vmbus channel object
|
||||
*/
|
||||
void free_channel(struct vmbus_channel *channel)
|
||||
static void free_channel(struct vmbus_channel *channel)
|
||||
{
|
||||
|
||||
/*
|
||||
|
@ -333,7 +220,7 @@ static void vmbus_process_rescind_offer(struct work_struct *work)
|
|||
struct vmbus_channel,
|
||||
work);
|
||||
|
||||
vmbus_child_device_unregister(channel->device_obj);
|
||||
vmbus_device_unregister(channel->device_obj);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -348,7 +235,6 @@ static void vmbus_process_offer(struct work_struct *work)
|
|||
struct vmbus_channel *channel;
|
||||
bool fnew = true;
|
||||
int ret;
|
||||
int cnt;
|
||||
unsigned long flags;
|
||||
|
||||
/* The next possible work is rescind handling */
|
||||
|
@ -358,12 +244,10 @@ static void vmbus_process_offer(struct work_struct *work)
|
|||
spin_lock_irqsave(&vmbus_connection.channel_lock, flags);
|
||||
|
||||
list_for_each_entry(channel, &vmbus_connection.chn_list, listentry) {
|
||||
if (!memcmp(&channel->offermsg.offer.if_type,
|
||||
&newchannel->offermsg.offer.if_type,
|
||||
sizeof(struct hv_guid)) &&
|
||||
!memcmp(&channel->offermsg.offer.if_instance,
|
||||
&newchannel->offermsg.offer.if_instance,
|
||||
sizeof(struct hv_guid))) {
|
||||
if (!uuid_le_cmp(channel->offermsg.offer.if_type,
|
||||
newchannel->offermsg.offer.if_type) &&
|
||||
!uuid_le_cmp(channel->offermsg.offer.if_instance,
|
||||
newchannel->offermsg.offer.if_instance)) {
|
||||
fnew = false;
|
||||
break;
|
||||
}
|
||||
|
@ -385,7 +269,7 @@ static void vmbus_process_offer(struct work_struct *work)
|
|||
* We need to set the DeviceObject field before calling
|
||||
* vmbus_child_dev_add()
|
||||
*/
|
||||
newchannel->device_obj = vmbus_child_device_create(
|
||||
newchannel->device_obj = vmbus_device_create(
|
||||
&newchannel->offermsg.offer.if_type,
|
||||
&newchannel->offermsg.offer.if_instance,
|
||||
newchannel);
|
||||
|
@ -395,7 +279,7 @@ static void vmbus_process_offer(struct work_struct *work)
|
|||
* binding which eventually invokes the device driver's AddDevice()
|
||||
* method.
|
||||
*/
|
||||
ret = vmbus_child_device_register(newchannel->device_obj);
|
||||
ret = vmbus_device_register(newchannel->device_obj);
|
||||
if (ret != 0) {
|
||||
pr_err("unable to add child device object (relid %d)\n",
|
||||
newchannel->offermsg.child_relid);
|
||||
|
@ -412,48 +296,26 @@ static void vmbus_process_offer(struct work_struct *work)
|
|||
* can cleanup properly
|
||||
*/
|
||||
newchannel->state = CHANNEL_OPEN_STATE;
|
||||
newchannel->util_index = -1; /* Invalid index */
|
||||
|
||||
/* Open IC channels */
|
||||
for (cnt = 0; cnt < MAX_MSG_TYPES; cnt++) {
|
||||
if (memcmp(&newchannel->offermsg.offer.if_type,
|
||||
&hv_cb_utils[cnt].data,
|
||||
sizeof(struct hv_guid)) == 0 &&
|
||||
vmbus_open(newchannel, 2 * PAGE_SIZE,
|
||||
2 * PAGE_SIZE, NULL, 0,
|
||||
chn_cb_negotiate,
|
||||
newchannel) == 0) {
|
||||
hv_cb_utils[cnt].channel = newchannel;
|
||||
newchannel->util_index = cnt;
|
||||
|
||||
pr_info("%s\n", hv_cb_utils[cnt].log_msg);
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* vmbus_onoffer - Handler for channel offers from vmbus in parent partition.
|
||||
*
|
||||
* We ignore all offers except network and storage offers. For each network and
|
||||
* storage offers, we create a channel object and queue a work item to the
|
||||
* channel object to process the offer synchronously
|
||||
*/
|
||||
static void vmbus_onoffer(struct vmbus_channel_message_header *hdr)
|
||||
{
|
||||
struct vmbus_channel_offer_channel *offer;
|
||||
struct vmbus_channel *newchannel;
|
||||
struct hv_guid *guidtype;
|
||||
struct hv_guid *guidinstance;
|
||||
uuid_le *guidtype;
|
||||
uuid_le *guidinstance;
|
||||
int i;
|
||||
int fsupported = 0;
|
||||
|
||||
offer = (struct vmbus_channel_offer_channel *)hdr;
|
||||
for (i = 0; i < MAX_NUM_DEVICE_CLASSES_SUPPORTED; i++) {
|
||||
if (memcmp(&offer->offer.if_type,
|
||||
&supported_device_classes[i],
|
||||
sizeof(struct hv_guid)) == 0) {
|
||||
if (!uuid_le_cmp(offer->offer.if_type,
|
||||
supported_device_classes[i])) {
|
||||
fsupported = 1;
|
||||
break;
|
||||
}
|
|
@ -25,11 +25,12 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/vmalloc.h>
|
||||
|
||||
#include "hyperv.h"
|
||||
#include <linux/hyperv.h>
|
||||
#include <asm/hyperv.h>
|
||||
#include "hyperv_vmbus.h"
|
||||
|
||||
|
||||
|
@ -49,10 +50,6 @@ int vmbus_connect(void)
|
|||
struct vmbus_channel_initiate_contact *msg;
|
||||
unsigned long flags;
|
||||
|
||||
/* Make sure we are not connecting or connected */
|
||||
if (vmbus_connection.conn_state != DISCONNECTED)
|
||||
return -EISCONN;
|
||||
|
||||
/* Initialize the vmbus connection */
|
||||
vmbus_connection.conn_state = CONNECTING;
|
||||
vmbus_connection.work_queue = create_workqueue("hv_vmbus_con");
|
||||
|
@ -214,8 +211,7 @@ struct vmbus_channel *relid2channel(u32 relid)
|
|||
static void process_chn_event(u32 relid)
|
||||
{
|
||||
struct vmbus_channel *channel;
|
||||
|
||||
/* ASSERT(relId > 0); */
|
||||
unsigned long flags;
|
||||
|
||||
/*
|
||||
* Find the channel based on this relid and invokes the
|
||||
|
@ -223,11 +219,27 @@ static void process_chn_event(u32 relid)
|
|||
*/
|
||||
channel = relid2channel(relid);
|
||||
|
||||
if (channel) {
|
||||
channel->onchannel_callback(channel->channel_callback_context);
|
||||
} else {
|
||||
if (!channel) {
|
||||
pr_err("channel not found for relid - %u\n", relid);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* A channel once created is persistent even when there
|
||||
* is no driver handling the device. An unloading driver
|
||||
* sets the onchannel_callback to NULL under the
|
||||
* protection of the channel inbound_lock. Thus, checking
|
||||
* and invoking the driver specific callback takes care of
|
||||
* orderly unloading of the driver.
|
||||
*/
|
||||
|
||||
spin_lock_irqsave(&channel->inbound_lock, flags);
|
||||
if (channel->onchannel_callback != NULL)
|
||||
channel->onchannel_callback(channel->channel_callback_context);
|
||||
else
|
||||
pr_err("no channel callback for relid - %u\n", relid);
|
||||
|
||||
spin_unlock_irqrestore(&channel->inbound_lock, flags);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -248,16 +260,17 @@ void vmbus_on_event(unsigned long data)
|
|||
if (!recv_int_page[dword])
|
||||
continue;
|
||||
for (bit = 0; bit < 32; bit++) {
|
||||
if (sync_test_and_clear_bit(bit, (unsigned long *)&recv_int_page[dword])) {
|
||||
if (sync_test_and_clear_bit(bit,
|
||||
(unsigned long *)&recv_int_page[dword])) {
|
||||
relid = (dword << 5) + bit;
|
||||
|
||||
if (relid == 0) {
|
||||
if (relid == 0)
|
||||
/*
|
||||
* Special case - vmbus
|
||||
* channel protocol msg
|
||||
*/
|
||||
continue;
|
||||
}
|
||||
|
||||
process_chn_event(relid);
|
||||
}
|
||||
}
|
||||
|
@ -270,10 +283,25 @@ void vmbus_on_event(unsigned long data)
|
|||
int vmbus_post_msg(void *buffer, size_t buflen)
|
||||
{
|
||||
union hv_connection_id conn_id;
|
||||
int ret = 0;
|
||||
int retries = 0;
|
||||
|
||||
conn_id.asu32 = 0;
|
||||
conn_id.u.id = VMBUS_MESSAGE_CONNECTION_ID;
|
||||
return hv_post_message(conn_id, 1, buffer, buflen);
|
||||
|
||||
/*
|
||||
* hv_post_message() can have transient failures because of
|
||||
* insufficient resources. Retry the operation a couple of
|
||||
* times before giving up.
|
||||
*/
|
||||
while (retries < 3) {
|
||||
ret = hv_post_message(conn_id, 1, buffer, buflen);
|
||||
if (ret != HV_STATUS_INSUFFICIENT_BUFFERS)
|
||||
return ret;
|
||||
retries++;
|
||||
msleep(100);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
|
@ -25,8 +25,8 @@
|
|||
#include <linux/mm.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/vmalloc.h>
|
||||
|
||||
#include "hyperv.h"
|
||||
#include <linux/hyperv.h>
|
||||
#include <asm/hyperv.h>
|
||||
#include "hyperv_vmbus.h"
|
||||
|
||||
/* The one and only */
|
||||
|
@ -111,7 +111,7 @@ static u64 do_hypercall(u64 control, void *input, void *output)
|
|||
u64 hv_status = 0;
|
||||
u64 input_address = (input) ? virt_to_phys(input) : 0;
|
||||
u64 output_address = (output) ? virt_to_phys(output) : 0;
|
||||
volatile void *hypercall_page = hv_context.hypercall_page;
|
||||
void *hypercall_page = hv_context.hypercall_page;
|
||||
|
||||
__asm__ __volatile__("mov %0, %%r8" : : "r" (output_address) : "r8");
|
||||
__asm__ __volatile__("call *%3" : "=a" (hv_status) :
|
||||
|
@ -132,7 +132,7 @@ static u64 do_hypercall(u64 control, void *input, void *output)
|
|||
u64 output_address = (output) ? virt_to_phys(output) : 0;
|
||||
u32 output_address_hi = output_address >> 32;
|
||||
u32 output_address_lo = output_address & 0xFFFFFFFF;
|
||||
volatile void *hypercall_page = hv_context.hypercall_page;
|
||||
void *hypercall_page = hv_context.hypercall_page;
|
||||
|
||||
__asm__ __volatile__ ("call *%8" : "=d"(hv_status_hi),
|
||||
"=a"(hv_status_lo) : "d" (control_hi),
|
||||
|
@ -151,7 +151,6 @@ static u64 do_hypercall(u64 control, void *input, void *output)
|
|||
*/
|
||||
int hv_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
int max_leaf;
|
||||
union hv_x64_msr_hypercall_contents hypercall_msr;
|
||||
void *virtaddr = NULL;
|
||||
|
@ -164,11 +163,7 @@ int hv_init(void)
|
|||
goto cleanup;
|
||||
|
||||
max_leaf = query_hypervisor_info();
|
||||
/* HvQueryHypervisorFeatures(maxLeaf); */
|
||||
|
||||
/*
|
||||
* We only support running on top of Hyper-V
|
||||
*/
|
||||
rdmsrl(HV_X64_MSR_GUEST_OS_ID, hv_context.guestid);
|
||||
|
||||
if (hv_context.guestid != 0)
|
||||
|
@ -181,10 +176,6 @@ int hv_init(void)
|
|||
/* See if the hypercall page is already set */
|
||||
rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
|
||||
|
||||
/*
|
||||
* Allocate the hypercall page memory
|
||||
* virtaddr = osd_page_alloc(1);
|
||||
*/
|
||||
virtaddr = __vmalloc(PAGE_SIZE, GFP_KERNEL, PAGE_KERNEL_EXEC);
|
||||
|
||||
if (!virtaddr)
|
||||
|
@ -222,7 +213,7 @@ int hv_init(void)
|
|||
hv_context.signal_event_param->flag_number = 0;
|
||||
hv_context.signal_event_param->rsvdz = 0;
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
|
||||
cleanup:
|
||||
if (virtaddr) {
|
||||
|
@ -233,8 +224,8 @@ cleanup:
|
|||
|
||||
vfree(virtaddr);
|
||||
}
|
||||
ret = -1;
|
||||
return ret;
|
||||
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -378,7 +369,7 @@ void hv_synic_init(void *irqarg)
|
|||
shared_sint.as_uint64 = 0;
|
||||
shared_sint.vector = irq_vector; /* HV_SHARED_SINT_IDT_VECTOR + 0x20; */
|
||||
shared_sint.masked = false;
|
||||
shared_sint.auto_eoi = true;
|
||||
shared_sint.auto_eoi = false;
|
||||
|
||||
wrmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
|
||||
|
|
@ -26,8 +26,8 @@
|
|||
#include <linux/nls.h>
|
||||
#include <linux/connector.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/hyperv.h>
|
||||
|
||||
#include "hyperv.h"
|
||||
#include "hv_kvp.h"
|
||||
|
||||
|
||||
|
@ -44,21 +44,24 @@
|
|||
static struct {
|
||||
bool active; /* transaction status - active or not */
|
||||
int recv_len; /* number of bytes received. */
|
||||
int index; /* current index */
|
||||
struct vmbus_channel *recv_channel; /* chn we got the request */
|
||||
u64 recv_req_id; /* request ID. */
|
||||
} kvp_transaction;
|
||||
|
||||
static int kvp_send_key(int index);
|
||||
static void kvp_send_key(struct work_struct *dummy);
|
||||
|
||||
#define TIMEOUT_FIRED 1
|
||||
|
||||
static void kvp_respond_to_host(char *key, char *value, int error);
|
||||
static void kvp_work_func(struct work_struct *dummy);
|
||||
static void kvp_register(void);
|
||||
|
||||
static DECLARE_DELAYED_WORK(kvp_work, kvp_work_func);
|
||||
static DECLARE_WORK(kvp_sendkey_work, kvp_send_key);
|
||||
|
||||
static struct cb_id kvp_id = { CN_KVP_IDX, CN_KVP_VAL };
|
||||
static const char kvp_name[] = "kvp_kernel_module";
|
||||
static int timeout_fired;
|
||||
static u8 *recv_buffer;
|
||||
/*
|
||||
* Register the kernel component with the user-level daemon.
|
||||
|
@ -90,8 +93,7 @@ kvp_work_func(struct work_struct *dummy)
|
|||
* If the timer fires, the user-mode component has not responded;
|
||||
* process the pending transaction.
|
||||
*/
|
||||
kvp_respond_to_host("Unknown key", "Guest timed out", timeout_fired);
|
||||
timeout_fired = 1;
|
||||
kvp_respond_to_host("Unknown key", "Guest timed out", TIMEOUT_FIRED);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -121,10 +123,11 @@ kvp_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp)
|
|||
}
|
||||
}
|
||||
|
||||
static int
|
||||
kvp_send_key(int index)
|
||||
static void
|
||||
kvp_send_key(struct work_struct *dummy)
|
||||
{
|
||||
struct cn_msg *msg;
|
||||
int index = kvp_transaction.index;
|
||||
|
||||
msg = kzalloc(sizeof(*msg) + sizeof(struct hv_kvp_msg) , GFP_ATOMIC);
|
||||
|
||||
|
@ -136,9 +139,8 @@ kvp_send_key(int index)
|
|||
msg->len = sizeof(struct hv_ku_msg);
|
||||
cn_netlink_send(msg, 0, GFP_ATOMIC);
|
||||
kfree(msg);
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -177,6 +179,15 @@ kvp_respond_to_host(char *key, char *value, int error)
|
|||
channel = kvp_transaction.recv_channel;
|
||||
req_id = kvp_transaction.recv_req_id;
|
||||
|
||||
kvp_transaction.active = false;
|
||||
|
||||
if (channel->onchannel_callback == NULL)
|
||||
/*
|
||||
* We have raced with util driver being unloaded;
|
||||
* silently return.
|
||||
*/
|
||||
return;
|
||||
|
||||
icmsghdrp = (struct icmsg_hdr *)
|
||||
&recv_buffer[sizeof(struct vmbuspipe_hdr)];
|
||||
kvp_msg = (struct hv_kvp_msg *)
|
||||
|
@ -217,7 +228,6 @@ response_done:
|
|||
vmbus_sendpacket(channel, recv_buffer, buf_len, req_id,
|
||||
VM_PKT_DATA_INBAND, 0);
|
||||
|
||||
kvp_transaction.active = false;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -243,10 +253,6 @@ void hv_kvp_onchannelcallback(void *context)
|
|||
struct icmsg_negotiate *negop = NULL;
|
||||
|
||||
|
||||
if (kvp_transaction.active)
|
||||
return;
|
||||
|
||||
|
||||
vmbus_recvpacket(channel, recv_buffer, PAGE_SIZE, &recvlen, &requestid);
|
||||
|
||||
if (recvlen > 0) {
|
||||
|
@ -254,7 +260,7 @@ void hv_kvp_onchannelcallback(void *context)
|
|||
sizeof(struct vmbuspipe_hdr)];
|
||||
|
||||
if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {
|
||||
prep_negotiate_resp(icmsghdrp, negop, recv_buffer);
|
||||
vmbus_prep_negotiate_resp(icmsghdrp, negop, recv_buffer);
|
||||
} else {
|
||||
kvp_msg = (struct hv_kvp_msg *)&recv_buffer[
|
||||
sizeof(struct vmbuspipe_hdr) +
|
||||
|
@ -282,6 +288,7 @@ void hv_kvp_onchannelcallback(void *context)
|
|||
kvp_transaction.recv_channel = channel;
|
||||
kvp_transaction.recv_req_id = requestid;
|
||||
kvp_transaction.active = true;
|
||||
kvp_transaction.index = kvp_data->index;
|
||||
|
||||
/*
|
||||
* Get the information from the
|
||||
|
@ -292,8 +299,8 @@ void hv_kvp_onchannelcallback(void *context)
|
|||
* Set a timeout to deal with
|
||||
* user-mode not responding.
|
||||
*/
|
||||
kvp_send_key(kvp_data->index);
|
||||
schedule_delayed_work(&kvp_work, 100);
|
||||
schedule_work(&kvp_sendkey_work);
|
||||
schedule_delayed_work(&kvp_work, 5*HZ);
|
||||
|
||||
return;
|
||||
|
||||
|
@ -312,16 +319,14 @@ callback_done:
|
|||
}
|
||||
|
||||
int
|
||||
hv_kvp_init(void)
|
||||
hv_kvp_init(struct hv_util_service *srv)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = cn_add_callback(&kvp_id, kvp_name, kvp_cn_callback);
|
||||
if (err)
|
||||
return err;
|
||||
recv_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL);
|
||||
if (!recv_buffer)
|
||||
return -ENOMEM;
|
||||
recv_buffer = srv->recv_buffer;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -330,5 +335,5 @@ void hv_kvp_deinit(void)
|
|||
{
|
||||
cn_del_callback(&kvp_id);
|
||||
cancel_delayed_work_sync(&kvp_work);
|
||||
kfree(recv_buffer);
|
||||
cancel_work_sync(&kvp_sendkey_work);
|
||||
}
|
|
@ -175,7 +175,7 @@ struct hv_kvp_msg {
|
|||
struct hv_kvp_msg_enumerate kvp_data;
|
||||
};
|
||||
|
||||
int hv_kvp_init(void);
|
||||
int hv_kvp_init(struct hv_util_service *);
|
||||
void hv_kvp_deinit(void);
|
||||
void hv_kvp_onchannelcallback(void *);
|
||||
|
|
@ -26,15 +26,31 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/sysctl.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/dmi.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/hyperv.h>
|
||||
|
||||
#include "hyperv.h"
|
||||
#include "hv_kvp.h"
|
||||
|
||||
static u8 *shut_txf_buf;
|
||||
static u8 *time_txf_buf;
|
||||
static u8 *hbeat_txf_buf;
|
||||
|
||||
static void shutdown_onchannelcallback(void *context);
|
||||
static struct hv_util_service util_shutdown = {
|
||||
.util_cb = shutdown_onchannelcallback,
|
||||
};
|
||||
|
||||
static void timesync_onchannelcallback(void *context);
|
||||
static struct hv_util_service util_timesynch = {
|
||||
.util_cb = timesync_onchannelcallback,
|
||||
};
|
||||
|
||||
static void heartbeat_onchannelcallback(void *context);
|
||||
static struct hv_util_service util_heartbeat = {
|
||||
.util_cb = heartbeat_onchannelcallback,
|
||||
};
|
||||
|
||||
static struct hv_util_service util_kvp = {
|
||||
.util_cb = hv_kvp_onchannelcallback,
|
||||
.util_init = hv_kvp_init,
|
||||
.util_deinit = hv_kvp_deinit,
|
||||
};
|
||||
|
||||
static void shutdown_onchannelcallback(void *context)
|
||||
{
|
||||
|
@ -42,6 +58,7 @@ static void shutdown_onchannelcallback(void *context)
|
|||
u32 recvlen;
|
||||
u64 requestid;
|
||||
u8 execute_shutdown = false;
|
||||
u8 *shut_txf_buf = util_shutdown.recv_buffer;
|
||||
|
||||
struct shutdown_msg_data *shutdown_msg;
|
||||
|
||||
|
@ -56,7 +73,7 @@ static void shutdown_onchannelcallback(void *context)
|
|||
sizeof(struct vmbuspipe_hdr)];
|
||||
|
||||
if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {
|
||||
prep_negotiate_resp(icmsghdrp, negop, shut_txf_buf);
|
||||
vmbus_prep_negotiate_resp(icmsghdrp, negop, shut_txf_buf);
|
||||
} else {
|
||||
shutdown_msg =
|
||||
(struct shutdown_msg_data *)&shut_txf_buf[
|
||||
|
@ -91,7 +108,7 @@ static void shutdown_onchannelcallback(void *context)
|
|||
}
|
||||
|
||||
if (execute_shutdown == true)
|
||||
orderly_poweroff(false);
|
||||
orderly_poweroff(true);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -108,6 +125,24 @@ static inline void do_adj_guesttime(u64 hosttime)
|
|||
do_settimeofday(&host_ts);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the host time in a process context.
|
||||
*/
|
||||
|
||||
struct adj_time_work {
|
||||
struct work_struct work;
|
||||
u64 host_time;
|
||||
};
|
||||
|
||||
static void hv_set_host_time(struct work_struct *work)
|
||||
{
|
||||
struct adj_time_work *wrk;
|
||||
|
||||
wrk = container_of(work, struct adj_time_work, work);
|
||||
do_adj_guesttime(wrk->host_time);
|
||||
kfree(wrk);
|
||||
}
|
||||
|
||||
/*
|
||||
* Synchronize time with host after reboot, restore, etc.
|
||||
*
|
||||
|
@ -121,17 +156,26 @@ static inline void do_adj_guesttime(u64 hosttime)
|
|||
*/
|
||||
static inline void adj_guesttime(u64 hosttime, u8 flags)
|
||||
{
|
||||
struct adj_time_work *wrk;
|
||||
static s32 scnt = 50;
|
||||
|
||||
wrk = kmalloc(sizeof(struct adj_time_work), GFP_ATOMIC);
|
||||
if (wrk == NULL)
|
||||
return;
|
||||
|
||||
wrk->host_time = hosttime;
|
||||
if ((flags & ICTIMESYNCFLAG_SYNC) != 0) {
|
||||
do_adj_guesttime(hosttime);
|
||||
INIT_WORK(&wrk->work, hv_set_host_time);
|
||||
schedule_work(&wrk->work);
|
||||
return;
|
||||
}
|
||||
|
||||
if ((flags & ICTIMESYNCFLAG_SAMPLE) != 0 && scnt > 0) {
|
||||
scnt--;
|
||||
do_adj_guesttime(hosttime);
|
||||
}
|
||||
INIT_WORK(&wrk->work, hv_set_host_time);
|
||||
schedule_work(&wrk->work);
|
||||
} else
|
||||
kfree(wrk);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -144,6 +188,7 @@ static void timesync_onchannelcallback(void *context)
|
|||
u64 requestid;
|
||||
struct icmsg_hdr *icmsghdrp;
|
||||
struct ictimesync_data *timedatap;
|
||||
u8 *time_txf_buf = util_timesynch.recv_buffer;
|
||||
|
||||
vmbus_recvpacket(channel, time_txf_buf,
|
||||
PAGE_SIZE, &recvlen, &requestid);
|
||||
|
@ -153,7 +198,7 @@ static void timesync_onchannelcallback(void *context)
|
|||
sizeof(struct vmbuspipe_hdr)];
|
||||
|
||||
if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {
|
||||
prep_negotiate_resp(icmsghdrp, NULL, time_txf_buf);
|
||||
vmbus_prep_negotiate_resp(icmsghdrp, NULL, time_txf_buf);
|
||||
} else {
|
||||
timedatap = (struct ictimesync_data *)&time_txf_buf[
|
||||
sizeof(struct vmbuspipe_hdr) +
|
||||
|
@ -182,6 +227,7 @@ static void heartbeat_onchannelcallback(void *context)
|
|||
u64 requestid;
|
||||
struct icmsg_hdr *icmsghdrp;
|
||||
struct heartbeat_msg_data *heartbeat_msg;
|
||||
u8 *hbeat_txf_buf = util_heartbeat.recv_buffer;
|
||||
|
||||
vmbus_recvpacket(channel, hbeat_txf_buf,
|
||||
PAGE_SIZE, &recvlen, &requestid);
|
||||
|
@ -191,7 +237,7 @@ static void heartbeat_onchannelcallback(void *context)
|
|||
sizeof(struct vmbuspipe_hdr)];
|
||||
|
||||
if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {
|
||||
prep_negotiate_resp(icmsghdrp, NULL, hbeat_txf_buf);
|
||||
vmbus_prep_negotiate_resp(icmsghdrp, NULL, hbeat_txf_buf);
|
||||
} else {
|
||||
heartbeat_msg =
|
||||
(struct heartbeat_msg_data *)&hbeat_txf_buf[
|
||||
|
@ -210,92 +256,94 @@ static void heartbeat_onchannelcallback(void *context)
|
|||
}
|
||||
}
|
||||
|
||||
static const struct pci_device_id __initconst
|
||||
hv_utils_pci_table[] __maybe_unused = {
|
||||
{ PCI_DEVICE(0x1414, 0x5353) }, /* Hyper-V emulated VGA controller */
|
||||
{ 0 }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, hv_utils_pci_table);
|
||||
static int util_probe(struct hv_device *dev,
|
||||
const struct hv_vmbus_device_id *dev_id)
|
||||
{
|
||||
struct hv_util_service *srv =
|
||||
(struct hv_util_service *)dev_id->driver_data;
|
||||
int ret;
|
||||
|
||||
srv->recv_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL);
|
||||
if (!srv->recv_buffer)
|
||||
return -ENOMEM;
|
||||
if (srv->util_init) {
|
||||
ret = srv->util_init(srv);
|
||||
if (ret) {
|
||||
ret = -ENODEV;
|
||||
goto error1;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct dmi_system_id __initconst
|
||||
hv_utils_dmi_table[] __maybe_unused = {
|
||||
{
|
||||
.ident = "Hyper-V",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
|
||||
DMI_MATCH(DMI_BOARD_NAME, "Virtual Machine"),
|
||||
},
|
||||
},
|
||||
ret = vmbus_open(dev->channel, 2 * PAGE_SIZE, 2 * PAGE_SIZE, NULL, 0,
|
||||
srv->util_cb, dev->channel);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
hv_set_drvdata(dev, srv);
|
||||
return 0;
|
||||
|
||||
error:
|
||||
if (srv->util_deinit)
|
||||
srv->util_deinit();
|
||||
error1:
|
||||
kfree(srv->recv_buffer);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int util_remove(struct hv_device *dev)
|
||||
{
|
||||
struct hv_util_service *srv = hv_get_drvdata(dev);
|
||||
|
||||
vmbus_close(dev->channel);
|
||||
if (srv->util_deinit)
|
||||
srv->util_deinit();
|
||||
kfree(srv->recv_buffer);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct hv_vmbus_device_id id_table[] = {
|
||||
/* Shutdown guid */
|
||||
{ VMBUS_DEVICE(0x31, 0x60, 0x0B, 0X0E, 0x13, 0x52, 0x34, 0x49,
|
||||
0x81, 0x8B, 0x38, 0XD9, 0x0C, 0xED, 0x39, 0xDB)
|
||||
.driver_data = (unsigned long)&util_shutdown },
|
||||
/* Time synch guid */
|
||||
{ VMBUS_DEVICE(0x30, 0xe6, 0x27, 0x95, 0xae, 0xd0, 0x7b, 0x49,
|
||||
0xad, 0xce, 0xe8, 0x0a, 0xb0, 0x17, 0x5c, 0xaf)
|
||||
.driver_data = (unsigned long)&util_timesynch },
|
||||
/* Heartbeat guid */
|
||||
{ VMBUS_DEVICE(0x39, 0x4f, 0x16, 0x57, 0x15, 0x91, 0x78, 0x4e,
|
||||
0xab, 0x55, 0x38, 0x2f, 0x3b, 0xd5, 0x42, 0x2d)
|
||||
.driver_data = (unsigned long)&util_heartbeat },
|
||||
/* KVP guid */
|
||||
{ VMBUS_DEVICE(0xe7, 0xf4, 0xa0, 0xa9, 0x45, 0x5a, 0x96, 0x4d,
|
||||
0xb8, 0x27, 0x8a, 0x84, 0x1e, 0x8c, 0x3, 0xe6)
|
||||
.driver_data = (unsigned long)&util_kvp },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(dmi, hv_utils_dmi_table);
|
||||
|
||||
MODULE_DEVICE_TABLE(vmbus, id_table);
|
||||
|
||||
/* The one and only one */
|
||||
static struct hv_driver util_drv = {
|
||||
.name = "hv_util",
|
||||
.id_table = id_table,
|
||||
.probe = util_probe,
|
||||
.remove = util_remove,
|
||||
};
|
||||
|
||||
static int __init init_hyperv_utils(void)
|
||||
{
|
||||
pr_info("Registering HyperV Utility Driver\n");
|
||||
|
||||
if (hv_kvp_init())
|
||||
return -ENODEV;
|
||||
|
||||
|
||||
if (!dmi_check_system(hv_utils_dmi_table))
|
||||
return -ENODEV;
|
||||
|
||||
shut_txf_buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
|
||||
time_txf_buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
|
||||
hbeat_txf_buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
|
||||
|
||||
if (!shut_txf_buf || !time_txf_buf || !hbeat_txf_buf) {
|
||||
pr_info("Unable to allocate memory for receive buffer\n");
|
||||
kfree(shut_txf_buf);
|
||||
kfree(time_txf_buf);
|
||||
kfree(hbeat_txf_buf);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
hv_cb_utils[HV_SHUTDOWN_MSG].callback = &shutdown_onchannelcallback;
|
||||
|
||||
hv_cb_utils[HV_TIMESYNC_MSG].callback = ×ync_onchannelcallback;
|
||||
|
||||
hv_cb_utils[HV_HEARTBEAT_MSG].callback = &heartbeat_onchannelcallback;
|
||||
|
||||
hv_cb_utils[HV_KVP_MSG].callback = &hv_kvp_onchannelcallback;
|
||||
|
||||
return 0;
|
||||
return vmbus_driver_register(&util_drv);
|
||||
}
|
||||
|
||||
static void exit_hyperv_utils(void)
|
||||
{
|
||||
pr_info("De-Registered HyperV Utility Driver\n");
|
||||
|
||||
if (hv_cb_utils[HV_SHUTDOWN_MSG].channel != NULL)
|
||||
hv_cb_utils[HV_SHUTDOWN_MSG].channel->onchannel_callback =
|
||||
&chn_cb_negotiate;
|
||||
hv_cb_utils[HV_SHUTDOWN_MSG].callback = NULL;
|
||||
|
||||
if (hv_cb_utils[HV_TIMESYNC_MSG].channel != NULL)
|
||||
hv_cb_utils[HV_TIMESYNC_MSG].channel->onchannel_callback =
|
||||
&chn_cb_negotiate;
|
||||
hv_cb_utils[HV_TIMESYNC_MSG].callback = NULL;
|
||||
|
||||
if (hv_cb_utils[HV_HEARTBEAT_MSG].channel != NULL)
|
||||
hv_cb_utils[HV_HEARTBEAT_MSG].channel->onchannel_callback =
|
||||
&chn_cb_negotiate;
|
||||
hv_cb_utils[HV_HEARTBEAT_MSG].callback = NULL;
|
||||
|
||||
if (hv_cb_utils[HV_KVP_MSG].channel != NULL)
|
||||
hv_cb_utils[HV_KVP_MSG].channel->onchannel_callback =
|
||||
&chn_cb_negotiate;
|
||||
hv_cb_utils[HV_KVP_MSG].callback = NULL;
|
||||
|
||||
hv_kvp_deinit();
|
||||
|
||||
kfree(shut_txf_buf);
|
||||
kfree(time_txf_buf);
|
||||
kfree(hbeat_txf_buf);
|
||||
vmbus_driver_unregister(&util_drv);
|
||||
}
|
||||
|
||||
module_init(init_hyperv_utils);
|
|
@ -28,8 +28,7 @@
|
|||
#include <linux/list.h>
|
||||
#include <asm/sync_bitops.h>
|
||||
#include <linux/atomic.h>
|
||||
|
||||
#include "hyperv.h"
|
||||
#include <linux/hyperv.h>
|
||||
|
||||
/*
|
||||
* The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
|
||||
|
@ -451,8 +450,8 @@ enum {
|
|||
/* #define VMBUS_PORT_ID 11 */
|
||||
|
||||
/* 628180B8-308D-4c5e-B7DB-1BEB62E62EF4 */
|
||||
static const struct hv_guid VMBUS_SERVICE_ID = {
|
||||
.data = {
|
||||
static const uuid_le VMBUS_SERVICE_ID = {
|
||||
.b = {
|
||||
0xb8, 0x80, 0x81, 0x62, 0x8d, 0x30, 0x5e, 0x4c,
|
||||
0xb7, 0xdb, 0x1b, 0xeb, 0x62, 0xe6, 0x2e, 0xf4
|
||||
},
|
||||
|
@ -530,8 +529,6 @@ int hv_ringbuffer_read(struct hv_ring_buffer_info *ring_info,
|
|||
|
||||
u32 hv_get_ringbuffer_interrupt_mask(struct hv_ring_buffer_info *ring_info);
|
||||
|
||||
void hv_dump_ring_info(struct hv_ring_buffer_info *ring_info, char *prefix);
|
||||
|
||||
void hv_ringbuffer_get_debuginfo(struct hv_ring_buffer_info *ring_info,
|
||||
struct hv_ring_buffer_debug_info *debug_info);
|
||||
|
||||
|
@ -601,12 +598,12 @@ extern struct vmbus_connection vmbus_connection;
|
|||
|
||||
/* General vmbus interface */
|
||||
|
||||
struct hv_device *vmbus_child_device_create(struct hv_guid *type,
|
||||
struct hv_guid *instance,
|
||||
struct hv_device *vmbus_device_create(uuid_le *type,
|
||||
uuid_le *instance,
|
||||
struct vmbus_channel *channel);
|
||||
|
||||
int vmbus_child_device_register(struct hv_device *child_device_obj);
|
||||
void vmbus_child_device_unregister(struct hv_device *device_obj);
|
||||
int vmbus_device_register(struct hv_device *child_device_obj);
|
||||
void vmbus_device_unregister(struct hv_device *device_obj);
|
||||
|
||||
/* static void */
|
||||
/* VmbusChildDeviceDestroy( */
|
|
@ -25,8 +25,8 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/hyperv.h>
|
||||
|
||||
#include "hyperv.h"
|
||||
#include "hyperv_vmbus.h"
|
||||
|
||||
|
||||
|
@ -34,7 +34,8 @@
|
|||
|
||||
|
||||
/* Amount of space to write to */
|
||||
#define BYTES_AVAIL_TO_WRITE(r, w, z) ((w) >= (r)) ? ((z) - ((w) - (r))) : ((r) - (w))
|
||||
#define BYTES_AVAIL_TO_WRITE(r, w, z) \
|
||||
((w) >= (r)) ? ((z) - ((w) - (r))) : ((r) - (w))
|
||||
|
||||
|
||||
/*
|
||||
|
@ -171,37 +172,6 @@ hv_get_ring_bufferindices(struct hv_ring_buffer_info *ring_info)
|
|||
return (u64)ring_info->ring_buffer->write_index << 32;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
*
|
||||
* hv_dump_ring_info()
|
||||
*
|
||||
* Dump out to console the ring buffer info
|
||||
*
|
||||
*/
|
||||
void hv_dump_ring_info(struct hv_ring_buffer_info *ring_info, char *prefix)
|
||||
{
|
||||
u32 bytes_avail_towrite;
|
||||
u32 bytes_avail_toread;
|
||||
|
||||
hv_get_ringbuffer_availbytes(ring_info,
|
||||
&bytes_avail_toread,
|
||||
&bytes_avail_towrite);
|
||||
|
||||
DPRINT(VMBUS,
|
||||
DEBUG_RING_LVL,
|
||||
"%s <<ringinfo %p buffer %p avail write %u "
|
||||
"avail read %u read idx %u write idx %u>>",
|
||||
prefix,
|
||||
ring_info,
|
||||
ring_info->ring_buffer->buffer,
|
||||
bytes_avail_towrite,
|
||||
bytes_avail_toread,
|
||||
ring_info->ring_buffer->read_index,
|
||||
ring_info->ring_buffer->write_index);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
*
|
||||
* hv_copyfrom_ringbuffer()
|
||||
|
@ -390,7 +360,7 @@ int hv_ringbuffer_write(struct hv_ring_buffer_info *outring_info,
|
|||
/* is empty since the read index == write index */
|
||||
if (bytes_avail_towrite <= totalbytes_towrite) {
|
||||
spin_unlock_irqrestore(&outring_info->ring_lock, flags);
|
||||
return -1;
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
/* Write to the ring buffer */
|
||||
|
@ -450,7 +420,7 @@ int hv_ringbuffer_peek(struct hv_ring_buffer_info *Inring_info,
|
|||
|
||||
spin_unlock_irqrestore(&Inring_info->ring_lock, flags);
|
||||
|
||||
return -1;
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
/* Convert to byte offset */
|
||||
|
@ -496,7 +466,7 @@ int hv_ringbuffer_read(struct hv_ring_buffer_info *inring_info, void *buffer,
|
|||
if (bytes_avail_toread < buflen) {
|
||||
spin_unlock_irqrestore(&inring_info->ring_lock, flags);
|
||||
|
||||
return -1;
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
next_read_location =
|
|
@ -28,14 +28,12 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/sysctl.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/dmi.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/acpi.h>
|
||||
#include <acpi/acpi_bus.h>
|
||||
#include <linux/completion.h>
|
||||
|
||||
#include "hyperv.h"
|
||||
#include <linux/hyperv.h>
|
||||
#include <asm/hyperv.h>
|
||||
#include "hyperv_vmbus.h"
|
||||
|
||||
|
||||
|
@ -43,15 +41,28 @@ static struct acpi_device *hv_acpi_dev;
|
|||
|
||||
static struct tasklet_struct msg_dpc;
|
||||
static struct tasklet_struct event_dpc;
|
||||
|
||||
unsigned int vmbus_loglevel = (ALL_MODULES << 16 | INFO_LVL);
|
||||
EXPORT_SYMBOL(vmbus_loglevel);
|
||||
/* (ALL_MODULES << 16 | DEBUG_LVL_ENTEREXIT); */
|
||||
/* (((VMBUS | VMBUS_DRV)<<16) | DEBUG_LVL_ENTEREXIT); */
|
||||
|
||||
static struct completion probe_event;
|
||||
static int irq;
|
||||
|
||||
struct hv_device_info {
|
||||
u32 chn_id;
|
||||
u32 chn_state;
|
||||
uuid_le chn_type;
|
||||
uuid_le chn_instance;
|
||||
|
||||
u32 monitor_id;
|
||||
u32 server_monitor_pending;
|
||||
u32 server_monitor_latency;
|
||||
u32 server_monitor_conn_id;
|
||||
u32 client_monitor_pending;
|
||||
u32 client_monitor_latency;
|
||||
u32 client_monitor_conn_id;
|
||||
|
||||
struct hv_dev_port_info inbound;
|
||||
struct hv_dev_port_info outbound;
|
||||
};
|
||||
|
||||
|
||||
static void get_channel_info(struct hv_device *device,
|
||||
struct hv_device_info *info)
|
||||
{
|
||||
|
@ -65,9 +76,9 @@ static void get_channel_info(struct hv_device *device,
|
|||
info->chn_id = debug_info.relid;
|
||||
info->chn_state = debug_info.state;
|
||||
memcpy(&info->chn_type, &debug_info.interfacetype,
|
||||
sizeof(struct hv_guid));
|
||||
sizeof(uuid_le));
|
||||
memcpy(&info->chn_instance, &debug_info.interface_instance,
|
||||
sizeof(struct hv_guid));
|
||||
sizeof(uuid_le));
|
||||
|
||||
info->monitor_id = debug_info.monitorid;
|
||||
|
||||
|
@ -97,6 +108,14 @@ static void get_channel_info(struct hv_device *device,
|
|||
debug_info.outbound.bytes_avail_towrite;
|
||||
}
|
||||
|
||||
#define VMBUS_ALIAS_LEN ((sizeof((struct hv_vmbus_device_id *)0)->guid) * 2)
|
||||
static void print_alias_name(struct hv_device *hv_dev, char *alias_name)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < VMBUS_ALIAS_LEN; i += 2)
|
||||
sprintf(&alias_name[i], "%02x", hv_dev->dev_type.b[i/2]);
|
||||
}
|
||||
|
||||
/*
|
||||
* vmbus_show_device_attr - Show the device attribute in sysfs.
|
||||
*
|
||||
|
@ -108,97 +127,105 @@ static ssize_t vmbus_show_device_attr(struct device *dev,
|
|||
char *buf)
|
||||
{
|
||||
struct hv_device *hv_dev = device_to_hv_device(dev);
|
||||
struct hv_device_info device_info;
|
||||
struct hv_device_info *device_info;
|
||||
char alias_name[VMBUS_ALIAS_LEN + 1];
|
||||
int ret = 0;
|
||||
|
||||
memset(&device_info, 0, sizeof(struct hv_device_info));
|
||||
device_info = kzalloc(sizeof(struct hv_device_info), GFP_KERNEL);
|
||||
if (!device_info)
|
||||
return ret;
|
||||
|
||||
get_channel_info(hv_dev, &device_info);
|
||||
get_channel_info(hv_dev, device_info);
|
||||
|
||||
if (!strcmp(dev_attr->attr.name, "class_id")) {
|
||||
return sprintf(buf, "{%02x%02x%02x%02x-%02x%02x-%02x%02x-"
|
||||
ret = sprintf(buf, "{%02x%02x%02x%02x-%02x%02x-%02x%02x-"
|
||||
"%02x%02x%02x%02x%02x%02x%02x%02x}\n",
|
||||
device_info.chn_type.data[3],
|
||||
device_info.chn_type.data[2],
|
||||
device_info.chn_type.data[1],
|
||||
device_info.chn_type.data[0],
|
||||
device_info.chn_type.data[5],
|
||||
device_info.chn_type.data[4],
|
||||
device_info.chn_type.data[7],
|
||||
device_info.chn_type.data[6],
|
||||
device_info.chn_type.data[8],
|
||||
device_info.chn_type.data[9],
|
||||
device_info.chn_type.data[10],
|
||||
device_info.chn_type.data[11],
|
||||
device_info.chn_type.data[12],
|
||||
device_info.chn_type.data[13],
|
||||
device_info.chn_type.data[14],
|
||||
device_info.chn_type.data[15]);
|
||||
device_info->chn_type.b[3],
|
||||
device_info->chn_type.b[2],
|
||||
device_info->chn_type.b[1],
|
||||
device_info->chn_type.b[0],
|
||||
device_info->chn_type.b[5],
|
||||
device_info->chn_type.b[4],
|
||||
device_info->chn_type.b[7],
|
||||
device_info->chn_type.b[6],
|
||||
device_info->chn_type.b[8],
|
||||
device_info->chn_type.b[9],
|
||||
device_info->chn_type.b[10],
|
||||
device_info->chn_type.b[11],
|
||||
device_info->chn_type.b[12],
|
||||
device_info->chn_type.b[13],
|
||||
device_info->chn_type.b[14],
|
||||
device_info->chn_type.b[15]);
|
||||
} else if (!strcmp(dev_attr->attr.name, "device_id")) {
|
||||
return sprintf(buf, "{%02x%02x%02x%02x-%02x%02x-%02x%02x-"
|
||||
ret = sprintf(buf, "{%02x%02x%02x%02x-%02x%02x-%02x%02x-"
|
||||
"%02x%02x%02x%02x%02x%02x%02x%02x}\n",
|
||||
device_info.chn_instance.data[3],
|
||||
device_info.chn_instance.data[2],
|
||||
device_info.chn_instance.data[1],
|
||||
device_info.chn_instance.data[0],
|
||||
device_info.chn_instance.data[5],
|
||||
device_info.chn_instance.data[4],
|
||||
device_info.chn_instance.data[7],
|
||||
device_info.chn_instance.data[6],
|
||||
device_info.chn_instance.data[8],
|
||||
device_info.chn_instance.data[9],
|
||||
device_info.chn_instance.data[10],
|
||||
device_info.chn_instance.data[11],
|
||||
device_info.chn_instance.data[12],
|
||||
device_info.chn_instance.data[13],
|
||||
device_info.chn_instance.data[14],
|
||||
device_info.chn_instance.data[15]);
|
||||
device_info->chn_instance.b[3],
|
||||
device_info->chn_instance.b[2],
|
||||
device_info->chn_instance.b[1],
|
||||
device_info->chn_instance.b[0],
|
||||
device_info->chn_instance.b[5],
|
||||
device_info->chn_instance.b[4],
|
||||
device_info->chn_instance.b[7],
|
||||
device_info->chn_instance.b[6],
|
||||
device_info->chn_instance.b[8],
|
||||
device_info->chn_instance.b[9],
|
||||
device_info->chn_instance.b[10],
|
||||
device_info->chn_instance.b[11],
|
||||
device_info->chn_instance.b[12],
|
||||
device_info->chn_instance.b[13],
|
||||
device_info->chn_instance.b[14],
|
||||
device_info->chn_instance.b[15]);
|
||||
} else if (!strcmp(dev_attr->attr.name, "modalias")) {
|
||||
print_alias_name(hv_dev, alias_name);
|
||||
ret = sprintf(buf, "vmbus:%s\n", alias_name);
|
||||
} else if (!strcmp(dev_attr->attr.name, "state")) {
|
||||
return sprintf(buf, "%d\n", device_info.chn_state);
|
||||
ret = sprintf(buf, "%d\n", device_info->chn_state);
|
||||
} else if (!strcmp(dev_attr->attr.name, "id")) {
|
||||
return sprintf(buf, "%d\n", device_info.chn_id);
|
||||
ret = sprintf(buf, "%d\n", device_info->chn_id);
|
||||
} else if (!strcmp(dev_attr->attr.name, "out_intr_mask")) {
|
||||
return sprintf(buf, "%d\n", device_info.outbound.int_mask);
|
||||
ret = sprintf(buf, "%d\n", device_info->outbound.int_mask);
|
||||
} else if (!strcmp(dev_attr->attr.name, "out_read_index")) {
|
||||
return sprintf(buf, "%d\n", device_info.outbound.read_idx);
|
||||
ret = sprintf(buf, "%d\n", device_info->outbound.read_idx);
|
||||
} else if (!strcmp(dev_attr->attr.name, "out_write_index")) {
|
||||
return sprintf(buf, "%d\n", device_info.outbound.write_idx);
|
||||
ret = sprintf(buf, "%d\n", device_info->outbound.write_idx);
|
||||
} else if (!strcmp(dev_attr->attr.name, "out_read_bytes_avail")) {
|
||||
return sprintf(buf, "%d\n",
|
||||
device_info.outbound.bytes_avail_toread);
|
||||
ret = sprintf(buf, "%d\n",
|
||||
device_info->outbound.bytes_avail_toread);
|
||||
} else if (!strcmp(dev_attr->attr.name, "out_write_bytes_avail")) {
|
||||
return sprintf(buf, "%d\n",
|
||||
device_info.outbound.bytes_avail_towrite);
|
||||
ret = sprintf(buf, "%d\n",
|
||||
device_info->outbound.bytes_avail_towrite);
|
||||
} else if (!strcmp(dev_attr->attr.name, "in_intr_mask")) {
|
||||
return sprintf(buf, "%d\n", device_info.inbound.int_mask);
|
||||
ret = sprintf(buf, "%d\n", device_info->inbound.int_mask);
|
||||
} else if (!strcmp(dev_attr->attr.name, "in_read_index")) {
|
||||
return sprintf(buf, "%d\n", device_info.inbound.read_idx);
|
||||
ret = sprintf(buf, "%d\n", device_info->inbound.read_idx);
|
||||
} else if (!strcmp(dev_attr->attr.name, "in_write_index")) {
|
||||
return sprintf(buf, "%d\n", device_info.inbound.write_idx);
|
||||
ret = sprintf(buf, "%d\n", device_info->inbound.write_idx);
|
||||
} else if (!strcmp(dev_attr->attr.name, "in_read_bytes_avail")) {
|
||||
return sprintf(buf, "%d\n",
|
||||
device_info.inbound.bytes_avail_toread);
|
||||
ret = sprintf(buf, "%d\n",
|
||||
device_info->inbound.bytes_avail_toread);
|
||||
} else if (!strcmp(dev_attr->attr.name, "in_write_bytes_avail")) {
|
||||
return sprintf(buf, "%d\n",
|
||||
device_info.inbound.bytes_avail_towrite);
|
||||
ret = sprintf(buf, "%d\n",
|
||||
device_info->inbound.bytes_avail_towrite);
|
||||
} else if (!strcmp(dev_attr->attr.name, "monitor_id")) {
|
||||
return sprintf(buf, "%d\n", device_info.monitor_id);
|
||||
ret = sprintf(buf, "%d\n", device_info->monitor_id);
|
||||
} else if (!strcmp(dev_attr->attr.name, "server_monitor_pending")) {
|
||||
return sprintf(buf, "%d\n", device_info.server_monitor_pending);
|
||||
ret = sprintf(buf, "%d\n", device_info->server_monitor_pending);
|
||||
} else if (!strcmp(dev_attr->attr.name, "server_monitor_latency")) {
|
||||
return sprintf(buf, "%d\n", device_info.server_monitor_latency);
|
||||
ret = sprintf(buf, "%d\n", device_info->server_monitor_latency);
|
||||
} else if (!strcmp(dev_attr->attr.name, "server_monitor_conn_id")) {
|
||||
return sprintf(buf, "%d\n",
|
||||
device_info.server_monitor_conn_id);
|
||||
ret = sprintf(buf, "%d\n",
|
||||
device_info->server_monitor_conn_id);
|
||||
} else if (!strcmp(dev_attr->attr.name, "client_monitor_pending")) {
|
||||
return sprintf(buf, "%d\n", device_info.client_monitor_pending);
|
||||
ret = sprintf(buf, "%d\n", device_info->client_monitor_pending);
|
||||
} else if (!strcmp(dev_attr->attr.name, "client_monitor_latency")) {
|
||||
return sprintf(buf, "%d\n", device_info.client_monitor_latency);
|
||||
ret = sprintf(buf, "%d\n", device_info->client_monitor_latency);
|
||||
} else if (!strcmp(dev_attr->attr.name, "client_monitor_conn_id")) {
|
||||
return sprintf(buf, "%d\n",
|
||||
device_info.client_monitor_conn_id);
|
||||
} else {
|
||||
return 0;
|
||||
ret = sprintf(buf, "%d\n",
|
||||
device_info->client_monitor_conn_id);
|
||||
}
|
||||
|
||||
kfree(device_info);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Set up per device attributes in /sys/bus/vmbus/devices/<bus device> */
|
||||
|
@ -208,6 +235,7 @@ static struct device_attribute vmbus_device_attrs[] = {
|
|||
__ATTR(class_id, S_IRUGO, vmbus_show_device_attr, NULL),
|
||||
__ATTR(device_id, S_IRUGO, vmbus_show_device_attr, NULL),
|
||||
__ATTR(monitor_id, S_IRUGO, vmbus_show_device_attr, NULL),
|
||||
__ATTR(modalias, S_IRUGO, vmbus_show_device_attr, NULL),
|
||||
|
||||
__ATTR(server_monitor_pending, S_IRUGO, vmbus_show_device_attr, NULL),
|
||||
__ATTR(server_monitor_latency, S_IRUGO, vmbus_show_device_attr, NULL),
|
||||
|
@ -238,76 +266,60 @@ static struct device_attribute vmbus_device_attrs[] = {
|
|||
* This routine is invoked when a device is added or removed on the vmbus to
|
||||
* generate a uevent to udev in the userspace. The udev will then look at its
|
||||
* rule and the uevent generated here to load the appropriate driver
|
||||
*
|
||||
* The alias string will be of the form vmbus:guid where guid is the string
|
||||
* representation of the device guid (each byte of the guid will be
|
||||
* represented with two hex characters.
|
||||
*/
|
||||
static int vmbus_uevent(struct device *device, struct kobj_uevent_env *env)
|
||||
{
|
||||
struct hv_device *dev = device_to_hv_device(device);
|
||||
int ret;
|
||||
char alias_name[VMBUS_ALIAS_LEN + 1];
|
||||
|
||||
ret = add_uevent_var(env, "VMBUS_DEVICE_CLASS_GUID={"
|
||||
"%02x%02x%02x%02x-%02x%02x-%02x%02x-"
|
||||
"%02x%02x%02x%02x%02x%02x%02x%02x}",
|
||||
dev->dev_type.data[3],
|
||||
dev->dev_type.data[2],
|
||||
dev->dev_type.data[1],
|
||||
dev->dev_type.data[0],
|
||||
dev->dev_type.data[5],
|
||||
dev->dev_type.data[4],
|
||||
dev->dev_type.data[7],
|
||||
dev->dev_type.data[6],
|
||||
dev->dev_type.data[8],
|
||||
dev->dev_type.data[9],
|
||||
dev->dev_type.data[10],
|
||||
dev->dev_type.data[11],
|
||||
dev->dev_type.data[12],
|
||||
dev->dev_type.data[13],
|
||||
dev->dev_type.data[14],
|
||||
dev->dev_type.data[15]);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = add_uevent_var(env, "VMBUS_DEVICE_DEVICE_GUID={"
|
||||
"%02x%02x%02x%02x-%02x%02x-%02x%02x-"
|
||||
"%02x%02x%02x%02x%02x%02x%02x%02x}",
|
||||
dev->dev_instance.data[3],
|
||||
dev->dev_instance.data[2],
|
||||
dev->dev_instance.data[1],
|
||||
dev->dev_instance.data[0],
|
||||
dev->dev_instance.data[5],
|
||||
dev->dev_instance.data[4],
|
||||
dev->dev_instance.data[7],
|
||||
dev->dev_instance.data[6],
|
||||
dev->dev_instance.data[8],
|
||||
dev->dev_instance.data[9],
|
||||
dev->dev_instance.data[10],
|
||||
dev->dev_instance.data[11],
|
||||
dev->dev_instance.data[12],
|
||||
dev->dev_instance.data[13],
|
||||
dev->dev_instance.data[14],
|
||||
dev->dev_instance.data[15]);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
print_alias_name(dev, alias_name);
|
||||
ret = add_uevent_var(env, "MODALIAS=vmbus:%s", alias_name);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static uuid_le null_guid;
|
||||
|
||||
static inline bool is_null_guid(const __u8 *guid)
|
||||
{
|
||||
if (memcmp(guid, &null_guid, sizeof(uuid_le)))
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return a matching hv_vmbus_device_id pointer.
|
||||
* If there is no match, return NULL.
|
||||
*/
|
||||
static const struct hv_vmbus_device_id *hv_vmbus_get_id(
|
||||
const struct hv_vmbus_device_id *id,
|
||||
__u8 *guid)
|
||||
{
|
||||
for (; !is_null_guid(id->guid); id++)
|
||||
if (!memcmp(&id->guid, guid, sizeof(uuid_le)))
|
||||
return id;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* vmbus_match - Attempt to match the specified device to the specified driver
|
||||
*/
|
||||
static int vmbus_match(struct device *device, struct device_driver *driver)
|
||||
{
|
||||
int match = 0;
|
||||
struct hv_driver *drv = drv_to_hv_drv(driver);
|
||||
struct hv_device *hv_dev = device_to_hv_device(device);
|
||||
|
||||
/* We found our driver ? */
|
||||
if (memcmp(&hv_dev->dev_type, &drv->dev_type,
|
||||
sizeof(struct hv_guid)) == 0)
|
||||
match = 1;
|
||||
if (hv_vmbus_get_id(drv->id_table, hv_dev->dev_type.b))
|
||||
return 1;
|
||||
|
||||
return match;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -319,9 +331,11 @@ static int vmbus_probe(struct device *child_device)
|
|||
struct hv_driver *drv =
|
||||
drv_to_hv_drv(child_device->driver);
|
||||
struct hv_device *dev = device_to_hv_device(child_device);
|
||||
const struct hv_vmbus_device_id *dev_id;
|
||||
|
||||
dev_id = hv_vmbus_get_id(drv->id_table, dev->dev_type.b);
|
||||
if (drv->probe) {
|
||||
ret = drv->probe(dev);
|
||||
ret = drv->probe(dev, dev_id);
|
||||
if (ret != 0)
|
||||
pr_err("probe failed for device %s (%d)\n",
|
||||
dev_name(child_device), ret);
|
||||
|
@ -339,22 +353,14 @@ static int vmbus_probe(struct device *child_device)
|
|||
*/
|
||||
static int vmbus_remove(struct device *child_device)
|
||||
{
|
||||
int ret;
|
||||
struct hv_driver *drv;
|
||||
|
||||
struct hv_driver *drv = drv_to_hv_drv(child_device->driver);
|
||||
struct hv_device *dev = device_to_hv_device(child_device);
|
||||
|
||||
if (child_device->driver) {
|
||||
drv = drv_to_hv_drv(child_device->driver);
|
||||
|
||||
if (drv->remove) {
|
||||
ret = drv->remove(dev);
|
||||
} else {
|
||||
pr_err("remove not set for driver %s\n",
|
||||
dev_name(child_device));
|
||||
ret = -ENODEV;
|
||||
}
|
||||
}
|
||||
if (drv->remove)
|
||||
drv->remove(dev);
|
||||
else
|
||||
pr_err("remove not set for driver %s\n",
|
||||
dev_name(child_device));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -422,9 +428,6 @@ static void vmbus_onmessage_work(struct work_struct *work)
|
|||
kfree(ctx);
|
||||
}
|
||||
|
||||
/*
|
||||
* vmbus_on_msg_dpc - DPC routine to handle messages from the hypervisior
|
||||
*/
|
||||
static void vmbus_on_msg_dpc(unsigned long data)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
|
@ -468,53 +471,42 @@ static void vmbus_on_msg_dpc(unsigned long data)
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* vmbus_on_isr - ISR routine
|
||||
*/
|
||||
static int vmbus_on_isr(void)
|
||||
static irqreturn_t vmbus_isr(int irq, void *dev_id)
|
||||
{
|
||||
int ret = 0;
|
||||
int cpu = smp_processor_id();
|
||||
void *page_addr;
|
||||
struct hv_message *msg;
|
||||
union hv_synic_event_flags *event;
|
||||
bool handled = false;
|
||||
|
||||
page_addr = hv_context.synic_message_page[cpu];
|
||||
msg = (struct hv_message *)page_addr + VMBUS_MESSAGE_SINT;
|
||||
|
||||
/* Check if there are actual msgs to be process */
|
||||
if (msg->header.message_type != HVMSG_NONE)
|
||||
ret |= 0x1;
|
||||
/*
|
||||
* Check for events before checking for messages. This is the order
|
||||
* in which events and messages are checked in Windows guests on
|
||||
* Hyper-V, and the Windows team suggested we do the same.
|
||||
*/
|
||||
|
||||
page_addr = hv_context.synic_event_page[cpu];
|
||||
event = (union hv_synic_event_flags *)page_addr + VMBUS_MESSAGE_SINT;
|
||||
|
||||
/* Since we are a child, we only need to check bit 0 */
|
||||
if (sync_test_and_clear_bit(0, (unsigned long *) &event->flags32[0]))
|
||||
ret |= 0x2;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static irqreturn_t vmbus_isr(int irq, void *dev_id)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = vmbus_on_isr();
|
||||
|
||||
/* Schedules a dpc if necessary */
|
||||
if (ret > 0) {
|
||||
if (test_bit(0, (unsigned long *)&ret))
|
||||
tasklet_schedule(&msg_dpc);
|
||||
|
||||
if (test_bit(1, (unsigned long *)&ret))
|
||||
tasklet_schedule(&event_dpc);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
} else {
|
||||
return IRQ_NONE;
|
||||
if (sync_test_and_clear_bit(0, (unsigned long *) &event->flags32[0])) {
|
||||
handled = true;
|
||||
tasklet_schedule(&event_dpc);
|
||||
}
|
||||
|
||||
page_addr = hv_context.synic_message_page[cpu];
|
||||
msg = (struct hv_message *)page_addr + VMBUS_MESSAGE_SINT;
|
||||
|
||||
/* Check if there are actual msgs to be processed */
|
||||
if (msg->header.message_type != HVMSG_NONE) {
|
||||
handled = true;
|
||||
tasklet_schedule(&msg_dpc);
|
||||
}
|
||||
|
||||
if (handled)
|
||||
return IRQ_HANDLED;
|
||||
else
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -538,26 +530,20 @@ static int vmbus_bus_init(int irq)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/* Initialize the bus context */
|
||||
tasklet_init(&msg_dpc, vmbus_on_msg_dpc, 0);
|
||||
tasklet_init(&event_dpc, vmbus_on_event, 0);
|
||||
|
||||
/* Now, register the bus with LDM */
|
||||
ret = bus_register(&hv_bus);
|
||||
if (ret)
|
||||
return ret;
|
||||
goto err_cleanup;
|
||||
|
||||
/* Get the interrupt resource */
|
||||
ret = request_irq(irq, vmbus_isr, IRQF_SAMPLE_RANDOM,
|
||||
driver_name, hv_acpi_dev);
|
||||
|
||||
if (ret != 0) {
|
||||
pr_err("Unable to request IRQ %d\n",
|
||||
irq);
|
||||
|
||||
bus_unregister(&hv_bus);
|
||||
|
||||
return ret;
|
||||
goto err_unregister;
|
||||
}
|
||||
|
||||
vector = IRQ0_VECTOR + irq;
|
||||
|
@ -568,76 +554,81 @@ static int vmbus_bus_init(int irq)
|
|||
*/
|
||||
on_each_cpu(hv_synic_init, (void *)&vector, 1);
|
||||
ret = vmbus_connect();
|
||||
if (ret) {
|
||||
free_irq(irq, hv_acpi_dev);
|
||||
bus_unregister(&hv_bus);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (ret)
|
||||
goto err_irq;
|
||||
|
||||
vmbus_request_offers();
|
||||
|
||||
return 0;
|
||||
|
||||
err_irq:
|
||||
free_irq(irq, hv_acpi_dev);
|
||||
|
||||
err_unregister:
|
||||
bus_unregister(&hv_bus);
|
||||
|
||||
err_cleanup:
|
||||
hv_cleanup();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* vmbus_child_driver_register() - Register a vmbus's child driver
|
||||
* @drv: Pointer to driver structure you want to register
|
||||
*
|
||||
* __vmbus_child_driver_register - Register a vmbus's driver
|
||||
* @drv: Pointer to driver structure you want to register
|
||||
* @owner: owner module of the drv
|
||||
* @mod_name: module name string
|
||||
*
|
||||
* Registers the given driver with Linux through the 'driver_register()' call
|
||||
* And sets up the hyper-v vmbus handling for this driver.
|
||||
* and sets up the hyper-v vmbus handling for this driver.
|
||||
* It will return the state of the 'driver_register()' call.
|
||||
*
|
||||
* Mainly used by Hyper-V drivers.
|
||||
*/
|
||||
int vmbus_child_driver_register(struct device_driver *drv)
|
||||
int __vmbus_driver_register(struct hv_driver *hv_driver, struct module *owner, const char *mod_name)
|
||||
{
|
||||
int ret;
|
||||
|
||||
pr_info("child driver registering - name %s\n", drv->name);
|
||||
pr_info("registering driver %s\n", hv_driver->name);
|
||||
|
||||
/* The child driver on this vmbus */
|
||||
drv->bus = &hv_bus;
|
||||
hv_driver->driver.name = hv_driver->name;
|
||||
hv_driver->driver.owner = owner;
|
||||
hv_driver->driver.mod_name = mod_name;
|
||||
hv_driver->driver.bus = &hv_bus;
|
||||
|
||||
ret = driver_register(drv);
|
||||
ret = driver_register(&hv_driver->driver);
|
||||
|
||||
vmbus_request_offers();
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(vmbus_child_driver_register);
|
||||
EXPORT_SYMBOL_GPL(__vmbus_driver_register);
|
||||
|
||||
/**
|
||||
* vmbus_child_driver_unregister() - Unregister a vmbus's child driver
|
||||
* @drv: Pointer to driver structure you want to un-register
|
||||
* vmbus_driver_unregister() - Unregister a vmbus's driver
|
||||
* @drv: Pointer to driver structure you want to un-register
|
||||
*
|
||||
*
|
||||
* Un-register the given driver with Linux through the 'driver_unregister()'
|
||||
* call. And ungegisters the driver from the Hyper-V vmbus handler.
|
||||
*
|
||||
* Mainly used by Hyper-V drivers.
|
||||
* Un-register the given driver that was previous registered with a call to
|
||||
* vmbus_driver_register()
|
||||
*/
|
||||
void vmbus_child_driver_unregister(struct device_driver *drv)
|
||||
void vmbus_driver_unregister(struct hv_driver *hv_driver)
|
||||
{
|
||||
pr_info("child driver unregistering - name %s\n", drv->name);
|
||||
pr_info("unregistering driver %s\n", hv_driver->name);
|
||||
|
||||
driver_unregister(drv);
|
||||
driver_unregister(&hv_driver->driver);
|
||||
|
||||
}
|
||||
EXPORT_SYMBOL(vmbus_child_driver_unregister);
|
||||
EXPORT_SYMBOL_GPL(vmbus_driver_unregister);
|
||||
|
||||
/*
|
||||
* vmbus_child_device_create - Creates and registers a new child device
|
||||
* vmbus_device_create - Creates and registers a new child device
|
||||
* on the vmbus.
|
||||
*/
|
||||
struct hv_device *vmbus_child_device_create(struct hv_guid *type,
|
||||
struct hv_guid *instance,
|
||||
struct hv_device *vmbus_device_create(uuid_le *type,
|
||||
uuid_le *instance,
|
||||
struct vmbus_channel *channel)
|
||||
{
|
||||
struct hv_device *child_device_obj;
|
||||
|
||||
/* Allocate the new child device */
|
||||
child_device_obj = kzalloc(sizeof(struct hv_device), GFP_KERNEL);
|
||||
if (!child_device_obj) {
|
||||
pr_err("Unable to allocate device object for child device\n");
|
||||
|
@ -645,29 +636,27 @@ struct hv_device *vmbus_child_device_create(struct hv_guid *type,
|
|||
}
|
||||
|
||||
child_device_obj->channel = channel;
|
||||
memcpy(&child_device_obj->dev_type, type, sizeof(struct hv_guid));
|
||||
memcpy(&child_device_obj->dev_type, type, sizeof(uuid_le));
|
||||
memcpy(&child_device_obj->dev_instance, instance,
|
||||
sizeof(struct hv_guid));
|
||||
sizeof(uuid_le));
|
||||
|
||||
|
||||
return child_device_obj;
|
||||
}
|
||||
|
||||
/*
|
||||
* vmbus_child_device_register - Register the child device
|
||||
* vmbus_device_register - Register the child device
|
||||
*/
|
||||
int vmbus_child_device_register(struct hv_device *child_device_obj)
|
||||
int vmbus_device_register(struct hv_device *child_device_obj)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
static atomic_t device_num = ATOMIC_INIT(0);
|
||||
|
||||
/* Set the device name. Otherwise, device_register() will fail. */
|
||||
dev_set_name(&child_device_obj->device, "vmbus_0_%d",
|
||||
atomic_inc_return(&device_num));
|
||||
|
||||
/* The new device belongs to this bus */
|
||||
child_device_obj->device.bus = &hv_bus; /* device->dev.bus; */
|
||||
child_device_obj->device.bus = &hv_bus;
|
||||
child_device_obj->device.parent = &hv_acpi_dev->dev;
|
||||
child_device_obj->device.release = vmbus_device_release;
|
||||
|
||||
|
@ -687,10 +676,10 @@ int vmbus_child_device_register(struct hv_device *child_device_obj)
|
|||
}
|
||||
|
||||
/*
|
||||
* vmbus_child_device_unregister - Remove the specified child device
|
||||
* vmbus_device_unregister - Remove the specified child device
|
||||
* from the vmbus.
|
||||
*/
|
||||
void vmbus_child_device_unregister(struct hv_device *device_obj)
|
||||
void vmbus_device_unregister(struct hv_device *device_obj)
|
||||
{
|
||||
/*
|
||||
* Kick off the process of unregistering the device.
|
||||
|
@ -727,9 +716,8 @@ static int vmbus_acpi_add(struct acpi_device *device)
|
|||
|
||||
hv_acpi_dev = device;
|
||||
|
||||
result =
|
||||
acpi_walk_resources(device->handle, METHOD_NAME__CRS,
|
||||
vmbus_walk_resources, &irq);
|
||||
result = acpi_walk_resources(device->handle, METHOD_NAME__CRS,
|
||||
vmbus_walk_resources, &irq);
|
||||
|
||||
if (ACPI_FAILURE(result)) {
|
||||
complete(&probe_event);
|
||||
|
@ -754,21 +742,9 @@ static struct acpi_driver vmbus_acpi_driver = {
|
|||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* We use a PCI table to determine if we should autoload this driver This is
|
||||
* needed by distro tools to determine if the hyperv drivers should be
|
||||
* installed and/or configured. We don't do anything else with the table, but
|
||||
* it needs to be present.
|
||||
*/
|
||||
static const struct pci_device_id microsoft_hv_pci_table[] = {
|
||||
{ PCI_DEVICE(0x1414, 0x5353) }, /* VGA compatible controller */
|
||||
{ 0 }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, microsoft_hv_pci_table);
|
||||
|
||||
static int __init hv_acpi_init(void)
|
||||
{
|
||||
int ret;
|
||||
int ret, t;
|
||||
|
||||
init_completion(&probe_event);
|
||||
|
||||
|
@ -781,22 +757,30 @@ static int __init hv_acpi_init(void)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
wait_for_completion(&probe_event);
|
||||
t = wait_for_completion_timeout(&probe_event, 5*HZ);
|
||||
if (t == 0) {
|
||||
ret = -ETIMEDOUT;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
if (irq <= 0) {
|
||||
acpi_bus_unregister_driver(&vmbus_acpi_driver);
|
||||
return -ENODEV;
|
||||
ret = -ENODEV;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
ret = vmbus_bus_init(irq);
|
||||
if (ret)
|
||||
acpi_bus_unregister_driver(&vmbus_acpi_driver);
|
||||
goto cleanup;
|
||||
|
||||
return 0;
|
||||
|
||||
cleanup:
|
||||
acpi_bus_unregister_driver(&vmbus_acpi_driver);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_VERSION(HV_DRV_VERSION);
|
||||
module_param(vmbus_loglevel, int, S_IRUGO|S_IWUSR);
|
||||
|
||||
module_init(hv_acpi_init);
|
|
@ -44,8 +44,6 @@ source "drivers/staging/wlan-ng/Kconfig"
|
|||
|
||||
source "drivers/staging/echo/Kconfig"
|
||||
|
||||
source "drivers/staging/brcm80211/Kconfig"
|
||||
|
||||
source "drivers/staging/comedi/Kconfig"
|
||||
|
||||
source "drivers/staging/olpc_dcon/Kconfig"
|
||||
|
@ -64,6 +62,8 @@ source "drivers/staging/rtl8712/Kconfig"
|
|||
|
||||
source "drivers/staging/rts_pstor/Kconfig"
|
||||
|
||||
source "drivers/staging/rts5139/Kconfig"
|
||||
|
||||
source "drivers/staging/frontier/Kconfig"
|
||||
|
||||
source "drivers/staging/pohmelfs/Kconfig"
|
||||
|
@ -126,8 +126,6 @@ source "drivers/staging/quickstart/Kconfig"
|
|||
|
||||
source "drivers/staging/sbe-2t3e3/Kconfig"
|
||||
|
||||
source "drivers/staging/ath6kl/Kconfig"
|
||||
|
||||
source "drivers/staging/keucr/Kconfig"
|
||||
|
||||
source "drivers/staging/bcm/Kconfig"
|
||||
|
|
|
@ -14,8 +14,6 @@ obj-$(CONFIG_USBIP_CORE) += usbip/
|
|||
obj-$(CONFIG_W35UND) += winbond/
|
||||
obj-$(CONFIG_PRISM2_USB) += wlan-ng/
|
||||
obj-$(CONFIG_ECHO) += echo/
|
||||
obj-$(CONFIG_BRCMSMAC) += brcm80211/
|
||||
obj-$(CONFIG_BRCMFMAC) += brcm80211/
|
||||
obj-$(CONFIG_COMEDI) += comedi/
|
||||
obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon/
|
||||
obj-$(CONFIG_ASUS_OLED) += asus_oled/
|
||||
|
@ -25,6 +23,7 @@ obj-$(CONFIG_RTL8192U) += rtl8192u/
|
|||
obj-$(CONFIG_RTL8192E) += rtl8192e/
|
||||
obj-$(CONFIG_R8712U) += rtl8712/
|
||||
obj-$(CONFIG_RTS_PSTOR) += rts_pstor/
|
||||
obj-$(CONFIG_RTS5139) += rts5139/
|
||||
obj-$(CONFIG_SPECTRA) += spectra/
|
||||
obj-$(CONFIG_TRANZPORT) += frontier/
|
||||
obj-$(CONFIG_POHMELFS) += pohmelfs/
|
||||
|
@ -54,7 +53,6 @@ obj-$(CONFIG_SOLO6X10) += solo6x10/
|
|||
obj-$(CONFIG_TIDSPBRIDGE) += tidspbridge/
|
||||
obj-$(CONFIG_ACPI_QUICKSTART) += quickstart/
|
||||
obj-$(CONFIG_SBE_2T3E3) += sbe-2t3e3/
|
||||
obj-$(CONFIG_ATH6K_LEGACY) += ath6kl/
|
||||
obj-$(CONFIG_USB_ENESTORAGE) += keucr/
|
||||
obj-$(CONFIG_BCM_WIMAX) += bcm/
|
||||
obj-$(CONFIG_FT1000) += ft1000/
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/string.h>
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/module.h>
|
||||
#include "altera.h"
|
||||
#include "altera-exprt.h"
|
||||
#include "altera-jtag.h"
|
||||
|
@ -2384,7 +2385,7 @@ static int altera_get_act_info(u8 *p,
|
|||
act_proc_attribute =
|
||||
(p[proc_table + (13 * act_proc_id) + 8] & 0x03);
|
||||
|
||||
procptr = (struct altera_procinfo *)
|
||||
procptr =
|
||||
kzalloc(sizeof(struct altera_procinfo),
|
||||
GFP_KERNEL);
|
||||
|
||||
|
|
|
@ -1,158 +0,0 @@
|
|||
config ATH6K_LEGACY
|
||||
tristate "Atheros AR6003 support (non mac80211)"
|
||||
depends on MMC && WLAN
|
||||
depends on CFG80211
|
||||
select WIRELESS_EXT
|
||||
select WEXT_PRIV
|
||||
help
|
||||
This module adds support for wireless adapters based on Atheros AR6003 chipset running over SDIO. If you choose to build it as a module, it will be called ath6kl. Pls note that AR6002 and AR6001 are not supported by this driver.
|
||||
|
||||
choice
|
||||
prompt "AR6003 Board Data Configuration"
|
||||
depends on ATH6K_LEGACY
|
||||
default AR600x_SD31_XXX
|
||||
help
|
||||
Select the appropriate board data template from the list below that matches your AR6003 based reference design.
|
||||
|
||||
config AR600x_SD31_XXX
|
||||
bool "SD31-xxx"
|
||||
help
|
||||
Board Data file for a standard SD31 reference design (File: bdata.SD31.bin)
|
||||
|
||||
config AR600x_WB31_XXX
|
||||
bool "WB31-xxx"
|
||||
help
|
||||
Board Data file for a standard WB31 (BT/WiFi) reference design (File: bdata.WB31.bin)
|
||||
|
||||
config AR600x_SD32_XXX
|
||||
bool "SD32-xxx"
|
||||
help
|
||||
Board Data file for a standard SD32 (5GHz) reference design (File: bdata.SD32.bin)
|
||||
|
||||
config AR600x_CUSTOM_XXX
|
||||
bool "CUSTOM-xxx"
|
||||
help
|
||||
Board Data file for a custom reference design (File: should be named as bdata.CUSTOM.bin)
|
||||
endchoice
|
||||
|
||||
config ATH6KL_ENABLE_COEXISTENCE
|
||||
bool "BT Coexistence support"
|
||||
depends on ATH6K_LEGACY
|
||||
help
|
||||
Enables WLAN/BT coexistence support. Select the apprpriate configuration from below.
|
||||
|
||||
choice
|
||||
prompt "Front-End Antenna Configuration"
|
||||
depends on ATH6KL_ENABLE_COEXISTENCE
|
||||
default AR600x_DUAL_ANTENNA
|
||||
help
|
||||
Indicates the number of antennas being used by BT and WLAN. Select the appropriate configuration from the list below that matches your AR6003 based reference design.
|
||||
|
||||
config AR600x_DUAL_ANTENNA
|
||||
bool "Dual Antenna"
|
||||
help
|
||||
Dual Antenna Design
|
||||
|
||||
config AR600x_SINGLE_ANTENNA
|
||||
bool "Single Antenna"
|
||||
help
|
||||
Single Antenna Design
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Collocated Bluetooth Type"
|
||||
depends on ATH6KL_ENABLE_COEXISTENCE
|
||||
default AR600x_BT_AR3001
|
||||
help
|
||||
Select the appropriate configuration from the list below that matches your AR6003 based reference design.
|
||||
|
||||
config AR600x_BT_QCOM
|
||||
bool "Qualcomm BTS4020X"
|
||||
help
|
||||
Qualcomm BT (3 Wire PTA)
|
||||
|
||||
config AR600x_BT_CSR
|
||||
bool "CSR BC06"
|
||||
help
|
||||
CSR BT (3 Wire PTA)
|
||||
|
||||
config AR600x_BT_AR3001
|
||||
bool "Atheros AR3001"
|
||||
help
|
||||
Atheros BT (3 Wire PTA)
|
||||
endchoice
|
||||
|
||||
config ATH6KL_HCI_BRIDGE
|
||||
bool "HCI over SDIO support"
|
||||
depends on ATH6K_LEGACY
|
||||
help
|
||||
Enables BT over SDIO. Applicable only for combo designs (eg: WB31)
|
||||
|
||||
config ATH6KL_CONFIG_GPIO_BT_RESET
|
||||
bool "Configure BT Reset GPIO"
|
||||
depends on ATH6KL_HCI_BRIDGE
|
||||
help
|
||||
Configure a WLAN GPIO for use with BT.
|
||||
|
||||
config AR600x_BT_RESET_PIN
|
||||
int "GPIO"
|
||||
depends on ATH6KL_CONFIG_GPIO_BT_RESET
|
||||
default 22
|
||||
help
|
||||
WLAN GPIO to be used for resetting BT
|
||||
|
||||
config ATH6KL_HTC_RAW_INTERFACE
|
||||
bool "RAW HTC support"
|
||||
depends on ATH6K_LEGACY
|
||||
help
|
||||
Enables raw HTC interface. Allows application to directly talk to the HTC interface via the ioctl interface
|
||||
|
||||
config ATH6KL_VIRTUAL_SCATTER_GATHER
|
||||
bool "Virtual Scatter-Gather support"
|
||||
depends on ATH6K_LEGACY
|
||||
help
|
||||
Enables virtual scatter gather support for the hardware that does not support it natively.
|
||||
|
||||
config ATH6KL_SKIP_ABI_VERSION_CHECK
|
||||
bool "Skip ABI version check support"
|
||||
depends on ATH6K_LEGACY
|
||||
help
|
||||
Forces the driver to disable ABI version check. Caution: Incompatilbity between the host driver and target firmware may lead to unknown side effects.
|
||||
|
||||
config ATH6KL_BT_UART_FC_POLARITY
|
||||
int "UART Flow Control Polarity"
|
||||
depends on ATH6KL_LEGACY
|
||||
default 0
|
||||
help
|
||||
Configures the polarity of UART Flow Control. A value of 0 implies active low and is the default setting. Set it to 1 for active high.
|
||||
|
||||
config ATH6KL_DEBUG
|
||||
bool "Debug support"
|
||||
depends on ATH6K_LEGACY
|
||||
help
|
||||
Enables debug support
|
||||
|
||||
config ATH6KL_ENABLE_HOST_DEBUG
|
||||
bool "Host Debug support"
|
||||
depends on ATH6KL_DEBUG
|
||||
help
|
||||
Enables debug support in the driver
|
||||
|
||||
config ATH6KL_ENABLE_TARGET_DEBUG_PRINTS
|
||||
bool "Target Debug support - Enable UART prints"
|
||||
depends on ATH6KL_DEBUG
|
||||
help
|
||||
Enables uart prints
|
||||
|
||||
config AR600x_DEBUG_UART_TX_PIN
|
||||
int "GPIO"
|
||||
depends on ATH6KL_ENABLE_TARGET_DEBUG_PRINTS
|
||||
default 8
|
||||
help
|
||||
WLAN GPIO to be used for Debug UART (Tx)
|
||||
|
||||
config ATH6KL_DISABLE_TARGET_DBGLOGS
|
||||
bool "Target Debug support - Disable Debug logs"
|
||||
depends on ATH6KL_DEBUG
|
||||
help
|
||||
Enables debug logs
|
|
@ -1,122 +0,0 @@
|
|||
#------------------------------------------------------------------------------
|
||||
# Copyright (c) 2004-2010 Atheros Communications Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
#
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
#
|
||||
#
|
||||
#
|
||||
# Author(s): ="Atheros"
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
ccflags-y += -I$(obj)/include
|
||||
ccflags-y += -I$(obj)/include/common
|
||||
ccflags-y += -I$(obj)/wlan/include
|
||||
ccflags-y += -I$(obj)/os/linux/include
|
||||
ccflags-y += -I$(obj)/os
|
||||
ccflags-y += -I$(obj)/bmi/include
|
||||
ccflags-y += -I$(obj)/include/common/AR6002/hw4.0
|
||||
|
||||
ifeq ($(CONFIG_AR600x_DUAL_ANTENNA),y)
|
||||
ccflags-y += -DAR600x_DUAL_ANTENNA
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_AR600x_SINGLE_ANTENNA),y)
|
||||
ccflags-y += -DAR600x_SINGLE_ANTENNA
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_AR600x_BT_QCOM),y)
|
||||
ccflags-y += -DAR600x_BT_QCOM
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_AR600x_BT_CSR),y)
|
||||
ccflags-y += -DAR600x_BT_CSR
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_AR600x_BT_AR3001),y)
|
||||
ccflags-y += -DAR600x_BT_AR3001
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ATH6KL_HCI_BRIDGE),y)
|
||||
ccflags-y += -DATH_AR6K_ENABLE_GMBOX
|
||||
ccflags-y += -DHCI_TRANSPORT_SDIO
|
||||
ccflags-y += -DSETUPHCI_ENABLED
|
||||
ccflags-y += -DSETUPBTDEV_ENABLED
|
||||
ath6kl-y += htc2/AR6000/ar6k_gmbox.o
|
||||
ath6kl-y += htc2/AR6000/ar6k_gmbox_hciuart.o
|
||||
ath6kl-y += miscdrv/ar3kconfig.o
|
||||
ath6kl-y += miscdrv/ar3kps/ar3kpsconfig.o
|
||||
ath6kl-y += miscdrv/ar3kps/ar3kpsparser.o
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ATH6KL_CONFIG_GPIO_BT_RESET),y)
|
||||
ccflags-y += -DATH6KL_CONFIG_GPIO_BT_RESET
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ATH6KL_HTC_RAW_INTERFACE),y)
|
||||
ccflags-y += -DHTC_RAW_INTERFACE
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ATH6KL_ENABLE_HOST_DEBUG),y)
|
||||
ccflags-y += -DDEBUG
|
||||
ccflags-y += -DATH_DEBUG_MODULE
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ATH6KL_ENABLE_TARGET_DEBUG_PRINTS),y)
|
||||
ccflags-y += -DENABLEUARTPRINT_SET
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ATH6KL_DISABLE_TARGET_DBGLOGS),y)
|
||||
ccflags-y += -DATH6KL_DISABLE_TARGET_DBGLOGS
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ATH6KL_VIRTUAL_SCATTER_GATHER),y)
|
||||
ccflags-y += -DATH6KL_CONFIG_HIF_VIRTUAL_SCATTER
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ATH6KL_SKIP_ABI_VERSION_CHECK),y)
|
||||
ccflags-y += -DATH6KL_SKIP_ABI_VERSION_CHECK
|
||||
endif
|
||||
|
||||
ccflags-y += -DWAPI_ENABLE
|
||||
ccflags-y += -DCHECKSUM_OFFLOAD
|
||||
|
||||
obj-$(CONFIG_ATH6K_LEGACY) := ath6kl.o
|
||||
ath6kl-y += htc2/AR6000/ar6k.o
|
||||
ath6kl-y += htc2/AR6000/ar6k_events.o
|
||||
ath6kl-y += htc2/htc_send.o
|
||||
ath6kl-y += htc2/htc_recv.o
|
||||
ath6kl-y += htc2/htc_services.o
|
||||
ath6kl-y += htc2/htc.o
|
||||
ath6kl-y += bmi/src/bmi.o
|
||||
ath6kl-y += os/linux/cfg80211.o
|
||||
ath6kl-y += os/linux/ar6000_drv.o
|
||||
ath6kl-y += os/linux/ar6000_raw_if.o
|
||||
ath6kl-y += os/linux/ar6000_pm.o
|
||||
ath6kl-y += os/linux/netbuf.o
|
||||
ath6kl-y += os/linux/hci_bridge.o
|
||||
ath6kl-y += miscdrv/common_drv.o
|
||||
ath6kl-y += miscdrv/credit_dist.o
|
||||
ath6kl-y += wmi/wmi.o
|
||||
ath6kl-y += reorder/rcv_aggr.o
|
||||
ath6kl-y += wlan/src/wlan_node.o
|
||||
ath6kl-y += wlan/src/wlan_recv_beacon.o
|
||||
ath6kl-y += wlan/src/wlan_utils.o
|
||||
|
||||
# ATH_HIF_TYPE := sdio
|
||||
ccflags-y += -I$(obj)/hif/sdio/linux_sdio/include
|
||||
ccflags-y += -DSDIO
|
||||
ath6kl-y += hif/sdio/linux_sdio/src/hif.o
|
||||
ath6kl-y += hif/sdio/linux_sdio/src/hif_scatter.o
|
|
@ -1,25 +0,0 @@
|
|||
TODO:
|
||||
|
||||
We are working hard on cleaning up the driver. There's sooooooooo much todo
|
||||
so instead of editing this file please use the wiki:
|
||||
|
||||
http://wireless.kernel.org/en/users/Drivers/ath6kl
|
||||
|
||||
There's a respective TODO page there. Please also subscribe to the wiki page
|
||||
to get e-mail updates on changes.
|
||||
|
||||
IRC:
|
||||
|
||||
We *really* need to coordinate development for ath6kl as the cleanup
|
||||
patches will break pretty much any other patches. Please use IRC to
|
||||
help coordinate better:
|
||||
|
||||
irc.freenode.net
|
||||
#ath6kl
|
||||
|
||||
Send patches to:
|
||||
|
||||
- Greg Kroah-Hartman <greg@kroah.com>
|
||||
- Luis R. Rodriguez <mcgrof@gmail.com>
|
||||
- Joe Perches <joe@perches.com>
|
||||
- Naveen Singh <nsingh@atheros.com>
|
|
@ -1,54 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2004-2010 Atheros Communications Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef BMI_INTERNAL_H
|
||||
#define BMI_INTERNAL_H
|
||||
|
||||
#include "a_config.h"
|
||||
#include "athdefs.h"
|
||||
#include "a_osapi.h"
|
||||
#define ATH_MODULE_NAME bmi
|
||||
#include "a_debug.h"
|
||||
#include "hw/mbox_host_reg.h"
|
||||
#include "bmi_msg.h"
|
||||
|
||||
#define ATH_DEBUG_BMI ATH_DEBUG_MAKE_MODULE_MASK(0)
|
||||
|
||||
|
||||
#define BMI_COMMUNICATION_TIMEOUT 100000
|
||||
|
||||
/* ------ Global Variable Declarations ------- */
|
||||
static bool bmiDone;
|
||||
|
||||
int
|
||||
bmiBufferSend(struct hif_device *device,
|
||||
u8 *buffer,
|
||||
u32 length);
|
||||
|
||||
int
|
||||
bmiBufferReceive(struct hif_device *device,
|
||||
u8 *buffer,
|
||||
u32 length,
|
||||
bool want_timeout);
|
||||
|
||||
#endif
|
File diff suppressed because it is too large
Load diff
|
@ -1,87 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// common header file for HIF modules designed for SDIO
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef HIF_SDIO_COMMON_H_
|
||||
#define HIF_SDIO_COMMON_H_
|
||||
|
||||
/* SDIO manufacturer ID and Codes */
|
||||
#define MANUFACTURER_ID_AR6002_BASE 0x200
|
||||
#define MANUFACTURER_ID_AR6003_BASE 0x300
|
||||
#define MANUFACTURER_ID_AR6K_BASE_MASK 0xFF00
|
||||
#define FUNCTION_CLASS 0x0
|
||||
#define MANUFACTURER_CODE 0x271 /* Atheros */
|
||||
|
||||
/* Mailbox address in SDIO address space */
|
||||
#define HIF_MBOX_BASE_ADDR 0x800
|
||||
#define HIF_MBOX_WIDTH 0x800
|
||||
#define HIF_MBOX_START_ADDR(mbox) \
|
||||
( HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH)
|
||||
|
||||
#define HIF_MBOX_END_ADDR(mbox) \
|
||||
(HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1)
|
||||
|
||||
/* extended MBOX address for larger MBOX writes to MBOX 0*/
|
||||
#define HIF_MBOX0_EXTENDED_BASE_ADDR 0x2800
|
||||
#define HIF_MBOX0_EXTENDED_WIDTH_AR6002 (6*1024)
|
||||
#define HIF_MBOX0_EXTENDED_WIDTH_AR6003 (18*1024)
|
||||
|
||||
/* version 1 of the chip has only a 12K extended mbox range */
|
||||
#define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1 0x4000
|
||||
#define HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1 (12*1024)
|
||||
|
||||
/* GMBOX addresses */
|
||||
#define HIF_GMBOX_BASE_ADDR 0x7000
|
||||
#define HIF_GMBOX_WIDTH 0x4000
|
||||
|
||||
/* for SDIO we recommend a 128-byte block size */
|
||||
#define HIF_DEFAULT_IO_BLOCK_SIZE 128
|
||||
|
||||
/* set extended MBOX window information for SDIO interconnects */
|
||||
static INLINE void SetExtendedMboxWindowInfo(u16 Manfid, struct hif_device_mbox_info *pInfo)
|
||||
{
|
||||
switch (Manfid & MANUFACTURER_ID_AR6K_BASE_MASK) {
|
||||
case MANUFACTURER_ID_AR6002_BASE :
|
||||
/* MBOX 0 has an extended range */
|
||||
pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR;
|
||||
pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6002;
|
||||
break;
|
||||
case MANUFACTURER_ID_AR6003_BASE :
|
||||
/* MBOX 0 has an extended range */
|
||||
pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1;
|
||||
pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1;
|
||||
pInfo->GMboxAddress = HIF_GMBOX_BASE_ADDR;
|
||||
pInfo->GMboxSize = HIF_GMBOX_WIDTH;
|
||||
break;
|
||||
default:
|
||||
A_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* special CCCR (func 0) registers */
|
||||
|
||||
#define CCCR_SDIO_IRQ_MODE_REG 0xF0 /* interrupt mode register */
|
||||
#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ (1 << 0) /* mode to enable special 4-bit interrupt assertion without clock*/
|
||||
|
||||
#endif /*HIF_SDIO_COMMON_H_*/
|
|
@ -1,131 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="hif_internal.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// internal header file for hif layer
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _HIF_INTERNAL_H_
|
||||
#define _HIF_INTERNAL_H_
|
||||
|
||||
#include "a_config.h"
|
||||
#include "athdefs.h"
|
||||
#include "a_osapi.h"
|
||||
#include "hif.h"
|
||||
#include "../../../common/hif_sdio_common.h"
|
||||
#include <linux/scatterlist.h>
|
||||
#define HIF_LINUX_MMC_SCATTER_SUPPORT
|
||||
|
||||
#define BUS_REQUEST_MAX_NUM 64
|
||||
|
||||
#define SDIO_CLOCK_FREQUENCY_DEFAULT 25000000
|
||||
#define SDWLAN_ENABLE_DISABLE_TIMEOUT 20
|
||||
#define FLAGS_CARD_ENAB 0x02
|
||||
#define FLAGS_CARD_IRQ_UNMSK 0x04
|
||||
|
||||
#define HIF_MBOX_BLOCK_SIZE HIF_DEFAULT_IO_BLOCK_SIZE
|
||||
#define HIF_MBOX0_BLOCK_SIZE 1
|
||||
#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
|
||||
#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
|
||||
#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
|
||||
|
||||
typedef struct bus_request {
|
||||
struct bus_request *next; /* link list of available requests */
|
||||
struct bus_request *inusenext; /* link list of in use requests */
|
||||
struct semaphore sem_req;
|
||||
u32 address; /* request data */
|
||||
u8 *buffer;
|
||||
u32 length;
|
||||
u32 request;
|
||||
void *context;
|
||||
int status;
|
||||
struct hif_scatter_req_priv *pScatterReq; /* this request is a scatter request */
|
||||
} BUS_REQUEST;
|
||||
|
||||
struct hif_device {
|
||||
struct sdio_func *func;
|
||||
spinlock_t asynclock;
|
||||
struct task_struct* async_task; /* task to handle async commands */
|
||||
struct semaphore sem_async; /* wake up for async task */
|
||||
int async_shutdown; /* stop the async task */
|
||||
struct completion async_completion; /* thread completion */
|
||||
BUS_REQUEST *asyncreq; /* request for async tasklet */
|
||||
BUS_REQUEST *taskreq; /* async tasklet data */
|
||||
spinlock_t lock;
|
||||
BUS_REQUEST *s_busRequestFreeQueue; /* free list */
|
||||
BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM]; /* available bus requests */
|
||||
void *claimedContext;
|
||||
HTC_CALLBACKS htcCallbacks;
|
||||
u8 *dma_buffer;
|
||||
struct dl_list ScatterReqHead; /* scatter request list head */
|
||||
bool scatter_enabled; /* scatter enabled flag */
|
||||
bool is_suspend;
|
||||
bool is_disabled;
|
||||
atomic_t irqHandling;
|
||||
HIF_DEVICE_POWER_CHANGE_TYPE powerConfig;
|
||||
const struct sdio_device_id *id;
|
||||
};
|
||||
|
||||
#define HIF_DMA_BUFFER_SIZE (32 * 1024)
|
||||
#define CMD53_FIXED_ADDRESS 1
|
||||
#define CMD53_INCR_ADDRESS 2
|
||||
|
||||
BUS_REQUEST *hifAllocateBusRequest(struct hif_device *device);
|
||||
void hifFreeBusRequest(struct hif_device *device, BUS_REQUEST *busrequest);
|
||||
void AddToAsyncList(struct hif_device *device, BUS_REQUEST *busrequest);
|
||||
|
||||
#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
|
||||
|
||||
#define MAX_SCATTER_REQUESTS 4
|
||||
#define MAX_SCATTER_ENTRIES_PER_REQ 16
|
||||
#define MAX_SCATTER_REQ_TRANSFER_SIZE 32*1024
|
||||
|
||||
struct hif_scatter_req_priv {
|
||||
struct hif_scatter_req *pHifScatterReq; /* HIF scatter request with allocated entries */
|
||||
struct hif_device *device; /* this device */
|
||||
BUS_REQUEST *busrequest; /* request associated with request */
|
||||
/* scatter list for linux */
|
||||
struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
|
||||
};
|
||||
|
||||
#define ATH_DEBUG_SCATTER ATH_DEBUG_MAKE_MODULE_MASK(0)
|
||||
|
||||
int SetupHIFScatterSupport(struct hif_device *device, struct hif_device_scatter_support_info *pInfo);
|
||||
void CleanupHIFScatterResources(struct hif_device *device);
|
||||
int DoHifReadWriteScatter(struct hif_device *device, BUS_REQUEST *busrequest);
|
||||
|
||||
#else // HIF_LINUX_MMC_SCATTER_SUPPORT
|
||||
|
||||
static inline int SetupHIFScatterSupport(struct hif_device *device, struct hif_device_scatter_support_info *pInfo)
|
||||
{
|
||||
return A_ENOTSUP;
|
||||
}
|
||||
|
||||
static inline int DoHifReadWriteScatter(struct hif_device *device, BUS_REQUEST *busrequest)
|
||||
{
|
||||
return A_ENOTSUP;
|
||||
}
|
||||
|
||||
#define CleanupHIFScatterResources(d) { }
|
||||
|
||||
#endif // HIF_LINUX_MMC_SCATTER_SUPPORT
|
||||
|
||||
#endif // _HIF_INTERNAL_H_
|
||||
|
File diff suppressed because it is too large
Load diff
|
@ -1,393 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// HIF scatter implementation
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#include <linux/mmc/card.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/mmc/sdio_func.h>
|
||||
#include <linux/mmc/sdio_ids.h>
|
||||
#include <linux/mmc/sdio.h>
|
||||
#include <linux/kthread.h>
|
||||
#include "hif_internal.h"
|
||||
#define ATH_MODULE_NAME hif
|
||||
#include "a_debug.h"
|
||||
|
||||
#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
|
||||
|
||||
#define _CMD53_ARG_READ 0
|
||||
#define _CMD53_ARG_WRITE 1
|
||||
#define _CMD53_ARG_BLOCK_BASIS 1
|
||||
#define _CMD53_ARG_FIXED_ADDRESS 0
|
||||
#define _CMD53_ARG_INCR_ADDRESS 1
|
||||
|
||||
#define SDIO_SET_CMD53_ARG(arg,rw,func,mode,opcode,address,bytes_blocks) \
|
||||
(arg) = (((rw) & 1) << 31) | \
|
||||
(((func) & 0x7) << 28) | \
|
||||
(((mode) & 1) << 27) | \
|
||||
(((opcode) & 1) << 26) | \
|
||||
(((address) & 0x1FFFF) << 9) | \
|
||||
((bytes_blocks) & 0x1FF)
|
||||
|
||||
static void FreeScatterReq(struct hif_device *device, struct hif_scatter_req *pReq)
|
||||
{
|
||||
unsigned long flag;
|
||||
|
||||
spin_lock_irqsave(&device->lock, flag);
|
||||
|
||||
DL_ListInsertTail(&device->ScatterReqHead, &pReq->ListLink);
|
||||
|
||||
spin_unlock_irqrestore(&device->lock, flag);
|
||||
|
||||
}
|
||||
|
||||
static struct hif_scatter_req *AllocScatterReq(struct hif_device *device)
|
||||
{
|
||||
struct dl_list *pItem;
|
||||
unsigned long flag;
|
||||
|
||||
spin_lock_irqsave(&device->lock, flag);
|
||||
|
||||
pItem = DL_ListRemoveItemFromHead(&device->ScatterReqHead);
|
||||
|
||||
spin_unlock_irqrestore(&device->lock, flag);
|
||||
|
||||
if (pItem != NULL) {
|
||||
return A_CONTAINING_STRUCT(pItem, struct hif_scatter_req, ListLink);
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* called by async task to perform the operation synchronously using direct MMC APIs */
|
||||
int DoHifReadWriteScatter(struct hif_device *device, BUS_REQUEST *busrequest)
|
||||
{
|
||||
int i;
|
||||
u8 rw;
|
||||
u8 opcode;
|
||||
struct mmc_request mmcreq;
|
||||
struct mmc_command cmd;
|
||||
struct mmc_data data;
|
||||
struct hif_scatter_req_priv *pReqPriv;
|
||||
struct hif_scatter_req *pReq;
|
||||
int status = 0;
|
||||
struct scatterlist *pSg;
|
||||
|
||||
pReqPriv = busrequest->pScatterReq;
|
||||
|
||||
A_ASSERT(pReqPriv != NULL);
|
||||
|
||||
pReq = pReqPriv->pHifScatterReq;
|
||||
|
||||
memset(&mmcreq, 0, sizeof(struct mmc_request));
|
||||
memset(&cmd, 0, sizeof(struct mmc_command));
|
||||
memset(&data, 0, sizeof(struct mmc_data));
|
||||
|
||||
data.blksz = HIF_MBOX_BLOCK_SIZE;
|
||||
data.blocks = pReq->TotalLength / HIF_MBOX_BLOCK_SIZE;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: (%s) Address: 0x%X, (BlockLen: %d, BlockCount: %d) , (tot:%d,sg:%d)\n",
|
||||
(pReq->Request & HIF_WRITE) ? "WRITE":"READ", pReq->Address, data.blksz, data.blocks,
|
||||
pReq->TotalLength,pReq->ValidScatterEntries));
|
||||
|
||||
if (pReq->Request & HIF_WRITE) {
|
||||
rw = _CMD53_ARG_WRITE;
|
||||
data.flags = MMC_DATA_WRITE;
|
||||
} else {
|
||||
rw = _CMD53_ARG_READ;
|
||||
data.flags = MMC_DATA_READ;
|
||||
}
|
||||
|
||||
if (pReq->Request & HIF_FIXED_ADDRESS) {
|
||||
opcode = _CMD53_ARG_FIXED_ADDRESS;
|
||||
} else {
|
||||
opcode = _CMD53_ARG_INCR_ADDRESS;
|
||||
}
|
||||
|
||||
/* fill SG entries */
|
||||
pSg = pReqPriv->sgentries;
|
||||
sg_init_table(pSg, pReq->ValidScatterEntries);
|
||||
|
||||
/* assemble SG list */
|
||||
for (i = 0 ; i < pReq->ValidScatterEntries ; i++, pSg++) {
|
||||
/* setup each sg entry */
|
||||
if ((unsigned long)pReq->ScatterList[i].pBuffer & 0x3) {
|
||||
/* note some scatter engines can handle unaligned buffers, print this
|
||||
* as informational only */
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
|
||||
("HIF: (%s) Scatter Buffer is unaligned 0x%lx\n",
|
||||
pReq->Request & HIF_WRITE ? "WRITE":"READ",
|
||||
(unsigned long)pReq->ScatterList[i].pBuffer));
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, (" %d: Addr:0x%lX, Len:%d \n",
|
||||
i,(unsigned long)pReq->ScatterList[i].pBuffer,pReq->ScatterList[i].Length));
|
||||
|
||||
sg_set_buf(pSg, pReq->ScatterList[i].pBuffer, pReq->ScatterList[i].Length);
|
||||
}
|
||||
/* set scatter-gather table for request */
|
||||
data.sg = pReqPriv->sgentries;
|
||||
data.sg_len = pReq->ValidScatterEntries;
|
||||
/* set command argument */
|
||||
SDIO_SET_CMD53_ARG(cmd.arg,
|
||||
rw,
|
||||
device->func->num,
|
||||
_CMD53_ARG_BLOCK_BASIS,
|
||||
opcode,
|
||||
pReq->Address,
|
||||
data.blocks);
|
||||
|
||||
cmd.opcode = SD_IO_RW_EXTENDED;
|
||||
cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
|
||||
|
||||
mmcreq.cmd = &cmd;
|
||||
mmcreq.data = &data;
|
||||
|
||||
mmc_set_data_timeout(&data, device->func->card);
|
||||
/* synchronous call to process request */
|
||||
mmc_wait_for_req(device->func->card->host, &mmcreq);
|
||||
|
||||
if (cmd.error) {
|
||||
status = A_ERROR;
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: cmd error: %d \n",cmd.error));
|
||||
}
|
||||
|
||||
if (data.error) {
|
||||
status = A_ERROR;
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: data error: %d \n",data.error));
|
||||
}
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: FAILED!!! (%s) Address: 0x%X, Block mode (BlockLen: %d, BlockCount: %d)\n",
|
||||
(pReq->Request & HIF_WRITE) ? "WRITE":"READ",pReq->Address, data.blksz, data.blocks));
|
||||
}
|
||||
|
||||
/* set completion status, fail or success */
|
||||
pReq->CompletionStatus = status;
|
||||
|
||||
if (pReq->Request & HIF_ASYNCHRONOUS) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: async_task completion routine req: 0x%lX (%d)\n",(unsigned long)busrequest, status));
|
||||
/* complete the request */
|
||||
A_ASSERT(pReq->CompletionRoutine != NULL);
|
||||
pReq->CompletionRoutine(pReq);
|
||||
} else {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER async_task upping busrequest : 0x%lX (%d)\n", (unsigned long)busrequest,status));
|
||||
/* signal wait */
|
||||
up(&busrequest->sem_req);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* callback to issue a read-write scatter request */
|
||||
static int HifReadWriteScatter(struct hif_device *device, struct hif_scatter_req *pReq)
|
||||
{
|
||||
int status = A_EINVAL;
|
||||
u32 request = pReq->Request;
|
||||
struct hif_scatter_req_priv *pReqPriv = (struct hif_scatter_req_priv *)pReq->HIFPrivate[0];
|
||||
|
||||
do {
|
||||
|
||||
A_ASSERT(pReqPriv != NULL);
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: total len: %d Scatter Entries: %d\n",
|
||||
pReq->TotalLength, pReq->ValidScatterEntries));
|
||||
|
||||
if (!(request & HIF_EXTENDED_IO)) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
|
||||
("HIF-SCATTER: Invalid command type: 0x%08x\n", request));
|
||||
break;
|
||||
}
|
||||
|
||||
if (!(request & (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS))) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
|
||||
("HIF-SCATTER: Invalid execution mode: 0x%08x\n", request));
|
||||
break;
|
||||
}
|
||||
|
||||
if (!(request & HIF_BLOCK_BASIS)) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
|
||||
("HIF-SCATTER: Invalid data mode: 0x%08x\n", request));
|
||||
break;
|
||||
}
|
||||
|
||||
if (pReq->TotalLength > MAX_SCATTER_REQ_TRANSFER_SIZE) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
|
||||
("HIF-SCATTER: Invalid length: %d \n", pReq->TotalLength));
|
||||
break;
|
||||
}
|
||||
|
||||
if (pReq->TotalLength == 0) {
|
||||
A_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
|
||||
/* add bus request to the async list for the async I/O thread to process */
|
||||
AddToAsyncList(device, pReqPriv->busrequest);
|
||||
|
||||
if (request & HIF_SYNCHRONOUS) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued sync req: 0x%lX\n", (unsigned long)pReqPriv->busrequest));
|
||||
/* signal thread and wait */
|
||||
up(&device->sem_async);
|
||||
if (down_interruptible(&pReqPriv->busrequest->sem_req) != 0) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,("HIF-SCATTER: interrupted! \n"));
|
||||
/* interrupted, exit */
|
||||
status = A_ERROR;
|
||||
break;
|
||||
} else {
|
||||
status = pReq->CompletionStatus;
|
||||
}
|
||||
} else {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued async req: 0x%lX\n", (unsigned long)pReqPriv->busrequest));
|
||||
/* wake thread, it will process and then take care of the async callback */
|
||||
up(&device->sem_async);
|
||||
status = 0;
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
if (status && (request & HIF_ASYNCHRONOUS)) {
|
||||
pReq->CompletionStatus = status;
|
||||
pReq->CompletionRoutine(pReq);
|
||||
status = 0;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* setup of HIF scatter resources */
|
||||
int SetupHIFScatterSupport(struct hif_device *device, struct hif_device_scatter_support_info *pInfo)
|
||||
{
|
||||
int status = A_ERROR;
|
||||
int i;
|
||||
struct hif_scatter_req_priv *pReqPriv;
|
||||
BUS_REQUEST *busrequest;
|
||||
|
||||
do {
|
||||
|
||||
/* check if host supports scatter requests and it meets our requirements */
|
||||
if (device->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : host only supports scatter of : %d entries, need: %d \n",
|
||||
device->func->card->host->max_segs, MAX_SCATTER_ENTRIES_PER_REQ));
|
||||
status = A_ENOTSUP;
|
||||
break;
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HIF-SCATTER Enabled: max scatter req : %d entries: %d \n",
|
||||
MAX_SCATTER_REQUESTS, MAX_SCATTER_ENTRIES_PER_REQ));
|
||||
|
||||
for (i = 0; i < MAX_SCATTER_REQUESTS; i++) {
|
||||
/* allocate the private request blob */
|
||||
pReqPriv = (struct hif_scatter_req_priv *)A_MALLOC(sizeof(struct hif_scatter_req_priv));
|
||||
if (NULL == pReqPriv) {
|
||||
break;
|
||||
}
|
||||
A_MEMZERO(pReqPriv, sizeof(struct hif_scatter_req_priv));
|
||||
/* save the device instance*/
|
||||
pReqPriv->device = device;
|
||||
/* allocate the scatter request */
|
||||
pReqPriv->pHifScatterReq = (struct hif_scatter_req *)A_MALLOC(sizeof(struct hif_scatter_req) +
|
||||
(MAX_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(struct hif_scatter_item)));
|
||||
|
||||
if (NULL == pReqPriv->pHifScatterReq) {
|
||||
kfree(pReqPriv);
|
||||
break;
|
||||
}
|
||||
/* just zero the main part of the scatter request */
|
||||
A_MEMZERO(pReqPriv->pHifScatterReq, sizeof(struct hif_scatter_req));
|
||||
/* back pointer to the private struct */
|
||||
pReqPriv->pHifScatterReq->HIFPrivate[0] = pReqPriv;
|
||||
/* allocate a bus request for this scatter request */
|
||||
busrequest = hifAllocateBusRequest(device);
|
||||
if (NULL == busrequest) {
|
||||
kfree(pReqPriv->pHifScatterReq);
|
||||
kfree(pReqPriv);
|
||||
break;
|
||||
}
|
||||
/* assign the scatter request to this bus request */
|
||||
busrequest->pScatterReq = pReqPriv;
|
||||
/* point back to the request */
|
||||
pReqPriv->busrequest = busrequest;
|
||||
/* add it to the scatter pool */
|
||||
FreeScatterReq(device,pReqPriv->pHifScatterReq);
|
||||
}
|
||||
|
||||
if (i != MAX_SCATTER_REQUESTS) {
|
||||
status = A_NO_MEMORY;
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : failed to alloc scatter resources !\n"));
|
||||
break;
|
||||
}
|
||||
|
||||
/* set scatter function pointers */
|
||||
pInfo->pAllocateReqFunc = AllocScatterReq;
|
||||
pInfo->pFreeReqFunc = FreeScatterReq;
|
||||
pInfo->pReadWriteScatterFunc = HifReadWriteScatter;
|
||||
pInfo->MaxScatterEntries = MAX_SCATTER_ENTRIES_PER_REQ;
|
||||
pInfo->MaxTransferSizePerScatterReq = MAX_SCATTER_REQ_TRANSFER_SIZE;
|
||||
|
||||
status = 0;
|
||||
|
||||
} while (false);
|
||||
|
||||
if (status) {
|
||||
CleanupHIFScatterResources(device);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* clean up scatter support */
|
||||
void CleanupHIFScatterResources(struct hif_device *device)
|
||||
{
|
||||
struct hif_scatter_req_priv *pReqPriv;
|
||||
struct hif_scatter_req *pReq;
|
||||
|
||||
/* empty the free list */
|
||||
|
||||
while (1) {
|
||||
|
||||
pReq = AllocScatterReq(device);
|
||||
|
||||
if (NULL == pReq) {
|
||||
break;
|
||||
}
|
||||
|
||||
pReqPriv = (struct hif_scatter_req_priv *)pReq->HIFPrivate[0];
|
||||
A_ASSERT(pReqPriv != NULL);
|
||||
|
||||
if (pReqPriv->busrequest != NULL) {
|
||||
pReqPriv->busrequest->pScatterReq = NULL;
|
||||
/* free bus request */
|
||||
hifFreeBusRequest(device, pReqPriv->busrequest);
|
||||
pReqPriv->busrequest = NULL;
|
||||
}
|
||||
|
||||
if (pReqPriv->pHifScatterReq != NULL) {
|
||||
kfree(pReqPriv->pHifScatterReq);
|
||||
pReqPriv->pHifScatterReq = NULL;
|
||||
}
|
||||
|
||||
kfree(pReqPriv);
|
||||
}
|
||||
}
|
||||
|
||||
#endif // HIF_LINUX_MMC_SCATTER_SUPPORT
|
File diff suppressed because it is too large
Load diff
|
@ -1,401 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="ar6k.h" company="Atheros">
|
||||
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// AR6K device layer that handles register level I/O
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef AR6K_H_
|
||||
#define AR6K_H_
|
||||
|
||||
#include "hci_transport_api.h"
|
||||
#include "../htc_debug.h"
|
||||
|
||||
#define AR6K_MAILBOXES 4
|
||||
|
||||
/* HTC runs over mailbox 0 */
|
||||
#define HTC_MAILBOX 0
|
||||
|
||||
#define AR6K_TARGET_DEBUG_INTR_MASK 0x01
|
||||
|
||||
#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \
|
||||
INT_STATUS_ENABLE_CPU_MASK | \
|
||||
INT_STATUS_ENABLE_COUNTER_MASK)
|
||||
|
||||
|
||||
//#define MBOXHW_UNIT_TEST 1
|
||||
|
||||
PREPACK struct ar6k_irq_proc_registers {
|
||||
u8 host_int_status;
|
||||
u8 cpu_int_status;
|
||||
u8 error_int_status;
|
||||
u8 counter_int_status;
|
||||
u8 mbox_frame;
|
||||
u8 rx_lookahead_valid;
|
||||
u8 host_int_status2;
|
||||
u8 gmbox_rx_avail;
|
||||
u32 rx_lookahead[2];
|
||||
u32 rx_gmbox_lookahead_alias[2];
|
||||
} POSTPACK;
|
||||
|
||||
#define AR6K_IRQ_PROC_REGS_SIZE sizeof(struct ar6k_irq_proc_registers)
|
||||
|
||||
PREPACK struct ar6k_irq_enable_registers {
|
||||
u8 int_status_enable;
|
||||
u8 cpu_int_status_enable;
|
||||
u8 error_status_enable;
|
||||
u8 counter_int_status_enable;
|
||||
} POSTPACK;
|
||||
|
||||
PREPACK struct ar6k_gmbox_ctrl_registers {
|
||||
u8 int_status_enable;
|
||||
} POSTPACK;
|
||||
|
||||
#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(struct ar6k_irq_enable_registers)
|
||||
|
||||
#define AR6K_REG_IO_BUFFER_SIZE 32
|
||||
#define AR6K_MAX_REG_IO_BUFFERS 8
|
||||
#define FROM_DMA_BUFFER true
|
||||
#define TO_DMA_BUFFER false
|
||||
#define AR6K_SCATTER_ENTRIES_PER_REQ 16
|
||||
#define AR6K_MAX_TRANSFER_SIZE_PER_SCATTER 16*1024
|
||||
#define AR6K_SCATTER_REQS 4
|
||||
#define AR6K_LEGACY_MAX_WRITE_LENGTH 2048
|
||||
|
||||
#ifndef A_CACHE_LINE_PAD
|
||||
#define A_CACHE_LINE_PAD 128
|
||||
#endif
|
||||
#define AR6K_MIN_SCATTER_ENTRIES_PER_REQ 2
|
||||
#define AR6K_MIN_TRANSFER_SIZE_PER_SCATTER 4*1024
|
||||
|
||||
/* buffers for ASYNC I/O */
|
||||
struct ar6k_async_reg_io_buffer {
|
||||
struct htc_packet HtcPacket; /* we use an HTC packet as a wrapper for our async register-based I/O */
|
||||
u8 _Pad1[A_CACHE_LINE_PAD];
|
||||
u8 Buffer[AR6K_REG_IO_BUFFER_SIZE]; /* cache-line safe with pads around */
|
||||
u8 _Pad2[A_CACHE_LINE_PAD];
|
||||
};
|
||||
|
||||
struct ar6k_gmbox_info {
|
||||
void *pProtocolContext;
|
||||
int (*pMessagePendingCallBack)(void *pContext, u8 LookAheadBytes[], int ValidBytes);
|
||||
int (*pCreditsPendingCallback)(void *pContext, int NumCredits, bool CreditIRQEnabled);
|
||||
void (*pTargetFailureCallback)(void *pContext, int Status);
|
||||
void (*pStateDumpCallback)(void *pContext);
|
||||
bool CreditCountIRQEnabled;
|
||||
};
|
||||
|
||||
struct ar6k_device {
|
||||
A_MUTEX_T Lock;
|
||||
u8 _Pad1[A_CACHE_LINE_PAD];
|
||||
struct ar6k_irq_proc_registers IrqProcRegisters; /* cache-line safe with pads around */
|
||||
u8 _Pad2[A_CACHE_LINE_PAD];
|
||||
struct ar6k_irq_enable_registers IrqEnableRegisters; /* cache-line safe with pads around */
|
||||
u8 _Pad3[A_CACHE_LINE_PAD];
|
||||
void *HIFDevice;
|
||||
u32 BlockSize;
|
||||
u32 BlockMask;
|
||||
struct hif_device_mbox_info MailBoxInfo;
|
||||
HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc;
|
||||
void *HTCContext;
|
||||
struct htc_packet_queue RegisterIOList;
|
||||
struct ar6k_async_reg_io_buffer RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS];
|
||||
void (*TargetFailureCallback)(void *Context);
|
||||
int (*MessagePendingCallback)(void *Context,
|
||||
u32 LookAheads[],
|
||||
int NumLookAheads,
|
||||
bool *pAsyncProc,
|
||||
int *pNumPktsFetched);
|
||||
HIF_DEVICE_IRQ_PROCESSING_MODE HifIRQProcessingMode;
|
||||
HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent;
|
||||
bool HifAttached;
|
||||
struct hif_device_irq_yield_params HifIRQYieldParams;
|
||||
bool DSRCanYield;
|
||||
int CurrentDSRRecvCount;
|
||||
struct hif_device_scatter_support_info HifScatterInfo;
|
||||
struct dl_list ScatterReqHead;
|
||||
bool ScatterIsVirtual;
|
||||
int MaxRecvBundleSize;
|
||||
int MaxSendBundleSize;
|
||||
struct ar6k_gmbox_info GMboxInfo;
|
||||
bool GMboxEnabled;
|
||||
struct ar6k_gmbox_ctrl_registers GMboxControlRegisters;
|
||||
int RecheckIRQStatusCnt;
|
||||
};
|
||||
|
||||
#define LOCK_AR6K(p) A_MUTEX_LOCK(&(p)->Lock);
|
||||
#define UNLOCK_AR6K(p) A_MUTEX_UNLOCK(&(p)->Lock);
|
||||
#define REF_IRQ_STATUS_RECHECK(p) (p)->RecheckIRQStatusCnt = 1 /* note: no need to lock this, it only gets set */
|
||||
|
||||
int DevSetup(struct ar6k_device *pDev);
|
||||
void DevCleanup(struct ar6k_device *pDev);
|
||||
int DevUnmaskInterrupts(struct ar6k_device *pDev);
|
||||
int DevMaskInterrupts(struct ar6k_device *pDev);
|
||||
int DevPollMboxMsgRecv(struct ar6k_device *pDev,
|
||||
u32 *pLookAhead,
|
||||
int TimeoutMS);
|
||||
int DevRWCompletionHandler(void *context, int status);
|
||||
int DevDsrHandler(void *context);
|
||||
int DevCheckPendingRecvMsgsAsync(void *context);
|
||||
void DevAsyncIrqProcessComplete(struct ar6k_device *pDev);
|
||||
void DevDumpRegisters(struct ar6k_device *pDev,
|
||||
struct ar6k_irq_proc_registers *pIrqProcRegs,
|
||||
struct ar6k_irq_enable_registers *pIrqEnableRegs);
|
||||
|
||||
#define DEV_STOP_RECV_ASYNC true
|
||||
#define DEV_STOP_RECV_SYNC false
|
||||
#define DEV_ENABLE_RECV_ASYNC true
|
||||
#define DEV_ENABLE_RECV_SYNC false
|
||||
int DevStopRecv(struct ar6k_device *pDev, bool ASyncMode);
|
||||
int DevEnableRecv(struct ar6k_device *pDev, bool ASyncMode);
|
||||
int DevEnableInterrupts(struct ar6k_device *pDev);
|
||||
int DevDisableInterrupts(struct ar6k_device *pDev);
|
||||
int DevWaitForPendingRecv(struct ar6k_device *pDev,u32 TimeoutInMs,bool *pbIsRecvPending);
|
||||
|
||||
#define DEV_CALC_RECV_PADDED_LEN(pDev, length) (((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask)))
|
||||
#define DEV_CALC_SEND_PADDED_LEN(pDev, length) DEV_CALC_RECV_PADDED_LEN(pDev,length)
|
||||
#define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) (((length) % (pDev)->BlockSize) == 0)
|
||||
|
||||
static INLINE int DevSendPacket(struct ar6k_device *pDev, struct htc_packet *pPacket, u32 SendLength) {
|
||||
u32 paddedLength;
|
||||
bool sync = (pPacket->Completion == NULL) ? true : false;
|
||||
int status;
|
||||
|
||||
/* adjust the length to be a multiple of block size if appropriate */
|
||||
paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, SendLength);
|
||||
|
||||
#if 0
|
||||
if (paddedLength > pPacket->BufferLength) {
|
||||
A_ASSERT(false);
|
||||
if (pPacket->Completion != NULL) {
|
||||
COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
|
||||
return 0;
|
||||
}
|
||||
return A_EINVAL;
|
||||
}
|
||||
#endif
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
|
||||
("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
|
||||
paddedLength,
|
||||
pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
|
||||
sync ? "SYNC" : "ASYNC"));
|
||||
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
|
||||
pPacket->pBuffer,
|
||||
paddedLength, /* the padded length */
|
||||
sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
|
||||
sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
|
||||
|
||||
if (sync) {
|
||||
pPacket->Status = status;
|
||||
} else {
|
||||
if (status == A_PENDING) {
|
||||
status = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static INLINE int DevRecvPacket(struct ar6k_device *pDev, struct htc_packet *pPacket, u32 RecvLength) {
|
||||
u32 paddedLength;
|
||||
int status;
|
||||
bool sync = (pPacket->Completion == NULL) ? true : false;
|
||||
|
||||
/* adjust the length to be a multiple of block size if appropriate */
|
||||
paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, RecvLength);
|
||||
|
||||
if (paddedLength > pPacket->BufferLength) {
|
||||
A_ASSERT(false);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
|
||||
paddedLength,RecvLength,pPacket->BufferLength));
|
||||
if (pPacket->Completion != NULL) {
|
||||
COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
|
||||
return 0;
|
||||
}
|
||||
return A_EINVAL;
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
|
||||
("DevRecvPacket (0x%lX : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n",
|
||||
(unsigned long)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr,
|
||||
paddedLength,
|
||||
pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
|
||||
sync ? "SYNC" : "ASYNC"));
|
||||
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
|
||||
pPacket->pBuffer,
|
||||
paddedLength,
|
||||
sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX,
|
||||
sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
|
||||
|
||||
if (sync) {
|
||||
pPacket->Status = status;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#define DEV_CHECK_RECV_YIELD(pDev) \
|
||||
((pDev)->CurrentDSRRecvCount >= (pDev)->HifIRQYieldParams.RecvPacketYieldCount)
|
||||
|
||||
#define IS_DEV_IRQ_PROC_SYNC_MODE(pDev) (HIF_DEVICE_IRQ_SYNC_ONLY == (pDev)->HifIRQProcessingMode)
|
||||
#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY)
|
||||
|
||||
/**************************************************/
|
||||
/****** Scatter Function and Definitions
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
int DevCopyScatterListToFromDMABuffer(struct hif_scatter_req *pReq, bool FromDMA);
|
||||
|
||||
/* copy any READ data back into scatter list */
|
||||
#define DEV_FINISH_SCATTER_OPERATION(pR) \
|
||||
do { \
|
||||
if (!((pR)->CompletionStatus) && \
|
||||
!((pR)->Request & HIF_WRITE) && \
|
||||
((pR)->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) { \
|
||||
(pR)->CompletionStatus = \
|
||||
DevCopyScatterListToFromDMABuffer((pR), \
|
||||
FROM_DMA_BUFFER); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/* copy any WRITE data to bounce buffer */
|
||||
static INLINE int DEV_PREPARE_SCATTER_OPERATION(struct hif_scatter_req *pReq) {
|
||||
if ((pReq->Request & HIF_WRITE) && (pReq->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) {
|
||||
return DevCopyScatterListToFromDMABuffer(pReq,TO_DMA_BUFFER);
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
int DevSetupMsgBundling(struct ar6k_device *pDev, int MaxMsgsPerTransfer);
|
||||
|
||||
int DevCleanupMsgBundling(struct ar6k_device *pDev);
|
||||
|
||||
#define DEV_GET_MAX_MSG_PER_BUNDLE(pDev) (pDev)->HifScatterInfo.MaxScatterEntries
|
||||
#define DEV_GET_MAX_BUNDLE_LENGTH(pDev) (pDev)->HifScatterInfo.MaxTransferSizePerScatterReq
|
||||
#define DEV_ALLOC_SCATTER_REQ(pDev) \
|
||||
(pDev)->HifScatterInfo.pAllocateReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice)
|
||||
|
||||
#define DEV_FREE_SCATTER_REQ(pDev,pR) \
|
||||
(pDev)->HifScatterInfo.pFreeReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice,(pR))
|
||||
|
||||
#define DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev) (pDev)->MaxRecvBundleSize
|
||||
#define DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev) (pDev)->MaxSendBundleSize
|
||||
|
||||
#define DEV_SCATTER_READ true
|
||||
#define DEV_SCATTER_WRITE false
|
||||
#define DEV_SCATTER_ASYNC true
|
||||
#define DEV_SCATTER_SYNC false
|
||||
int DevSubmitScatterRequest(struct ar6k_device *pDev, struct hif_scatter_req *pScatterReq, bool Read, bool Async);
|
||||
|
||||
#ifdef MBOXHW_UNIT_TEST
|
||||
int DoMboxHWTest(struct ar6k_device *pDev);
|
||||
#endif
|
||||
|
||||
/* completely virtual */
|
||||
struct dev_scatter_dma_virtual_info {
|
||||
u8 *pVirtDmaBuffer; /* dma-able buffer - CPU accessible address */
|
||||
u8 DataArea[1]; /* start of data area */
|
||||
};
|
||||
|
||||
|
||||
|
||||
void DumpAR6KDevState(struct ar6k_device *pDev);
|
||||
|
||||
/**************************************************/
|
||||
/****** GMBOX functions and definitions
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef ATH_AR6K_ENABLE_GMBOX
|
||||
|
||||
void DevCleanupGMbox(struct ar6k_device *pDev);
|
||||
int DevSetupGMbox(struct ar6k_device *pDev);
|
||||
int DevCheckGMboxInterrupts(struct ar6k_device *pDev);
|
||||
void DevNotifyGMboxTargetFailure(struct ar6k_device *pDev);
|
||||
|
||||
#else
|
||||
|
||||
/* compiled out */
|
||||
#define DevCleanupGMbox(p)
|
||||
#define DevCheckGMboxInterrupts(p) 0
|
||||
#define DevNotifyGMboxTargetFailure(p)
|
||||
|
||||
static INLINE int DevSetupGMbox(struct ar6k_device *pDev) {
|
||||
pDev->GMboxEnabled = false;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef ATH_AR6K_ENABLE_GMBOX
|
||||
|
||||
/* GMBOX protocol modules must expose each of these internal APIs */
|
||||
HCI_TRANSPORT_HANDLE GMboxAttachProtocol(struct ar6k_device *pDev, struct hci_transport_config_info *pInfo);
|
||||
int GMboxProtocolInstall(struct ar6k_device *pDev);
|
||||
void GMboxProtocolUninstall(struct ar6k_device *pDev);
|
||||
|
||||
/* API used by GMBOX protocol modules */
|
||||
struct ar6k_device *HTCGetAR6KDevice(void *HTCHandle);
|
||||
#define DEV_GMBOX_SET_PROTOCOL(pDev,recv_callback,credits_pending,failure,statedump,context) \
|
||||
{ \
|
||||
(pDev)->GMboxInfo.pProtocolContext = (context); \
|
||||
(pDev)->GMboxInfo.pMessagePendingCallBack = (recv_callback); \
|
||||
(pDev)->GMboxInfo.pCreditsPendingCallback = (credits_pending); \
|
||||
(pDev)->GMboxInfo.pTargetFailureCallback = (failure); \
|
||||
(pDev)->GMboxInfo.pStateDumpCallback = (statedump); \
|
||||
}
|
||||
|
||||
#define DEV_GMBOX_GET_PROTOCOL(pDev) (pDev)->GMboxInfo.pProtocolContext
|
||||
|
||||
int DevGMboxWrite(struct ar6k_device *pDev, struct htc_packet *pPacket, u32 WriteLength);
|
||||
int DevGMboxRead(struct ar6k_device *pDev, struct htc_packet *pPacket, u32 ReadLength);
|
||||
|
||||
#define PROC_IO_ASYNC true
|
||||
#define PROC_IO_SYNC false
|
||||
typedef enum GMBOX_IRQ_ACTION_TYPE {
|
||||
GMBOX_ACTION_NONE = 0,
|
||||
GMBOX_DISABLE_ALL,
|
||||
GMBOX_ERRORS_IRQ_ENABLE,
|
||||
GMBOX_RECV_IRQ_ENABLE,
|
||||
GMBOX_RECV_IRQ_DISABLE,
|
||||
GMBOX_CREDIT_IRQ_ENABLE,
|
||||
GMBOX_CREDIT_IRQ_DISABLE,
|
||||
} GMBOX_IRQ_ACTION_TYPE;
|
||||
|
||||
int DevGMboxIRQAction(struct ar6k_device *pDev, GMBOX_IRQ_ACTION_TYPE, bool AsyncMode);
|
||||
int DevGMboxReadCreditCounter(struct ar6k_device *pDev, bool AsyncMode, int *pCredits);
|
||||
int DevGMboxReadCreditSize(struct ar6k_device *pDev, int *pCreditSize);
|
||||
int DevGMboxRecvLookAheadPeek(struct ar6k_device *pDev, u8 *pLookAheadBuffer, int *pLookAheadBytes);
|
||||
int DevGMboxSetTargetInterrupt(struct ar6k_device *pDev, int SignalNumber, int AckTimeoutMS);
|
||||
|
||||
#endif
|
||||
|
||||
#endif /*AR6K_H_*/
|
|
@ -1,783 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="ar6k_events.c" company="Atheros">
|
||||
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// AR6K Driver layer event handling (i.e. interrupts, message polling)
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#include "a_config.h"
|
||||
#include "athdefs.h"
|
||||
#include "hw/mbox_host_reg.h"
|
||||
#include "a_osapi.h"
|
||||
#include "../htc_debug.h"
|
||||
#include "hif.h"
|
||||
#include "htc_packet.h"
|
||||
#include "ar6k.h"
|
||||
|
||||
extern void AR6KFreeIOPacket(struct ar6k_device *pDev, struct htc_packet *pPacket);
|
||||
extern struct htc_packet *AR6KAllocIOPacket(struct ar6k_device *pDev);
|
||||
|
||||
static int DevServiceDebugInterrupt(struct ar6k_device *pDev);
|
||||
|
||||
#define DELAY_PER_INTERVAL_MS 10 /* 10 MS delay per polling interval */
|
||||
|
||||
/* completion routine for ALL HIF layer async I/O */
|
||||
int DevRWCompletionHandler(void *context, int status)
|
||||
{
|
||||
struct htc_packet *pPacket = (struct htc_packet *)context;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
|
||||
("+DevRWCompletionHandler (Pkt:0x%lX) , Status: %d \n",
|
||||
(unsigned long)pPacket,
|
||||
status));
|
||||
|
||||
COMPLETE_HTC_PACKET(pPacket,status);
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
|
||||
("-DevRWCompletionHandler\n"));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* mailbox recv message polling */
|
||||
int DevPollMboxMsgRecv(struct ar6k_device *pDev,
|
||||
u32 *pLookAhead,
|
||||
int TimeoutMS)
|
||||
{
|
||||
int status = 0;
|
||||
int timeout = TimeoutMS/DELAY_PER_INTERVAL_MS;
|
||||
|
||||
A_ASSERT(timeout > 0);
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n"));
|
||||
|
||||
while (true) {
|
||||
|
||||
if (pDev->GetPendingEventsFunc != NULL) {
|
||||
|
||||
struct hif_pending_events_info events;
|
||||
|
||||
#ifdef THREAD_X
|
||||
events.Polling =1;
|
||||
#endif
|
||||
|
||||
/* the HIF layer uses a special mechanism to get events, do this
|
||||
* synchronously */
|
||||
status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
|
||||
&events,
|
||||
NULL);
|
||||
if (status)
|
||||
{
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n"));
|
||||
break;
|
||||
}
|
||||
|
||||
if (events.Events & HIF_RECV_MSG_AVAIL)
|
||||
{
|
||||
/* there is a message available, the lookahead should be valid now */
|
||||
*pLookAhead = events.LookAhead;
|
||||
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
|
||||
/* this is the standard HIF way.... */
|
||||
/* load the register table */
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
HOST_INT_STATUS_ADDRESS,
|
||||
(u8 *)&pDev->IrqProcRegisters,
|
||||
AR6K_IRQ_PROC_REGS_SIZE,
|
||||
HIF_RD_SYNC_BYTE_INC,
|
||||
NULL);
|
||||
|
||||
if (status){
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n"));
|
||||
break;
|
||||
}
|
||||
|
||||
/* check for MBOX data and valid lookahead */
|
||||
if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX)) {
|
||||
if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX))
|
||||
{
|
||||
/* mailbox has a message and the look ahead is valid */
|
||||
*pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
timeout--;
|
||||
|
||||
if (timeout <= 0) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n"));
|
||||
status = A_ERROR;
|
||||
|
||||
/* check if the target asserted */
|
||||
if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
|
||||
/* target signaled an assert, process this pending interrupt
|
||||
* this will call the target failure handler */
|
||||
DevServiceDebugInterrupt(pDev);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
/* delay a little */
|
||||
A_MDELAY(DELAY_PER_INTERVAL_MS);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Retry Mbox Poll : %d \n",timeout));
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n"));
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int DevServiceCPUInterrupt(struct ar6k_device *pDev)
|
||||
{
|
||||
int status;
|
||||
u8 cpu_int_status;
|
||||
u8 regBuffer[4];
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n"));
|
||||
cpu_int_status = pDev->IrqProcRegisters.cpu_int_status &
|
||||
pDev->IrqEnableRegisters.cpu_int_status_enable;
|
||||
A_ASSERT(cpu_int_status);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
|
||||
("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
|
||||
cpu_int_status));
|
||||
|
||||
/* Clear the interrupt */
|
||||
pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */
|
||||
|
||||
/* set up the register transfer buffer to hit the register 4 times , this is done
|
||||
* to make the access 4-byte aligned to mitigate issues with host bus interconnects that
|
||||
* restrict bus transfer lengths to be a multiple of 4-bytes */
|
||||
|
||||
/* set W1C value to clear the interrupt, this hits the register first */
|
||||
regBuffer[0] = cpu_int_status;
|
||||
/* the remaining 4 values are set to zero which have no-effect */
|
||||
regBuffer[1] = 0;
|
||||
regBuffer[2] = 0;
|
||||
regBuffer[3] = 0;
|
||||
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
CPU_INT_STATUS_ADDRESS,
|
||||
regBuffer,
|
||||
4,
|
||||
HIF_WR_SYNC_BYTE_FIX,
|
||||
NULL);
|
||||
|
||||
A_ASSERT(status == 0);
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
static int DevServiceErrorInterrupt(struct ar6k_device *pDev)
|
||||
{
|
||||
int status;
|
||||
u8 error_int_status;
|
||||
u8 regBuffer[4];
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error Interrupt\n"));
|
||||
error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F;
|
||||
A_ASSERT(error_int_status);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
|
||||
("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
|
||||
error_int_status));
|
||||
|
||||
if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) {
|
||||
/* Wakeup */
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n"));
|
||||
}
|
||||
|
||||
if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) {
|
||||
/* Rx Underflow */
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n"));
|
||||
}
|
||||
|
||||
if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) {
|
||||
/* Tx Overflow */
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n"));
|
||||
}
|
||||
|
||||
/* Clear the interrupt */
|
||||
pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */
|
||||
|
||||
/* set up the register transfer buffer to hit the register 4 times , this is done
|
||||
* to make the access 4-byte aligned to mitigate issues with host bus interconnects that
|
||||
* restrict bus transfer lengths to be a multiple of 4-bytes */
|
||||
|
||||
/* set W1C value to clear the interrupt, this hits the register first */
|
||||
regBuffer[0] = error_int_status;
|
||||
/* the remaining 4 values are set to zero which have no-effect */
|
||||
regBuffer[1] = 0;
|
||||
regBuffer[2] = 0;
|
||||
regBuffer[3] = 0;
|
||||
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
ERROR_INT_STATUS_ADDRESS,
|
||||
regBuffer,
|
||||
4,
|
||||
HIF_WR_SYNC_BYTE_FIX,
|
||||
NULL);
|
||||
|
||||
A_ASSERT(status == 0);
|
||||
return status;
|
||||
}
|
||||
|
||||
static int DevServiceDebugInterrupt(struct ar6k_device *pDev)
|
||||
{
|
||||
u32 dummy;
|
||||
int status;
|
||||
|
||||
/* Send a target failure event to the application */
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n"));
|
||||
|
||||
if (pDev->TargetFailureCallback != NULL) {
|
||||
pDev->TargetFailureCallback(pDev->HTCContext);
|
||||
}
|
||||
|
||||
if (pDev->GMboxEnabled) {
|
||||
DevNotifyGMboxTargetFailure(pDev);
|
||||
}
|
||||
|
||||
/* clear the interrupt , the debug error interrupt is
|
||||
* counter 0 */
|
||||
/* read counter to clear interrupt */
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
COUNT_DEC_ADDRESS,
|
||||
(u8 *)&dummy,
|
||||
4,
|
||||
HIF_RD_SYNC_BYTE_INC,
|
||||
NULL);
|
||||
|
||||
A_ASSERT(status == 0);
|
||||
return status;
|
||||
}
|
||||
|
||||
static int DevServiceCounterInterrupt(struct ar6k_device *pDev)
|
||||
{
|
||||
u8 counter_int_status;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n"));
|
||||
|
||||
counter_int_status = pDev->IrqProcRegisters.counter_int_status &
|
||||
pDev->IrqEnableRegisters.counter_int_status_enable;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
|
||||
("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
|
||||
counter_int_status));
|
||||
|
||||
/* Check if the debug interrupt is pending
|
||||
* NOTE: other modules like GMBOX may use the counter interrupt for
|
||||
* credit flow control on other counters, we only need to check for the debug assertion
|
||||
* counter interrupt */
|
||||
if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
|
||||
return DevServiceDebugInterrupt(pDev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* callback when our fetch to get interrupt status registers completes */
|
||||
static void DevGetEventAsyncHandler(void *Context, struct htc_packet *pPacket)
|
||||
{
|
||||
struct ar6k_device *pDev = (struct ar6k_device *)Context;
|
||||
u32 lookAhead = 0;
|
||||
bool otherInts = false;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
|
||||
|
||||
do {
|
||||
|
||||
if (pPacket->Status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
(" GetEvents I/O request failed, status:%d \n", pPacket->Status));
|
||||
/* bail out, don't unmask HIF interrupt */
|
||||
break;
|
||||
}
|
||||
|
||||
if (pDev->GetPendingEventsFunc != NULL) {
|
||||
/* the HIF layer collected the information for us */
|
||||
struct hif_pending_events_info *pEvents = (struct hif_pending_events_info *)pPacket->pBuffer;
|
||||
if (pEvents->Events & HIF_RECV_MSG_AVAIL) {
|
||||
lookAhead = pEvents->LookAhead;
|
||||
if (0 == lookAhead) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n"));
|
||||
}
|
||||
}
|
||||
if (pEvents->Events & HIF_OTHER_EVENTS) {
|
||||
otherInts = true;
|
||||
}
|
||||
} else {
|
||||
/* standard interrupt table handling.... */
|
||||
struct ar6k_irq_proc_registers *pReg = (struct ar6k_irq_proc_registers *)pPacket->pBuffer;
|
||||
u8 host_int_status;
|
||||
|
||||
host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable;
|
||||
|
||||
if (host_int_status & (1 << HTC_MAILBOX)) {
|
||||
host_int_status &= ~(1 << HTC_MAILBOX);
|
||||
if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) {
|
||||
/* mailbox has a message and the look ahead is valid */
|
||||
lookAhead = pReg->rx_lookahead[HTC_MAILBOX];
|
||||
if (0 == lookAhead) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n"));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (host_int_status) {
|
||||
/* there are other interrupts to handle */
|
||||
otherInts = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (otherInts || (lookAhead == 0)) {
|
||||
/* if there are other interrupts to process, we cannot do this in the async handler so
|
||||
* ack the interrupt which will cause our sync handler to run again
|
||||
* if however there are no more messages, we can now ack the interrupt */
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
|
||||
(" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n",
|
||||
otherInts, lookAhead));
|
||||
HIFAckInterrupt(pDev->HIFDevice);
|
||||
} else {
|
||||
int fetched = 0;
|
||||
int status;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
|
||||
(" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n",
|
||||
lookAhead));
|
||||
/* lookahead is non-zero and there are no other interrupts to service,
|
||||
* go get the next message */
|
||||
status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, NULL, &fetched);
|
||||
|
||||
if (!status && !fetched) {
|
||||
/* HTC layer could not pull out messages due to lack of resources, stop IRQ processing */
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("MessagePendingCallback did not pull any messages, force-ack \n"));
|
||||
DevAsyncIrqProcessComplete(pDev);
|
||||
}
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
/* free this IO packet */
|
||||
AR6KFreeIOPacket(pDev,pPacket);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n"));
|
||||
}
|
||||
|
||||
/* called by the HTC layer when it wants us to check if the device has any more pending
|
||||
* recv messages, this starts off a series of async requests to read interrupt registers */
|
||||
int DevCheckPendingRecvMsgsAsync(void *context)
|
||||
{
|
||||
struct ar6k_device *pDev = (struct ar6k_device *)context;
|
||||
int status = 0;
|
||||
struct htc_packet *pIOPacket;
|
||||
|
||||
/* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can
|
||||
* cause us to switch contexts */
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%lX)\n", (unsigned long)pDev));
|
||||
|
||||
do {
|
||||
|
||||
if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
|
||||
/* break the async processing chain right here, no need to continue.
|
||||
* The DevDsrHandler() will handle things in a loop when things are driven
|
||||
* synchronously */
|
||||
break;
|
||||
}
|
||||
|
||||
/* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
|
||||
* the target, if upper layers determine that we are in a low-throughput mode, we can
|
||||
* rely on taking another interrupt rather than re-checking the status registers which can
|
||||
* re-wake the target */
|
||||
if (pDev->RecheckIRQStatusCnt == 0) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, re-acking HIF interrupts\n"));
|
||||
/* ack interrupt */
|
||||
HIFAckInterrupt(pDev->HIFDevice);
|
||||
break;
|
||||
}
|
||||
|
||||
/* first allocate one of our HTC packets we created for async I/O
|
||||
* we reuse HTC packet definitions so that we can use the completion mechanism
|
||||
* in DevRWCompletionHandler() */
|
||||
pIOPacket = AR6KAllocIOPacket(pDev);
|
||||
|
||||
if (NULL == pIOPacket) {
|
||||
/* there should be only 1 asynchronous request out at a time to read these registers
|
||||
* so this should actually never happen */
|
||||
status = A_NO_MEMORY;
|
||||
A_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
|
||||
/* stick in our completion routine when the I/O operation completes */
|
||||
pIOPacket->Completion = DevGetEventAsyncHandler;
|
||||
pIOPacket->pContext = pDev;
|
||||
|
||||
if (pDev->GetPendingEventsFunc) {
|
||||
/* HIF layer has it's own mechanism, pass the IO to it.. */
|
||||
status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
|
||||
(struct hif_pending_events_info *)pIOPacket->pBuffer,
|
||||
pIOPacket);
|
||||
|
||||
} else {
|
||||
/* standard way, read the interrupt register table asynchronously again */
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
HOST_INT_STATUS_ADDRESS,
|
||||
pIOPacket->pBuffer,
|
||||
AR6K_IRQ_PROC_REGS_SIZE,
|
||||
HIF_RD_ASYNC_BYTE_INC,
|
||||
pIOPacket);
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n"));
|
||||
} while (false);
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n"));
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
void DevAsyncIrqProcessComplete(struct ar6k_device *pDev)
|
||||
{
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("DevAsyncIrqProcessComplete - forcing HIF IRQ ACK \n"));
|
||||
HIFAckInterrupt(pDev->HIFDevice);
|
||||
}
|
||||
|
||||
/* process pending interrupts synchronously */
|
||||
static int ProcessPendingIRQs(struct ar6k_device *pDev, bool *pDone, bool *pASyncProcessing)
|
||||
{
|
||||
int status = 0;
|
||||
u8 host_int_status = 0;
|
||||
u32 lookAhead = 0;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%lX)\n", (unsigned long)pDev));
|
||||
|
||||
/*** NOTE: the HIF implementation guarantees that the context of this call allows
|
||||
* us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that
|
||||
* can block or switch thread/task ontexts.
|
||||
* This is a fully schedulable context.
|
||||
* */
|
||||
do {
|
||||
|
||||
if (pDev->IrqEnableRegisters.int_status_enable == 0) {
|
||||
/* interrupt enables have been cleared, do not try to process any pending interrupts that
|
||||
* may result in more bus transactions. The target may be unresponsive at this
|
||||
* point. */
|
||||
break;
|
||||
}
|
||||
|
||||
if (pDev->GetPendingEventsFunc != NULL) {
|
||||
struct hif_pending_events_info events;
|
||||
|
||||
#ifdef THREAD_X
|
||||
events.Polling= 0;
|
||||
#endif
|
||||
/* the HIF layer uses a special mechanism to get events
|
||||
* get this synchronously */
|
||||
status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
|
||||
&events,
|
||||
NULL);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (events.Events & HIF_RECV_MSG_AVAIL) {
|
||||
lookAhead = events.LookAhead;
|
||||
if (0 == lookAhead) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n"));
|
||||
}
|
||||
}
|
||||
|
||||
if (!(events.Events & HIF_OTHER_EVENTS) ||
|
||||
!(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) {
|
||||
/* no need to read the register table, no other interesting interrupts.
|
||||
* Some interfaces (like SPI) can shadow interrupt sources without
|
||||
* requiring the host to do a full table read */
|
||||
break;
|
||||
}
|
||||
|
||||
/* otherwise fall through and read the register table */
|
||||
}
|
||||
|
||||
/*
|
||||
* Read the first 28 bytes of the HTC register table. This will yield us
|
||||
* the value of different int status registers and the lookahead
|
||||
* registers.
|
||||
* length = sizeof(int_status) + sizeof(cpu_int_status) +
|
||||
* sizeof(error_int_status) + sizeof(counter_int_status) +
|
||||
* sizeof(mbox_frame) + sizeof(rx_lookahead_valid) +
|
||||
* sizeof(hole) + sizeof(rx_lookahead) +
|
||||
* sizeof(int_status_enable) + sizeof(cpu_int_status_enable) +
|
||||
* sizeof(error_status_enable) +
|
||||
* sizeof(counter_int_status_enable);
|
||||
*
|
||||
*/
|
||||
#ifdef CONFIG_MMC_SDHCI_S3C
|
||||
pDev->IrqProcRegisters.host_int_status = 0;
|
||||
pDev->IrqProcRegisters.rx_lookahead_valid = 0;
|
||||
pDev->IrqProcRegisters.host_int_status2 = 0;
|
||||
pDev->IrqProcRegisters.rx_lookahead[0] = 0;
|
||||
pDev->IrqProcRegisters.rx_lookahead[1] = 0xaaa5555;
|
||||
#endif /* CONFIG_MMC_SDHCI_S3C */
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
HOST_INT_STATUS_ADDRESS,
|
||||
(u8 *)&pDev->IrqProcRegisters,
|
||||
AR6K_IRQ_PROC_REGS_SIZE,
|
||||
HIF_RD_SYNC_BYTE_INC,
|
||||
NULL);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ATH_DEBUG_MODULE
|
||||
if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) {
|
||||
DevDumpRegisters(pDev,
|
||||
&pDev->IrqProcRegisters,
|
||||
&pDev->IrqEnableRegisters);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Update only those registers that are enabled */
|
||||
host_int_status = pDev->IrqProcRegisters.host_int_status &
|
||||
pDev->IrqEnableRegisters.int_status_enable;
|
||||
|
||||
if (NULL == pDev->GetPendingEventsFunc) {
|
||||
/* only look at mailbox status if the HIF layer did not provide this function,
|
||||
* on some HIF interfaces reading the RX lookahead is not valid to do */
|
||||
if (host_int_status & (1 << HTC_MAILBOX)) {
|
||||
/* mask out pending mailbox value, we use "lookAhead" as the real flag for
|
||||
* mailbox processing below */
|
||||
host_int_status &= ~(1 << HTC_MAILBOX);
|
||||
if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) {
|
||||
/* mailbox has a message and the look ahead is valid */
|
||||
lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
|
||||
if (0 == lookAhead) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n"));
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* not valid to check if the HIF has another mechanism for reading mailbox pending status*/
|
||||
host_int_status &= ~(1 << HTC_MAILBOX);
|
||||
}
|
||||
|
||||
if (pDev->GMboxEnabled) {
|
||||
/*call GMBOX layer to process any interrupts of interest */
|
||||
status = DevCheckGMboxInterrupts(pDev);
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
|
||||
do {
|
||||
|
||||
/* did the interrupt status fetches succeed? */
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
if ((0 == host_int_status) && (0 == lookAhead)) {
|
||||
/* nothing to process, the caller can use this to break out of a loop */
|
||||
*pDone = true;
|
||||
break;
|
||||
}
|
||||
|
||||
if (lookAhead != 0) {
|
||||
int fetched = 0;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead));
|
||||
/* Mailbox Interrupt, the HTC layer may issue async requests to empty the
|
||||
* mailbox...
|
||||
* When emptying the recv mailbox we use the async handler above called from the
|
||||
* completion routine of the callers read request. This can improve performance
|
||||
* by reducing context switching when we rapidly pull packets */
|
||||
status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, pASyncProcessing, &fetched);
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (!fetched) {
|
||||
/* HTC could not pull any messages out due to lack of resources */
|
||||
/* force DSR handler to ack the interrupt */
|
||||
*pASyncProcessing = false;
|
||||
pDev->RecheckIRQStatusCnt = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* now handle the rest of them */
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
|
||||
(" Valid interrupt source(s) for OTHER interrupts: 0x%x\n",
|
||||
host_int_status));
|
||||
|
||||
if (HOST_INT_STATUS_CPU_GET(host_int_status)) {
|
||||
/* CPU Interrupt */
|
||||
status = DevServiceCPUInterrupt(pDev);
|
||||
if (status){
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (HOST_INT_STATUS_ERROR_GET(host_int_status)) {
|
||||
/* Error Interrupt */
|
||||
status = DevServiceErrorInterrupt(pDev);
|
||||
if (status){
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) {
|
||||
/* Counter Interrupt */
|
||||
status = DevServiceCounterInterrupt(pDev);
|
||||
if (status){
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
/* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
|
||||
* the target, if upper layers determine that we are in a low-throughput mode, we can
|
||||
* rely on taking another interrupt rather than re-checking the status registers which can
|
||||
* re-wake the target.
|
||||
*
|
||||
* NOTE : for host interfaces that use the special GetPendingEventsFunc, this optimization cannot
|
||||
* be used due to possible side-effects. For example, SPI requires the host to drain all
|
||||
* messages from the mailbox before exiting the ISR routine. */
|
||||
if (!(*pASyncProcessing) && (pDev->RecheckIRQStatusCnt == 0) && (pDev->GetPendingEventsFunc == NULL)) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, forcing done \n"));
|
||||
*pDone = true;
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n",
|
||||
*pDone, *pASyncProcessing, status));
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/
|
||||
int DevDsrHandler(void *context)
|
||||
{
|
||||
struct ar6k_device *pDev = (struct ar6k_device *)context;
|
||||
int status = 0;
|
||||
bool done = false;
|
||||
bool asyncProc = false;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
|
||||
|
||||
/* reset the recv counter that tracks when we need to yield from the DSR */
|
||||
pDev->CurrentDSRRecvCount = 0;
|
||||
/* reset counter used to flag a re-scan of IRQ status registers on the target */
|
||||
pDev->RecheckIRQStatusCnt = 0;
|
||||
|
||||
while (!done) {
|
||||
status = ProcessPendingIRQs(pDev, &done, &asyncProc);
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
|
||||
/* the HIF layer does not allow async IRQ processing, override the asyncProc flag */
|
||||
asyncProc = false;
|
||||
/* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers.
|
||||
* this has a nice side effect of blocking us until all async read requests are completed.
|
||||
* This behavior is required on some HIF implementations that do not allow ASYNC
|
||||
* processing in interrupt handlers (like Windows CE) */
|
||||
|
||||
if (pDev->DSRCanYield && DEV_CHECK_RECV_YIELD(pDev)) {
|
||||
/* ProcessPendingIRQs() pulled enough recv messages to satisfy the yield count, stop
|
||||
* checking for more messages and return */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (asyncProc) {
|
||||
/* the function performed some async I/O for performance, we
|
||||
need to exit the ISR immediately, the check below will prevent the interrupt from being
|
||||
Ack'd while we handle it asynchronously */
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (!status && !asyncProc) {
|
||||
/* Ack the interrupt only if :
|
||||
* 1. we did not get any errors in processing interrupts
|
||||
* 2. there are no outstanding async processing requests */
|
||||
if (pDev->DSRCanYield) {
|
||||
/* if the DSR can yield do not ACK the interrupt, there could be more pending messages.
|
||||
* The HIF layer must ACK the interrupt on behalf of HTC */
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Yield in effect (cur RX count: %d) \n", pDev->CurrentDSRRecvCount));
|
||||
} else {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n"));
|
||||
HIFAckInterrupt(pDev->HIFDevice);
|
||||
}
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n"));
|
||||
return status;
|
||||
}
|
||||
|
||||
#ifdef ATH_DEBUG_MODULE
|
||||
void DumpAR6KDevState(struct ar6k_device *pDev)
|
||||
{
|
||||
int status;
|
||||
struct ar6k_irq_enable_registers regs;
|
||||
struct ar6k_irq_proc_registers procRegs;
|
||||
|
||||
LOCK_AR6K(pDev);
|
||||
/* copy into our temp area */
|
||||
memcpy(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
|
||||
UNLOCK_AR6K(pDev);
|
||||
|
||||
/* load the register table from the device */
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
HOST_INT_STATUS_ADDRESS,
|
||||
(u8 *)&procRegs,
|
||||
AR6K_IRQ_PROC_REGS_SIZE,
|
||||
HIF_RD_SYNC_BYTE_INC,
|
||||
NULL);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
("DumpAR6KDevState : Failed to read register table (%d) \n",status));
|
||||
return;
|
||||
}
|
||||
|
||||
DevDumpRegisters(pDev,&procRegs,®s);
|
||||
|
||||
if (pDev->GMboxInfo.pStateDumpCallback != NULL) {
|
||||
pDev->GMboxInfo.pStateDumpCallback(pDev->GMboxInfo.pProtocolContext);
|
||||
}
|
||||
|
||||
/* dump any bus state at the HIF layer */
|
||||
HIFConfigureDevice(pDev->HIFDevice,HIF_DEVICE_DEBUG_BUS_STATE,NULL,0);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1,755 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="ar6k_gmbox.c" company="Atheros">
|
||||
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Generic MBOX API implementation
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#include "a_config.h"
|
||||
#include "athdefs.h"
|
||||
#include "a_osapi.h"
|
||||
#include "../htc_debug.h"
|
||||
#include "hif.h"
|
||||
#include "htc_packet.h"
|
||||
#include "ar6k.h"
|
||||
#include "hw/mbox_host_reg.h"
|
||||
#include "gmboxif.h"
|
||||
|
||||
/*
|
||||
* This file provides management functions and a toolbox for GMBOX protocol modules.
|
||||
* Only one protocol module can be installed at a time. The determination of which protocol
|
||||
* module is installed is determined at compile time.
|
||||
*
|
||||
*/
|
||||
#ifdef ATH_AR6K_ENABLE_GMBOX
|
||||
/* GMBOX definitions */
|
||||
#define GMBOX_INT_STATUS_ENABLE_REG 0x488
|
||||
#define GMBOX_INT_STATUS_RX_DATA (1 << 0)
|
||||
#define GMBOX_INT_STATUS_TX_OVERFLOW (1 << 1)
|
||||
#define GMBOX_INT_STATUS_RX_OVERFLOW (1 << 2)
|
||||
|
||||
#define GMBOX_LOOKAHEAD_MUX_REG 0x498
|
||||
#define GMBOX_LA_MUX_OVERRIDE_2_3 (1 << 0)
|
||||
|
||||
#define AR6K_GMBOX_CREDIT_DEC_ADDRESS (COUNT_DEC_ADDRESS + 4 * AR6K_GMBOX_CREDIT_COUNTER)
|
||||
#define AR6K_GMBOX_CREDIT_SIZE_ADDRESS (COUNT_ADDRESS + AR6K_GMBOX_CREDIT_SIZE_COUNTER)
|
||||
|
||||
|
||||
/* external APIs for allocating and freeing internal I/O packets to handle ASYNC I/O */
|
||||
extern void AR6KFreeIOPacket(struct ar6k_device *pDev, struct htc_packet *pPacket);
|
||||
extern struct htc_packet *AR6KAllocIOPacket(struct ar6k_device *pDev);
|
||||
|
||||
|
||||
/* callback when our fetch to enable/disable completes */
|
||||
static void DevGMboxIRQActionAsyncHandler(void *Context, struct htc_packet *pPacket)
|
||||
{
|
||||
struct ar6k_device *pDev = (struct ar6k_device *)Context;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGMboxIRQActionAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
|
||||
|
||||
if (pPacket->Status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
("IRQAction Operation (%d) failed! status:%d \n", pPacket->PktInfo.AsRx.HTCRxFlags,pPacket->Status));
|
||||
}
|
||||
/* free this IO packet */
|
||||
AR6KFreeIOPacket(pDev,pPacket);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGMboxIRQActionAsyncHandler \n"));
|
||||
}
|
||||
|
||||
static int DevGMboxCounterEnableDisable(struct ar6k_device *pDev, GMBOX_IRQ_ACTION_TYPE IrqAction, bool AsyncMode)
|
||||
{
|
||||
int status = 0;
|
||||
struct ar6k_irq_enable_registers regs;
|
||||
struct htc_packet *pIOPacket = NULL;
|
||||
|
||||
LOCK_AR6K(pDev);
|
||||
|
||||
if (GMBOX_CREDIT_IRQ_ENABLE == IrqAction) {
|
||||
pDev->GMboxInfo.CreditCountIRQEnabled = true;
|
||||
pDev->IrqEnableRegisters.counter_int_status_enable |=
|
||||
COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER);
|
||||
pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_COUNTER_SET(0x01);
|
||||
} else {
|
||||
pDev->GMboxInfo.CreditCountIRQEnabled = false;
|
||||
pDev->IrqEnableRegisters.counter_int_status_enable &=
|
||||
~(COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER));
|
||||
}
|
||||
/* copy into our temp area */
|
||||
memcpy(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
|
||||
|
||||
UNLOCK_AR6K(pDev);
|
||||
|
||||
do {
|
||||
|
||||
if (AsyncMode) {
|
||||
|
||||
pIOPacket = AR6KAllocIOPacket(pDev);
|
||||
|
||||
if (NULL == pIOPacket) {
|
||||
status = A_NO_MEMORY;
|
||||
A_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
|
||||
/* copy values to write to our async I/O buffer */
|
||||
memcpy(pIOPacket->pBuffer,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
|
||||
|
||||
/* stick in our completion routine when the I/O operation completes */
|
||||
pIOPacket->Completion = DevGMboxIRQActionAsyncHandler;
|
||||
pIOPacket->pContext = pDev;
|
||||
pIOPacket->PktInfo.AsRx.HTCRxFlags = IrqAction;
|
||||
/* write it out asynchronously */
|
||||
HIFReadWrite(pDev->HIFDevice,
|
||||
INT_STATUS_ENABLE_ADDRESS,
|
||||
pIOPacket->pBuffer,
|
||||
AR6K_IRQ_ENABLE_REGS_SIZE,
|
||||
HIF_WR_ASYNC_BYTE_INC,
|
||||
pIOPacket);
|
||||
|
||||
pIOPacket = NULL;
|
||||
break;
|
||||
}
|
||||
|
||||
/* if we get here we are doing it synchronously */
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
INT_STATUS_ENABLE_ADDRESS,
|
||||
®s.int_status_enable,
|
||||
AR6K_IRQ_ENABLE_REGS_SIZE,
|
||||
HIF_WR_SYNC_BYTE_INC,
|
||||
NULL);
|
||||
} while (false);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
(" IRQAction Operation (%d) failed! status:%d \n", IrqAction, status));
|
||||
} else {
|
||||
if (!AsyncMode) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
|
||||
(" IRQAction Operation (%d) success \n", IrqAction));
|
||||
}
|
||||
}
|
||||
|
||||
if (pIOPacket != NULL) {
|
||||
AR6KFreeIOPacket(pDev,pIOPacket);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
int DevGMboxIRQAction(struct ar6k_device *pDev, GMBOX_IRQ_ACTION_TYPE IrqAction, bool AsyncMode)
|
||||
{
|
||||
int status = 0;
|
||||
struct htc_packet *pIOPacket = NULL;
|
||||
u8 GMboxIntControl[4];
|
||||
|
||||
if (GMBOX_CREDIT_IRQ_ENABLE == IrqAction) {
|
||||
return DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_ENABLE, AsyncMode);
|
||||
} else if(GMBOX_CREDIT_IRQ_DISABLE == IrqAction) {
|
||||
return DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_DISABLE, AsyncMode);
|
||||
}
|
||||
|
||||
if (GMBOX_DISABLE_ALL == IrqAction) {
|
||||
/* disable credit IRQ, those are on a different set of registers */
|
||||
DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_DISABLE, AsyncMode);
|
||||
}
|
||||
|
||||
/* take the lock to protect interrupt enable shadows */
|
||||
LOCK_AR6K(pDev);
|
||||
|
||||
switch (IrqAction) {
|
||||
|
||||
case GMBOX_DISABLE_ALL:
|
||||
pDev->GMboxControlRegisters.int_status_enable = 0;
|
||||
break;
|
||||
case GMBOX_ERRORS_IRQ_ENABLE:
|
||||
pDev->GMboxControlRegisters.int_status_enable |= GMBOX_INT_STATUS_TX_OVERFLOW |
|
||||
GMBOX_INT_STATUS_RX_OVERFLOW;
|
||||
break;
|
||||
case GMBOX_RECV_IRQ_ENABLE:
|
||||
pDev->GMboxControlRegisters.int_status_enable |= GMBOX_INT_STATUS_RX_DATA;
|
||||
break;
|
||||
case GMBOX_RECV_IRQ_DISABLE:
|
||||
pDev->GMboxControlRegisters.int_status_enable &= ~GMBOX_INT_STATUS_RX_DATA;
|
||||
break;
|
||||
case GMBOX_ACTION_NONE:
|
||||
default:
|
||||
A_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
|
||||
GMboxIntControl[0] = pDev->GMboxControlRegisters.int_status_enable;
|
||||
GMboxIntControl[1] = GMboxIntControl[0];
|
||||
GMboxIntControl[2] = GMboxIntControl[0];
|
||||
GMboxIntControl[3] = GMboxIntControl[0];
|
||||
|
||||
UNLOCK_AR6K(pDev);
|
||||
|
||||
do {
|
||||
|
||||
if (AsyncMode) {
|
||||
|
||||
pIOPacket = AR6KAllocIOPacket(pDev);
|
||||
|
||||
if (NULL == pIOPacket) {
|
||||
status = A_NO_MEMORY;
|
||||
A_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
|
||||
/* copy values to write to our async I/O buffer */
|
||||
memcpy(pIOPacket->pBuffer,GMboxIntControl,sizeof(GMboxIntControl));
|
||||
|
||||
/* stick in our completion routine when the I/O operation completes */
|
||||
pIOPacket->Completion = DevGMboxIRQActionAsyncHandler;
|
||||
pIOPacket->pContext = pDev;
|
||||
pIOPacket->PktInfo.AsRx.HTCRxFlags = IrqAction;
|
||||
/* write it out asynchronously */
|
||||
HIFReadWrite(pDev->HIFDevice,
|
||||
GMBOX_INT_STATUS_ENABLE_REG,
|
||||
pIOPacket->pBuffer,
|
||||
sizeof(GMboxIntControl),
|
||||
HIF_WR_ASYNC_BYTE_FIX,
|
||||
pIOPacket);
|
||||
pIOPacket = NULL;
|
||||
break;
|
||||
}
|
||||
|
||||
/* if we get here we are doing it synchronously */
|
||||
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
GMBOX_INT_STATUS_ENABLE_REG,
|
||||
GMboxIntControl,
|
||||
sizeof(GMboxIntControl),
|
||||
HIF_WR_SYNC_BYTE_FIX,
|
||||
NULL);
|
||||
|
||||
} while (false);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
(" IRQAction Operation (%d) failed! status:%d \n", IrqAction, status));
|
||||
} else {
|
||||
if (!AsyncMode) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
|
||||
(" IRQAction Operation (%d) success \n", IrqAction));
|
||||
}
|
||||
}
|
||||
|
||||
if (pIOPacket != NULL) {
|
||||
AR6KFreeIOPacket(pDev,pIOPacket);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
void DevCleanupGMbox(struct ar6k_device *pDev)
|
||||
{
|
||||
if (pDev->GMboxEnabled) {
|
||||
pDev->GMboxEnabled = false;
|
||||
GMboxProtocolUninstall(pDev);
|
||||
}
|
||||
}
|
||||
|
||||
int DevSetupGMbox(struct ar6k_device *pDev)
|
||||
{
|
||||
int status = 0;
|
||||
u8 muxControl[4];
|
||||
|
||||
do {
|
||||
|
||||
if (0 == pDev->MailBoxInfo.GMboxAddress) {
|
||||
break;
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,(" GMBOX Advertised: Address:0x%X , size:%d \n",
|
||||
pDev->MailBoxInfo.GMboxAddress, pDev->MailBoxInfo.GMboxSize));
|
||||
|
||||
status = DevGMboxIRQAction(pDev, GMBOX_DISABLE_ALL, PROC_IO_SYNC);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
/* write to mailbox look ahead mux control register, we want the
|
||||
* GMBOX lookaheads to appear on lookaheads 2 and 3
|
||||
* the register is 1-byte wide so we need to hit it 4 times to align the operation
|
||||
* to 4-bytes */
|
||||
muxControl[0] = GMBOX_LA_MUX_OVERRIDE_2_3;
|
||||
muxControl[1] = GMBOX_LA_MUX_OVERRIDE_2_3;
|
||||
muxControl[2] = GMBOX_LA_MUX_OVERRIDE_2_3;
|
||||
muxControl[3] = GMBOX_LA_MUX_OVERRIDE_2_3;
|
||||
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
GMBOX_LOOKAHEAD_MUX_REG,
|
||||
muxControl,
|
||||
sizeof(muxControl),
|
||||
HIF_WR_SYNC_BYTE_FIX, /* hit this register 4 times */
|
||||
NULL);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
status = GMboxProtocolInstall(pDev);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
pDev->GMboxEnabled = true;
|
||||
|
||||
} while (false);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int DevCheckGMboxInterrupts(struct ar6k_device *pDev)
|
||||
{
|
||||
int status = 0;
|
||||
u8 counter_int_status;
|
||||
int credits;
|
||||
u8 host_int_status2;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("+DevCheckGMboxInterrupts \n"));
|
||||
|
||||
/* the caller guarantees that this is a context that allows for blocking I/O */
|
||||
|
||||
do {
|
||||
|
||||
host_int_status2 = pDev->IrqProcRegisters.host_int_status2 &
|
||||
pDev->GMboxControlRegisters.int_status_enable;
|
||||
|
||||
if (host_int_status2 & GMBOX_INT_STATUS_TX_OVERFLOW) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("GMBOX : TX Overflow \n"));
|
||||
status = A_ECOMM;
|
||||
}
|
||||
|
||||
if (host_int_status2 & GMBOX_INT_STATUS_RX_OVERFLOW) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("GMBOX : RX Overflow \n"));
|
||||
status = A_ECOMM;
|
||||
}
|
||||
|
||||
if (status) {
|
||||
if (pDev->GMboxInfo.pTargetFailureCallback != NULL) {
|
||||
pDev->GMboxInfo.pTargetFailureCallback(pDev->GMboxInfo.pProtocolContext, status);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (host_int_status2 & GMBOX_INT_STATUS_RX_DATA) {
|
||||
if (pDev->IrqProcRegisters.gmbox_rx_avail > 0) {
|
||||
A_ASSERT(pDev->GMboxInfo.pMessagePendingCallBack != NULL);
|
||||
status = pDev->GMboxInfo.pMessagePendingCallBack(
|
||||
pDev->GMboxInfo.pProtocolContext,
|
||||
(u8 *)&pDev->IrqProcRegisters.rx_gmbox_lookahead_alias[0],
|
||||
pDev->IrqProcRegisters.gmbox_rx_avail);
|
||||
}
|
||||
}
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
counter_int_status = pDev->IrqProcRegisters.counter_int_status &
|
||||
pDev->IrqEnableRegisters.counter_int_status_enable;
|
||||
|
||||
/* check if credit interrupt is pending */
|
||||
if (counter_int_status & (COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER))) {
|
||||
|
||||
/* do synchronous read */
|
||||
status = DevGMboxReadCreditCounter(pDev, PROC_IO_SYNC, &credits);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
A_ASSERT(pDev->GMboxInfo.pCreditsPendingCallback != NULL);
|
||||
status = pDev->GMboxInfo.pCreditsPendingCallback(pDev->GMboxInfo.pProtocolContext,
|
||||
credits,
|
||||
pDev->GMboxInfo.CreditCountIRQEnabled);
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("-DevCheckGMboxInterrupts (%d) \n",status));
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
int DevGMboxWrite(struct ar6k_device *pDev, struct htc_packet *pPacket, u32 WriteLength)
|
||||
{
|
||||
u32 paddedLength;
|
||||
bool sync = (pPacket->Completion == NULL) ? true : false;
|
||||
int status;
|
||||
u32 address;
|
||||
|
||||
/* adjust the length to be a multiple of block size if appropriate */
|
||||
paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, WriteLength);
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
|
||||
("DevGMboxWrite, Padded Length: %d Mbox:0x%X (mode:%s)\n",
|
||||
WriteLength,
|
||||
pDev->MailBoxInfo.GMboxAddress,
|
||||
sync ? "SYNC" : "ASYNC"));
|
||||
|
||||
/* last byte of packet has to hit the EOM marker */
|
||||
address = pDev->MailBoxInfo.GMboxAddress + pDev->MailBoxInfo.GMboxSize - paddedLength;
|
||||
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
address,
|
||||
pPacket->pBuffer,
|
||||
paddedLength, /* the padded length */
|
||||
sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
|
||||
sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
|
||||
|
||||
if (sync) {
|
||||
pPacket->Status = status;
|
||||
} else {
|
||||
if (status == A_PENDING) {
|
||||
status = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int DevGMboxRead(struct ar6k_device *pDev, struct htc_packet *pPacket, u32 ReadLength)
|
||||
{
|
||||
|
||||
u32 paddedLength;
|
||||
int status;
|
||||
bool sync = (pPacket->Completion == NULL) ? true : false;
|
||||
|
||||
/* adjust the length to be a multiple of block size if appropriate */
|
||||
paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, ReadLength);
|
||||
|
||||
if (paddedLength > pPacket->BufferLength) {
|
||||
A_ASSERT(false);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
("DevGMboxRead, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
|
||||
paddedLength,ReadLength,pPacket->BufferLength));
|
||||
if (pPacket->Completion != NULL) {
|
||||
COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
|
||||
return 0;
|
||||
}
|
||||
return A_EINVAL;
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
|
||||
("DevGMboxRead (0x%lX : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n",
|
||||
(unsigned long)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr,
|
||||
paddedLength,
|
||||
pDev->MailBoxInfo.GMboxAddress,
|
||||
sync ? "SYNC" : "ASYNC"));
|
||||
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
pDev->MailBoxInfo.GMboxAddress,
|
||||
pPacket->pBuffer,
|
||||
paddedLength,
|
||||
sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX,
|
||||
sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
|
||||
|
||||
if (sync) {
|
||||
pPacket->Status = status;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
static int ProcessCreditCounterReadBuffer(u8 *pBuffer, int Length)
|
||||
{
|
||||
int credits = 0;
|
||||
|
||||
/* theory of how this works:
|
||||
* We read the credit decrement register multiple times on a byte-wide basis.
|
||||
* The number of times (32) aligns the I/O operation to be a multiple of 4 bytes and provides a
|
||||
* reasonable chance to acquire "all" pending credits in a single I/O operation.
|
||||
*
|
||||
* Once we obtain the filled buffer, we can walk through it looking for credit decrement transitions.
|
||||
* Each non-zero byte represents a single credit decrement (which is a credit given back to the host)
|
||||
* For example if the target provides 3 credits and added 4 more during the 32-byte read operation the following
|
||||
* pattern "could" appear:
|
||||
*
|
||||
* 0x3 0x2 0x1 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 ......rest zeros
|
||||
* <---------> <----------------------------->
|
||||
* \_ credits aleady there \_ target adding 4 more credits
|
||||
*
|
||||
* The total available credits would be 7, since there are 7 non-zero bytes in the buffer.
|
||||
*
|
||||
* */
|
||||
|
||||
if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
|
||||
DebugDumpBytes(pBuffer, Length, "GMBOX Credit read buffer");
|
||||
}
|
||||
|
||||
while (Length) {
|
||||
if (*pBuffer != 0) {
|
||||
credits++;
|
||||
}
|
||||
Length--;
|
||||
pBuffer++;
|
||||
}
|
||||
|
||||
return credits;
|
||||
}
|
||||
|
||||
|
||||
/* callback when our fetch to enable/disable completes */
|
||||
static void DevGMboxReadCreditsAsyncHandler(void *Context, struct htc_packet *pPacket)
|
||||
{
|
||||
struct ar6k_device *pDev = (struct ar6k_device *)Context;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGMboxReadCreditsAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
|
||||
|
||||
if (pPacket->Status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
("Read Credit Operation failed! status:%d \n", pPacket->Status));
|
||||
} else {
|
||||
int credits = 0;
|
||||
credits = ProcessCreditCounterReadBuffer(pPacket->pBuffer, AR6K_REG_IO_BUFFER_SIZE);
|
||||
pDev->GMboxInfo.pCreditsPendingCallback(pDev->GMboxInfo.pProtocolContext,
|
||||
credits,
|
||||
pDev->GMboxInfo.CreditCountIRQEnabled);
|
||||
|
||||
|
||||
}
|
||||
/* free this IO packet */
|
||||
AR6KFreeIOPacket(pDev,pPacket);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGMboxReadCreditsAsyncHandler \n"));
|
||||
}
|
||||
|
||||
int DevGMboxReadCreditCounter(struct ar6k_device *pDev, bool AsyncMode, int *pCredits)
|
||||
{
|
||||
int status = 0;
|
||||
struct htc_packet *pIOPacket = NULL;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+DevGMboxReadCreditCounter (%s) \n", AsyncMode ? "ASYNC" : "SYNC"));
|
||||
|
||||
do {
|
||||
|
||||
pIOPacket = AR6KAllocIOPacket(pDev);
|
||||
|
||||
if (NULL == pIOPacket) {
|
||||
status = A_NO_MEMORY;
|
||||
A_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
|
||||
A_MEMZERO(pIOPacket->pBuffer,AR6K_REG_IO_BUFFER_SIZE);
|
||||
|
||||
if (AsyncMode) {
|
||||
/* stick in our completion routine when the I/O operation completes */
|
||||
pIOPacket->Completion = DevGMboxReadCreditsAsyncHandler;
|
||||
pIOPacket->pContext = pDev;
|
||||
/* read registers asynchronously */
|
||||
HIFReadWrite(pDev->HIFDevice,
|
||||
AR6K_GMBOX_CREDIT_DEC_ADDRESS,
|
||||
pIOPacket->pBuffer,
|
||||
AR6K_REG_IO_BUFFER_SIZE, /* hit the register multiple times */
|
||||
HIF_RD_ASYNC_BYTE_FIX,
|
||||
pIOPacket);
|
||||
pIOPacket = NULL;
|
||||
break;
|
||||
}
|
||||
|
||||
pIOPacket->Completion = NULL;
|
||||
/* if we get here we are doing it synchronously */
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
AR6K_GMBOX_CREDIT_DEC_ADDRESS,
|
||||
pIOPacket->pBuffer,
|
||||
AR6K_REG_IO_BUFFER_SIZE,
|
||||
HIF_RD_SYNC_BYTE_FIX,
|
||||
NULL);
|
||||
} while (false);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
(" DevGMboxReadCreditCounter failed! status:%d \n", status));
|
||||
}
|
||||
|
||||
if (pIOPacket != NULL) {
|
||||
if (!status) {
|
||||
/* sync mode processing */
|
||||
*pCredits = ProcessCreditCounterReadBuffer(pIOPacket->pBuffer, AR6K_REG_IO_BUFFER_SIZE);
|
||||
}
|
||||
AR6KFreeIOPacket(pDev,pIOPacket);
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-DevGMboxReadCreditCounter (%s) (%d) \n",
|
||||
AsyncMode ? "ASYNC" : "SYNC", status));
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int DevGMboxReadCreditSize(struct ar6k_device *pDev, int *pCreditSize)
|
||||
{
|
||||
int status;
|
||||
u8 buffer[4];
|
||||
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
AR6K_GMBOX_CREDIT_SIZE_ADDRESS,
|
||||
buffer,
|
||||
sizeof(buffer),
|
||||
HIF_RD_SYNC_BYTE_FIX, /* hit the register 4 times to align the I/O */
|
||||
NULL);
|
||||
|
||||
if (!status) {
|
||||
if (buffer[0] == 0) {
|
||||
*pCreditSize = 256;
|
||||
} else {
|
||||
*pCreditSize = buffer[0];
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
void DevNotifyGMboxTargetFailure(struct ar6k_device *pDev)
|
||||
{
|
||||
/* Target ASSERTED!!! */
|
||||
if (pDev->GMboxInfo.pTargetFailureCallback != NULL) {
|
||||
pDev->GMboxInfo.pTargetFailureCallback(pDev->GMboxInfo.pProtocolContext, A_HARDWARE);
|
||||
}
|
||||
}
|
||||
|
||||
int DevGMboxRecvLookAheadPeek(struct ar6k_device *pDev, u8 *pLookAheadBuffer, int *pLookAheadBytes)
|
||||
{
|
||||
|
||||
int status = 0;
|
||||
struct ar6k_irq_proc_registers procRegs;
|
||||
int maxCopy;
|
||||
|
||||
do {
|
||||
/* on entry the caller provides the length of the lookahead buffer */
|
||||
if (*pLookAheadBytes > sizeof(procRegs.rx_gmbox_lookahead_alias)) {
|
||||
A_ASSERT(false);
|
||||
status = A_EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
maxCopy = *pLookAheadBytes;
|
||||
*pLookAheadBytes = 0;
|
||||
/* load the register table from the device */
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
HOST_INT_STATUS_ADDRESS,
|
||||
(u8 *)&procRegs,
|
||||
AR6K_IRQ_PROC_REGS_SIZE,
|
||||
HIF_RD_SYNC_BYTE_INC,
|
||||
NULL);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
("DevGMboxRecvLookAheadPeek : Failed to read register table (%d) \n",status));
|
||||
break;
|
||||
}
|
||||
|
||||
if (procRegs.gmbox_rx_avail > 0) {
|
||||
int bytes = procRegs.gmbox_rx_avail > maxCopy ? maxCopy : procRegs.gmbox_rx_avail;
|
||||
memcpy(pLookAheadBuffer,&procRegs.rx_gmbox_lookahead_alias[0],bytes);
|
||||
*pLookAheadBytes = bytes;
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int DevGMboxSetTargetInterrupt(struct ar6k_device *pDev, int Signal, int AckTimeoutMS)
|
||||
{
|
||||
int status = 0;
|
||||
int i;
|
||||
u8 buffer[4];
|
||||
|
||||
A_MEMZERO(buffer, sizeof(buffer));
|
||||
|
||||
do {
|
||||
|
||||
if (Signal >= MBOX_SIG_HCI_BRIDGE_MAX) {
|
||||
status = A_EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
/* set the last buffer to do the actual signal trigger */
|
||||
buffer[3] = (1 << Signal);
|
||||
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
INT_WLAN_ADDRESS,
|
||||
buffer,
|
||||
sizeof(buffer),
|
||||
HIF_WR_SYNC_BYTE_FIX, /* hit the register 4 times to align the I/O */
|
||||
NULL);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
|
||||
if (!status) {
|
||||
/* now read back the register to see if the bit cleared */
|
||||
while (AckTimeoutMS) {
|
||||
status = HIFReadWrite(pDev->HIFDevice,
|
||||
INT_WLAN_ADDRESS,
|
||||
buffer,
|
||||
sizeof(buffer),
|
||||
HIF_RD_SYNC_BYTE_FIX,
|
||||
NULL);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
for (i = 0; i < sizeof(buffer); i++) {
|
||||
if (buffer[i] & (1 << Signal)) {
|
||||
/* bit is still set */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i >= sizeof(buffer)) {
|
||||
/* done */
|
||||
break;
|
||||
}
|
||||
|
||||
AckTimeoutMS--;
|
||||
A_MDELAY(1);
|
||||
}
|
||||
|
||||
if (0 == AckTimeoutMS) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
("DevGMboxSetTargetInterrupt : Ack Timed-out (sig:%d) \n",Signal));
|
||||
status = A_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
|
||||
}
|
||||
|
||||
#endif //ATH_AR6K_ENABLE_GMBOX
|
||||
|
||||
|
||||
|
||||
|
File diff suppressed because it is too large
Load diff
|
@ -1,575 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="htc.c" company="Atheros">
|
||||
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#include "htc_internal.h"
|
||||
|
||||
#ifdef ATH_DEBUG_MODULE
|
||||
static struct ath_debug_mask_description g_HTCDebugDescription[] = {
|
||||
{ ATH_DEBUG_SEND , "Send"},
|
||||
{ ATH_DEBUG_RECV , "Recv"},
|
||||
{ ATH_DEBUG_SYNC , "Sync"},
|
||||
{ ATH_DEBUG_DUMP , "Dump Data (RX or TX)"},
|
||||
{ ATH_DEBUG_IRQ , "Interrupt Processing"}
|
||||
};
|
||||
|
||||
ATH_DEBUG_INSTANTIATE_MODULE_VAR(htc,
|
||||
"htc",
|
||||
"Host Target Communications",
|
||||
ATH_DEBUG_MASK_DEFAULTS,
|
||||
ATH_DEBUG_DESCRIPTION_COUNT(g_HTCDebugDescription),
|
||||
g_HTCDebugDescription);
|
||||
|
||||
#endif
|
||||
|
||||
static void HTCReportFailure(void *Context);
|
||||
static void ResetEndpointStates(struct htc_target *target);
|
||||
|
||||
void HTCFreeControlBuffer(struct htc_target *target, struct htc_packet *pPacket, struct htc_packet_queue *pList)
|
||||
{
|
||||
LOCK_HTC(target);
|
||||
HTC_PACKET_ENQUEUE(pList,pPacket);
|
||||
UNLOCK_HTC(target);
|
||||
}
|
||||
|
||||
struct htc_packet *HTCAllocControlBuffer(struct htc_target *target, struct htc_packet_queue *pList)
|
||||
{
|
||||
struct htc_packet *pPacket;
|
||||
|
||||
LOCK_HTC(target);
|
||||
pPacket = HTC_PACKET_DEQUEUE(pList);
|
||||
UNLOCK_HTC(target);
|
||||
|
||||
return pPacket;
|
||||
}
|
||||
|
||||
/* cleanup the HTC instance */
|
||||
static void HTCCleanup(struct htc_target *target)
|
||||
{
|
||||
s32 i;
|
||||
|
||||
DevCleanup(&target->Device);
|
||||
|
||||
for (i = 0;i < NUM_CONTROL_BUFFERS;i++) {
|
||||
if (target->HTCControlBuffers[i].Buffer) {
|
||||
kfree(target->HTCControlBuffers[i].Buffer);
|
||||
}
|
||||
}
|
||||
|
||||
if (A_IS_MUTEX_VALID(&target->HTCLock)) {
|
||||
A_MUTEX_DELETE(&target->HTCLock);
|
||||
}
|
||||
|
||||
if (A_IS_MUTEX_VALID(&target->HTCRxLock)) {
|
||||
A_MUTEX_DELETE(&target->HTCRxLock);
|
||||
}
|
||||
|
||||
if (A_IS_MUTEX_VALID(&target->HTCTxLock)) {
|
||||
A_MUTEX_DELETE(&target->HTCTxLock);
|
||||
}
|
||||
/* free our instance */
|
||||
kfree(target);
|
||||
}
|
||||
|
||||
/* registered target arrival callback from the HIF layer */
|
||||
HTC_HANDLE HTCCreate(void *hif_handle, struct htc_init_info *pInfo)
|
||||
{
|
||||
struct htc_target *target = NULL;
|
||||
int status = 0;
|
||||
int i;
|
||||
u32 ctrl_bufsz;
|
||||
u32 blocksizes[HTC_MAILBOX_NUM_MAX];
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Enter\n"));
|
||||
|
||||
A_REGISTER_MODULE_DEBUG_INFO(htc);
|
||||
|
||||
do {
|
||||
|
||||
/* allocate target memory */
|
||||
if ((target = (struct htc_target *)A_MALLOC(sizeof(struct htc_target))) == NULL) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
|
||||
status = A_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
A_MEMZERO(target, sizeof(struct htc_target));
|
||||
A_MUTEX_INIT(&target->HTCLock);
|
||||
A_MUTEX_INIT(&target->HTCRxLock);
|
||||
A_MUTEX_INIT(&target->HTCTxLock);
|
||||
INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList);
|
||||
INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList);
|
||||
|
||||
/* give device layer the hif device handle */
|
||||
target->Device.HIFDevice = hif_handle;
|
||||
/* give the device layer our context (for event processing)
|
||||
* the device layer will register it's own context with HIF
|
||||
* so we need to set this so we can fetch it in the target remove handler */
|
||||
target->Device.HTCContext = target;
|
||||
/* set device layer target failure callback */
|
||||
target->Device.TargetFailureCallback = HTCReportFailure;
|
||||
/* set device layer recv message pending callback */
|
||||
target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler;
|
||||
target->EpWaitingForBuffers = ENDPOINT_MAX;
|
||||
|
||||
memcpy(&target->HTCInitInfo,pInfo,sizeof(struct htc_init_info));
|
||||
|
||||
ResetEndpointStates(target);
|
||||
|
||||
/* setup device layer */
|
||||
status = DevSetup(&target->Device);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
/* get the block sizes */
|
||||
status = HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
|
||||
blocksizes, sizeof(blocksizes));
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get block size info from HIF layer...\n"));
|
||||
break;
|
||||
}
|
||||
|
||||
/* Set the control buffer size based on the block size */
|
||||
if (blocksizes[1] > HTC_MAX_CONTROL_MESSAGE_LENGTH) {
|
||||
ctrl_bufsz = blocksizes[1] + HTC_HDR_LENGTH;
|
||||
} else {
|
||||
ctrl_bufsz = HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH;
|
||||
}
|
||||
for (i = 0;i < NUM_CONTROL_BUFFERS;i++) {
|
||||
target->HTCControlBuffers[i].Buffer = A_MALLOC(ctrl_bufsz);
|
||||
if (target->HTCControlBuffers[i].Buffer == NULL) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
|
||||
status = A_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
/* carve up buffers/packets for control messages */
|
||||
for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) {
|
||||
struct htc_packet *pControlPacket;
|
||||
pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
|
||||
SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket,
|
||||
target,
|
||||
target->HTCControlBuffers[i].Buffer,
|
||||
ctrl_bufsz,
|
||||
ENDPOINT_0);
|
||||
HTC_FREE_CONTROL_RX(target,pControlPacket);
|
||||
}
|
||||
|
||||
for (;i < NUM_CONTROL_BUFFERS;i++) {
|
||||
struct htc_packet *pControlPacket;
|
||||
pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
|
||||
INIT_HTC_PACKET_INFO(pControlPacket,
|
||||
target->HTCControlBuffers[i].Buffer,
|
||||
ctrl_bufsz);
|
||||
HTC_FREE_CONTROL_TX(target,pControlPacket);
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
if (status) {
|
||||
if (target != NULL) {
|
||||
HTCCleanup(target);
|
||||
target = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Exit\n"));
|
||||
|
||||
return target;
|
||||
}
|
||||
|
||||
void HTCDestroy(HTC_HANDLE HTCHandle)
|
||||
{
|
||||
struct htc_target *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCDestroy .. Destroying :0x%lX \n",(unsigned long)target));
|
||||
HTCCleanup(target);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCDestroy \n"));
|
||||
}
|
||||
|
||||
/* get the low level HIF device for the caller , the caller may wish to do low level
|
||||
* HIF requests */
|
||||
void *HTCGetHifDevice(HTC_HANDLE HTCHandle)
|
||||
{
|
||||
struct htc_target *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
|
||||
return target->Device.HIFDevice;
|
||||
}
|
||||
|
||||
/* wait for the target to arrive (sends HTC Ready message)
|
||||
* this operation is fully synchronous and the message is polled for */
|
||||
int HTCWaitTarget(HTC_HANDLE HTCHandle)
|
||||
{
|
||||
struct htc_target *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
|
||||
int status;
|
||||
struct htc_packet *pPacket = NULL;
|
||||
HTC_READY_EX_MSG *pRdyMsg;
|
||||
|
||||
struct htc_service_connect_req connect;
|
||||
struct htc_service_connect_resp resp;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Enter (target:0x%lX) \n", (unsigned long)target));
|
||||
|
||||
do {
|
||||
|
||||
#ifdef MBOXHW_UNIT_TEST
|
||||
|
||||
status = DoMboxHWTest(&target->Device);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* we should be getting 1 control message that the target is ready */
|
||||
status = HTCWaitforControlMessage(target, &pPacket);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Target Not Available!!\n"));
|
||||
break;
|
||||
}
|
||||
|
||||
/* we controlled the buffer creation so it has to be properly aligned */
|
||||
pRdyMsg = (HTC_READY_EX_MSG *)pPacket->pBuffer;
|
||||
|
||||
if ((pRdyMsg->Version2_0_Info.MessageID != HTC_MSG_READY_ID) ||
|
||||
(pPacket->ActualLength < sizeof(HTC_READY_MSG))) {
|
||||
/* this message is not valid */
|
||||
AR_DEBUG_ASSERT(false);
|
||||
status = A_EPROTO;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
if (pRdyMsg->Version2_0_Info.CreditCount == 0 || pRdyMsg->Version2_0_Info.CreditSize == 0) {
|
||||
/* this message is not valid */
|
||||
AR_DEBUG_ASSERT(false);
|
||||
status = A_EPROTO;
|
||||
break;
|
||||
}
|
||||
|
||||
target->TargetCredits = pRdyMsg->Version2_0_Info.CreditCount;
|
||||
target->TargetCreditSize = pRdyMsg->Version2_0_Info.CreditSize;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_WARN, (" Target Ready: credits: %d credit size: %d\n",
|
||||
target->TargetCredits, target->TargetCreditSize));
|
||||
|
||||
/* check if this is an extended ready message */
|
||||
if (pPacket->ActualLength >= sizeof(HTC_READY_EX_MSG)) {
|
||||
/* this is an extended message */
|
||||
target->HTCTargetVersion = pRdyMsg->HTCVersion;
|
||||
target->MaxMsgPerBundle = pRdyMsg->MaxMsgsPerHTCBundle;
|
||||
} else {
|
||||
/* legacy */
|
||||
target->HTCTargetVersion = HTC_VERSION_2P0;
|
||||
target->MaxMsgPerBundle = 0;
|
||||
}
|
||||
|
||||
#ifdef HTC_FORCE_LEGACY_2P0
|
||||
/* for testing and comparison...*/
|
||||
target->HTCTargetVersion = HTC_VERSION_2P0;
|
||||
target->MaxMsgPerBundle = 0;
|
||||
#endif
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
|
||||
("Using HTC Protocol Version : %s (%d)\n ",
|
||||
(target->HTCTargetVersion == HTC_VERSION_2P0) ? "2.0" : ">= 2.1",
|
||||
target->HTCTargetVersion));
|
||||
|
||||
if (target->MaxMsgPerBundle > 0) {
|
||||
/* limit what HTC can handle */
|
||||
target->MaxMsgPerBundle = min(HTC_HOST_MAX_MSG_PER_BUNDLE, target->MaxMsgPerBundle);
|
||||
/* target supports message bundling, setup device layer */
|
||||
if (DevSetupMsgBundling(&target->Device,target->MaxMsgPerBundle)) {
|
||||
/* device layer can't handle bundling */
|
||||
target->MaxMsgPerBundle = 0;
|
||||
} else {
|
||||
/* limit bundle what the device layer can handle */
|
||||
target->MaxMsgPerBundle = min(DEV_GET_MAX_MSG_PER_BUNDLE(&target->Device),
|
||||
target->MaxMsgPerBundle);
|
||||
}
|
||||
}
|
||||
|
||||
if (target->MaxMsgPerBundle > 0) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
|
||||
(" HTC bundling allowed. Max Msg Per HTC Bundle: %d\n", target->MaxMsgPerBundle));
|
||||
|
||||
if (DEV_GET_MAX_BUNDLE_SEND_LENGTH(&target->Device) != 0) {
|
||||
target->SendBundlingEnabled = true;
|
||||
}
|
||||
if (DEV_GET_MAX_BUNDLE_RECV_LENGTH(&target->Device) != 0) {
|
||||
target->RecvBundlingEnabled = true;
|
||||
}
|
||||
|
||||
if (!DEV_IS_LEN_BLOCK_ALIGNED(&target->Device,target->TargetCreditSize)) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("*** Credit size: %d is not block aligned! Disabling send bundling \n",
|
||||
target->TargetCreditSize));
|
||||
/* disallow send bundling since the credit size is not aligned to a block size
|
||||
* the I/O block padding will spill into the next credit buffer which is fatal */
|
||||
target->SendBundlingEnabled = false;
|
||||
}
|
||||
}
|
||||
|
||||
/* setup our pseudo HTC control endpoint connection */
|
||||
A_MEMZERO(&connect,sizeof(connect));
|
||||
A_MEMZERO(&resp,sizeof(resp));
|
||||
connect.EpCallbacks.pContext = target;
|
||||
connect.EpCallbacks.EpTxComplete = HTCControlTxComplete;
|
||||
connect.EpCallbacks.EpRecv = HTCControlRecv;
|
||||
connect.EpCallbacks.EpRecvRefill = NULL; /* not needed */
|
||||
connect.EpCallbacks.EpSendFull = NULL; /* not nedded */
|
||||
connect.MaxSendQueueDepth = NUM_CONTROL_BUFFERS;
|
||||
connect.ServiceID = HTC_CTRL_RSVD_SVC;
|
||||
|
||||
/* connect fake service */
|
||||
status = HTCConnectService((HTC_HANDLE)target,
|
||||
&connect,
|
||||
&resp);
|
||||
|
||||
if (!status) {
|
||||
break;
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
if (pPacket != NULL) {
|
||||
HTC_FREE_CONTROL_RX(target,pPacket);
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Exit\n"));
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Start HTC, enable interrupts and let the target know host has finished setup */
|
||||
int HTCStart(HTC_HANDLE HTCHandle)
|
||||
{
|
||||
struct htc_target *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
|
||||
struct htc_packet *pPacket;
|
||||
int status;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n"));
|
||||
|
||||
/* make sure interrupts are disabled at the chip level,
|
||||
* this function can be called again from a reboot of the target without shutting down HTC */
|
||||
DevDisableInterrupts(&target->Device);
|
||||
/* make sure state is cleared again */
|
||||
target->OpStateFlags = 0;
|
||||
target->RecvStateFlags = 0;
|
||||
|
||||
/* now that we are starting, push control receive buffers into the
|
||||
* HTC control endpoint */
|
||||
|
||||
while (1) {
|
||||
pPacket = HTC_ALLOC_CONTROL_RX(target);
|
||||
if (NULL == pPacket) {
|
||||
break;
|
||||
}
|
||||
HTCAddReceivePkt((HTC_HANDLE)target,pPacket);
|
||||
}
|
||||
|
||||
do {
|
||||
|
||||
AR_DEBUG_ASSERT(target->InitCredits != NULL);
|
||||
AR_DEBUG_ASSERT(target->EpCreditDistributionListHead != NULL);
|
||||
AR_DEBUG_ASSERT(target->EpCreditDistributionListHead->pNext != NULL);
|
||||
|
||||
/* call init credits callback to do the distribution ,
|
||||
* NOTE: the first entry in the distribution list is ENDPOINT_0, so
|
||||
* we pass the start of the list after this one. */
|
||||
target->InitCredits(target->pCredDistContext,
|
||||
target->EpCreditDistributionListHead->pNext,
|
||||
target->TargetCredits);
|
||||
|
||||
#ifdef ATH_DEBUG_MODULE
|
||||
|
||||
if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) {
|
||||
DumpCreditDistStates(target);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* the caller is done connecting to services, so we can indicate to the
|
||||
* target that the setup phase is complete */
|
||||
status = HTCSendSetupComplete(target);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
/* unmask interrupts */
|
||||
status = DevUnmaskInterrupts(&target->Device);
|
||||
|
||||
if (status) {
|
||||
HTCStop(target);
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n"));
|
||||
return status;
|
||||
}
|
||||
|
||||
static void ResetEndpointStates(struct htc_target *target)
|
||||
{
|
||||
struct htc_endpoint *pEndpoint;
|
||||
int i;
|
||||
|
||||
for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
|
||||
pEndpoint = &target->EndPoint[i];
|
||||
|
||||
A_MEMZERO(&pEndpoint->CreditDist, sizeof(pEndpoint->CreditDist));
|
||||
pEndpoint->ServiceID = 0;
|
||||
pEndpoint->MaxMsgLength = 0;
|
||||
pEndpoint->MaxTxQueueDepth = 0;
|
||||
A_MEMZERO(&pEndpoint->EndPointStats,sizeof(pEndpoint->EndPointStats));
|
||||
INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers);
|
||||
INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue);
|
||||
INIT_HTC_PACKET_QUEUE(&pEndpoint->RecvIndicationQueue);
|
||||
pEndpoint->target = target;
|
||||
}
|
||||
/* reset distribution list */
|
||||
target->EpCreditDistributionListHead = NULL;
|
||||
}
|
||||
|
||||
/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */
|
||||
void HTCStop(HTC_HANDLE HTCHandle)
|
||||
{
|
||||
struct htc_target *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCStop \n"));
|
||||
|
||||
LOCK_HTC(target);
|
||||
/* mark that we are shutting down .. */
|
||||
target->OpStateFlags |= HTC_OP_STATE_STOPPING;
|
||||
UNLOCK_HTC(target);
|
||||
|
||||
/* Masking interrupts is a synchronous operation, when this function returns
|
||||
* all pending HIF I/O has completed, we can safely flush the queues */
|
||||
DevMaskInterrupts(&target->Device);
|
||||
|
||||
#ifdef THREAD_X
|
||||
//
|
||||
// Is this delay required
|
||||
//
|
||||
A_MDELAY(200); // wait for IRQ process done
|
||||
#endif
|
||||
/* flush all send packets */
|
||||
HTCFlushSendPkts(target);
|
||||
/* flush all recv buffers */
|
||||
HTCFlushRecvBuffers(target);
|
||||
|
||||
DevCleanupMsgBundling(&target->Device);
|
||||
|
||||
ResetEndpointStates(target);
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCStop \n"));
|
||||
}
|
||||
|
||||
#ifdef ATH_DEBUG_MODULE
|
||||
void HTCDumpCreditStates(HTC_HANDLE HTCHandle)
|
||||
{
|
||||
struct htc_target *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
|
||||
|
||||
LOCK_HTC_TX(target);
|
||||
|
||||
DumpCreditDistStates(target);
|
||||
|
||||
UNLOCK_HTC_TX(target);
|
||||
|
||||
DumpAR6KDevState(&target->Device);
|
||||
}
|
||||
#endif
|
||||
/* report a target failure from the device, this is a callback from the device layer
|
||||
* which uses a mechanism to report errors from the target (i.e. special interrupts) */
|
||||
static void HTCReportFailure(void *Context)
|
||||
{
|
||||
struct htc_target *target = (struct htc_target *)Context;
|
||||
|
||||
target->TargetFailure = true;
|
||||
|
||||
if (target->HTCInitInfo.TargetFailure != NULL) {
|
||||
/* let upper layer know, it needs to call HTCStop() */
|
||||
target->HTCInitInfo.TargetFailure(target->HTCInitInfo.pContext, A_ERROR);
|
||||
}
|
||||
}
|
||||
|
||||
bool HTCGetEndpointStatistics(HTC_HANDLE HTCHandle,
|
||||
HTC_ENDPOINT_ID Endpoint,
|
||||
HTC_ENDPOINT_STAT_ACTION Action,
|
||||
struct htc_endpoint_stats *pStats)
|
||||
{
|
||||
|
||||
struct htc_target *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
|
||||
bool clearStats = false;
|
||||
bool sample = false;
|
||||
|
||||
switch (Action) {
|
||||
case HTC_EP_STAT_SAMPLE :
|
||||
sample = true;
|
||||
break;
|
||||
case HTC_EP_STAT_SAMPLE_AND_CLEAR :
|
||||
sample = true;
|
||||
clearStats = true;
|
||||
break;
|
||||
case HTC_EP_STAT_CLEAR :
|
||||
clearStats = true;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
A_ASSERT(Endpoint < ENDPOINT_MAX);
|
||||
|
||||
/* lock out TX and RX while we sample and/or clear */
|
||||
LOCK_HTC_TX(target);
|
||||
LOCK_HTC_RX(target);
|
||||
|
||||
if (sample) {
|
||||
A_ASSERT(pStats != NULL);
|
||||
/* return the stats to the caller */
|
||||
memcpy(pStats, &target->EndPoint[Endpoint].EndPointStats, sizeof(struct htc_endpoint_stats));
|
||||
}
|
||||
|
||||
if (clearStats) {
|
||||
/* reset stats */
|
||||
A_MEMZERO(&target->EndPoint[Endpoint].EndPointStats, sizeof(struct htc_endpoint_stats));
|
||||
}
|
||||
|
||||
UNLOCK_HTC_RX(target);
|
||||
UNLOCK_HTC_TX(target);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
struct ar6k_device *HTCGetAR6KDevice(void *HTCHandle)
|
||||
{
|
||||
struct htc_target *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
|
||||
return &target->Device;
|
||||
}
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="htc_debug.h" company="Atheros">
|
||||
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef HTC_DEBUG_H_
|
||||
#define HTC_DEBUG_H_
|
||||
|
||||
#define ATH_MODULE_NAME htc
|
||||
#include "a_debug.h"
|
||||
|
||||
/* ------- Debug related stuff ------- */
|
||||
|
||||
#define ATH_DEBUG_SEND ATH_DEBUG_MAKE_MODULE_MASK(0)
|
||||
#define ATH_DEBUG_RECV ATH_DEBUG_MAKE_MODULE_MASK(1)
|
||||
#define ATH_DEBUG_SYNC ATH_DEBUG_MAKE_MODULE_MASK(2)
|
||||
#define ATH_DEBUG_DUMP ATH_DEBUG_MAKE_MODULE_MASK(3)
|
||||
#define ATH_DEBUG_IRQ ATH_DEBUG_MAKE_MODULE_MASK(4)
|
||||
|
||||
|
||||
#endif /*HTC_DEBUG_H_*/
|
|
@ -1,211 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="htc_internal.h" company="Atheros">
|
||||
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _HTC_INTERNAL_H_
|
||||
#define _HTC_INTERNAL_H_
|
||||
|
||||
/* for debugging, uncomment this to capture the last frame header, on frame header
|
||||
* processing errors, the last frame header is dump for comparison */
|
||||
//#define HTC_CAPTURE_LAST_FRAME
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Header files */
|
||||
|
||||
#include "a_config.h"
|
||||
#include "athdefs.h"
|
||||
#include "a_osapi.h"
|
||||
#include "htc_debug.h"
|
||||
#include "htc.h"
|
||||
#include "htc_api.h"
|
||||
#include "bmi_msg.h"
|
||||
#include "hif.h"
|
||||
#include "AR6000/ar6k.h"
|
||||
|
||||
/* HTC operational parameters */
|
||||
#define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */
|
||||
#define HTC_TARGET_DEBUG_INTR_MASK 0x01
|
||||
#define HTC_TARGET_CREDIT_INTR_MASK 0xF0
|
||||
|
||||
#define HTC_HOST_MAX_MSG_PER_BUNDLE 8
|
||||
#define HTC_MIN_HTC_MSGS_TO_BUNDLE 2
|
||||
|
||||
/* packet flags */
|
||||
|
||||
#define HTC_RX_PKT_IGNORE_LOOKAHEAD (1 << 0)
|
||||
#define HTC_RX_PKT_REFRESH_HDR (1 << 1)
|
||||
#define HTC_RX_PKT_PART_OF_BUNDLE (1 << 2)
|
||||
#define HTC_RX_PKT_NO_RECYCLE (1 << 3)
|
||||
|
||||
/* scatter request flags */
|
||||
|
||||
#define HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE (1 << 0)
|
||||
|
||||
struct htc_endpoint {
|
||||
HTC_ENDPOINT_ID Id;
|
||||
HTC_SERVICE_ID ServiceID; /* service ID this endpoint is bound to
|
||||
non-zero value means this endpoint is in use */
|
||||
struct htc_packet_queue TxQueue; /* HTC frame buffer TX queue */
|
||||
struct htc_packet_queue RxBuffers; /* HTC frame buffer RX list */
|
||||
struct htc_endpoint_credit_dist CreditDist; /* credit distribution structure (exposed to driver layer) */
|
||||
struct htc_ep_callbacks EpCallBacks; /* callbacks associated with this endpoint */
|
||||
int MaxTxQueueDepth; /* max depth of the TX queue before we need to
|
||||
call driver's full handler */
|
||||
int MaxMsgLength; /* max length of endpoint message */
|
||||
int TxProcessCount; /* reference count to continue tx processing */
|
||||
struct htc_packet_queue RecvIndicationQueue; /* recv packets ready to be indicated */
|
||||
int RxProcessCount; /* reference count to allow single processing context */
|
||||
struct htc_target *target; /* back pointer to target */
|
||||
u8 SeqNo; /* TX seq no (helpful) for debugging */
|
||||
u32 LocalConnectionFlags; /* local connection flags */
|
||||
struct htc_endpoint_stats EndPointStats; /* endpoint statistics */
|
||||
};
|
||||
|
||||
#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count);
|
||||
#define HTC_SERVICE_TX_PACKET_TAG HTC_TX_PACKET_TAG_INTERNAL
|
||||
|
||||
#define NUM_CONTROL_BUFFERS 8
|
||||
#define NUM_CONTROL_TX_BUFFERS 2
|
||||
#define NUM_CONTROL_RX_BUFFERS (NUM_CONTROL_BUFFERS - NUM_CONTROL_TX_BUFFERS)
|
||||
|
||||
struct htc_control_buffer {
|
||||
struct htc_packet HtcPacket;
|
||||
u8 *Buffer;
|
||||
};
|
||||
|
||||
#define HTC_RECV_WAIT_BUFFERS (1 << 0)
|
||||
#define HTC_OP_STATE_STOPPING (1 << 0)
|
||||
|
||||
/* our HTC target state */
|
||||
struct htc_target {
|
||||
struct htc_endpoint EndPoint[ENDPOINT_MAX];
|
||||
struct htc_control_buffer HTCControlBuffers[NUM_CONTROL_BUFFERS];
|
||||
struct htc_endpoint_credit_dist *EpCreditDistributionListHead;
|
||||
struct htc_packet_queue ControlBufferTXFreeList;
|
||||
struct htc_packet_queue ControlBufferRXFreeList;
|
||||
HTC_CREDIT_DIST_CALLBACK DistributeCredits;
|
||||
HTC_CREDIT_INIT_CALLBACK InitCredits;
|
||||
void *pCredDistContext;
|
||||
int TargetCredits;
|
||||
unsigned int TargetCreditSize;
|
||||
A_MUTEX_T HTCLock;
|
||||
A_MUTEX_T HTCRxLock;
|
||||
A_MUTEX_T HTCTxLock;
|
||||
struct ar6k_device Device; /* AR6K - specific state */
|
||||
u32 OpStateFlags;
|
||||
u32 RecvStateFlags;
|
||||
HTC_ENDPOINT_ID EpWaitingForBuffers;
|
||||
bool TargetFailure;
|
||||
#ifdef HTC_CAPTURE_LAST_FRAME
|
||||
struct htc_frame_hdr LastFrameHdr; /* useful for debugging */
|
||||
u8 LastTrailer[256];
|
||||
u8 LastTrailerLength;
|
||||
#endif
|
||||
struct htc_init_info HTCInitInfo;
|
||||
u8 HTCTargetVersion;
|
||||
int MaxMsgPerBundle; /* max messages per bundle for HTC */
|
||||
bool SendBundlingEnabled; /* run time enable for send bundling (dynamic) */
|
||||
int RecvBundlingEnabled; /* run time enable for recv bundling (dynamic) */
|
||||
};
|
||||
|
||||
#define HTC_STOPPING(t) ((t)->OpStateFlags & HTC_OP_STATE_STOPPING)
|
||||
#define LOCK_HTC(t) A_MUTEX_LOCK(&(t)->HTCLock);
|
||||
#define UNLOCK_HTC(t) A_MUTEX_UNLOCK(&(t)->HTCLock);
|
||||
#define LOCK_HTC_RX(t) A_MUTEX_LOCK(&(t)->HTCRxLock);
|
||||
#define UNLOCK_HTC_RX(t) A_MUTEX_UNLOCK(&(t)->HTCRxLock);
|
||||
#define LOCK_HTC_TX(t) A_MUTEX_LOCK(&(t)->HTCTxLock);
|
||||
#define UNLOCK_HTC_TX(t) A_MUTEX_UNLOCK(&(t)->HTCTxLock);
|
||||
|
||||
#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((struct htc_target *)(hnd))
|
||||
#define HTC_RECYCLE_RX_PKT(target,p,e) \
|
||||
{ \
|
||||
if ((p)->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_NO_RECYCLE) { \
|
||||
HTC_PACKET_RESET_RX(pPacket); \
|
||||
pPacket->Status = A_ECANCELED; \
|
||||
(e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext, \
|
||||
(p)); \
|
||||
} else { \
|
||||
HTC_PACKET_RESET_RX(pPacket); \
|
||||
HTCAddReceivePkt((HTC_HANDLE)(target),(p)); \
|
||||
} \
|
||||
}
|
||||
|
||||
/* internal HTC functions */
|
||||
void HTCControlTxComplete(void *Context, struct htc_packet *pPacket);
|
||||
void HTCControlRecv(void *Context, struct htc_packet *pPacket);
|
||||
int HTCWaitforControlMessage(struct htc_target *target, struct htc_packet **ppControlPacket);
|
||||
struct htc_packet *HTCAllocControlBuffer(struct htc_target *target, struct htc_packet_queue *pList);
|
||||
void HTCFreeControlBuffer(struct htc_target *target, struct htc_packet *pPacket, struct htc_packet_queue *pList);
|
||||
int HTCIssueSend(struct htc_target *target, struct htc_packet *pPacket);
|
||||
void HTCRecvCompleteHandler(void *Context, struct htc_packet *pPacket);
|
||||
int HTCRecvMessagePendingHandler(void *Context, u32 MsgLookAheads[], int NumLookAheads, bool *pAsyncProc, int *pNumPktsFetched);
|
||||
void HTCProcessCreditRpt(struct htc_target *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint);
|
||||
int HTCSendSetupComplete(struct htc_target *target);
|
||||
void HTCFlushRecvBuffers(struct htc_target *target);
|
||||
void HTCFlushSendPkts(struct htc_target *target);
|
||||
|
||||
#ifdef ATH_DEBUG_MODULE
|
||||
void DumpCreditDist(struct htc_endpoint_credit_dist *pEPDist);
|
||||
void DumpCreditDistStates(struct htc_target *target);
|
||||
void DebugDumpBytes(u8 *buffer, u16 length, char *pDescription);
|
||||
#endif
|
||||
|
||||
static INLINE struct htc_packet *HTC_ALLOC_CONTROL_TX(struct htc_target *target) {
|
||||
struct htc_packet *pPacket = HTCAllocControlBuffer(target,&target->ControlBufferTXFreeList);
|
||||
if (pPacket != NULL) {
|
||||
/* set payload pointer area with some headroom */
|
||||
pPacket->pBuffer = pPacket->pBufferStart + HTC_HDR_LENGTH;
|
||||
}
|
||||
return pPacket;
|
||||
}
|
||||
|
||||
#define HTC_FREE_CONTROL_TX(t,p) HTCFreeControlBuffer((t),(p),&(t)->ControlBufferTXFreeList)
|
||||
#define HTC_ALLOC_CONTROL_RX(t) HTCAllocControlBuffer((t),&(t)->ControlBufferRXFreeList)
|
||||
#define HTC_FREE_CONTROL_RX(t,p) \
|
||||
{ \
|
||||
HTC_PACKET_RESET_RX(p); \
|
||||
HTCFreeControlBuffer((t),(p),&(t)->ControlBufferRXFreeList); \
|
||||
}
|
||||
|
||||
#define HTC_PREPARE_SEND_PKT(pP,sendflags,ctrl0,ctrl1) \
|
||||
{ \
|
||||
u8 *pHdrBuf; \
|
||||
(pP)->pBuffer -= HTC_HDR_LENGTH; \
|
||||
pHdrBuf = (pP)->pBuffer; \
|
||||
A_SET_UINT16_FIELD(pHdrBuf,struct htc_frame_hdr,PayloadLen,(u16)(pP)->ActualLength); \
|
||||
A_SET_UINT8_FIELD(pHdrBuf,struct htc_frame_hdr,Flags,(sendflags)); \
|
||||
A_SET_UINT8_FIELD(pHdrBuf,struct htc_frame_hdr,EndpointID, (u8)(pP)->Endpoint); \
|
||||
A_SET_UINT8_FIELD(pHdrBuf,struct htc_frame_hdr,ControlBytes[0], (u8)(ctrl0)); \
|
||||
A_SET_UINT8_FIELD(pHdrBuf,struct htc_frame_hdr,ControlBytes[1], (u8)(ctrl1)); \
|
||||
}
|
||||
|
||||
#define HTC_UNPREPARE_SEND_PKT(pP) \
|
||||
(pP)->pBuffer += HTC_HDR_LENGTH; \
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HTC_INTERNAL_H_ */
|
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
@ -1,450 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="htc_services.c" company="Atheros">
|
||||
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#include "htc_internal.h"
|
||||
|
||||
void HTCControlTxComplete(void *Context, struct htc_packet *pPacket)
|
||||
{
|
||||
/* not implemented
|
||||
* we do not send control TX frames during normal runtime, only during setup */
|
||||
AR_DEBUG_ASSERT(false);
|
||||
}
|
||||
|
||||
/* callback when a control message arrives on this endpoint */
|
||||
void HTCControlRecv(void *Context, struct htc_packet *pPacket)
|
||||
{
|
||||
AR_DEBUG_ASSERT(pPacket->Endpoint == ENDPOINT_0);
|
||||
|
||||
if (pPacket->Status == A_ECANCELED) {
|
||||
/* this is a flush operation, return the control packet back to the pool */
|
||||
HTC_FREE_CONTROL_RX((struct htc_target*)Context,pPacket);
|
||||
return;
|
||||
}
|
||||
|
||||
/* the only control messages we are expecting are NULL messages (credit resports) */
|
||||
if (pPacket->ActualLength > 0) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
("HTCControlRecv, got message with length:%d \n",
|
||||
pPacket->ActualLength + (u32)HTC_HDR_LENGTH));
|
||||
|
||||
#ifdef ATH_DEBUG_MODULE
|
||||
/* dump header and message */
|
||||
DebugDumpBytes(pPacket->pBuffer - HTC_HDR_LENGTH,
|
||||
pPacket->ActualLength + HTC_HDR_LENGTH,
|
||||
"Unexpected ENDPOINT 0 Message");
|
||||
#endif
|
||||
}
|
||||
|
||||
HTC_RECYCLE_RX_PKT((struct htc_target*)Context,pPacket,&((struct htc_target*)Context)->EndPoint[0]);
|
||||
}
|
||||
|
||||
int HTCSendSetupComplete(struct htc_target *target)
|
||||
{
|
||||
struct htc_packet *pSendPacket = NULL;
|
||||
int status;
|
||||
|
||||
do {
|
||||
/* allocate a packet to send to the target */
|
||||
pSendPacket = HTC_ALLOC_CONTROL_TX(target);
|
||||
|
||||
if (NULL == pSendPacket) {
|
||||
status = A_NO_MEMORY;
|
||||
break;
|
||||
}
|
||||
|
||||
if (target->HTCTargetVersion >= HTC_VERSION_2P1) {
|
||||
HTC_SETUP_COMPLETE_EX_MSG *pSetupCompleteEx;
|
||||
u32 setupFlags = 0;
|
||||
|
||||
pSetupCompleteEx = (HTC_SETUP_COMPLETE_EX_MSG *)pSendPacket->pBuffer;
|
||||
A_MEMZERO(pSetupCompleteEx, sizeof(HTC_SETUP_COMPLETE_EX_MSG));
|
||||
pSetupCompleteEx->MessageID = HTC_MSG_SETUP_COMPLETE_EX_ID;
|
||||
if (target->MaxMsgPerBundle > 0) {
|
||||
/* host can do HTC bundling, indicate this to the target */
|
||||
setupFlags |= HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV;
|
||||
pSetupCompleteEx->MaxMsgsPerBundledRecv = target->MaxMsgPerBundle;
|
||||
}
|
||||
memcpy(&pSetupCompleteEx->SetupFlags, &setupFlags, sizeof(pSetupCompleteEx->SetupFlags));
|
||||
SET_HTC_PACKET_INFO_TX(pSendPacket,
|
||||
NULL,
|
||||
(u8 *)pSetupCompleteEx,
|
||||
sizeof(HTC_SETUP_COMPLETE_EX_MSG),
|
||||
ENDPOINT_0,
|
||||
HTC_SERVICE_TX_PACKET_TAG);
|
||||
|
||||
} else {
|
||||
HTC_SETUP_COMPLETE_MSG *pSetupComplete;
|
||||
/* assemble setup complete message */
|
||||
pSetupComplete = (HTC_SETUP_COMPLETE_MSG *)pSendPacket->pBuffer;
|
||||
A_MEMZERO(pSetupComplete, sizeof(HTC_SETUP_COMPLETE_MSG));
|
||||
pSetupComplete->MessageID = HTC_MSG_SETUP_COMPLETE_ID;
|
||||
SET_HTC_PACKET_INFO_TX(pSendPacket,
|
||||
NULL,
|
||||
(u8 *)pSetupComplete,
|
||||
sizeof(HTC_SETUP_COMPLETE_MSG),
|
||||
ENDPOINT_0,
|
||||
HTC_SERVICE_TX_PACKET_TAG);
|
||||
}
|
||||
|
||||
/* we want synchronous operation */
|
||||
pSendPacket->Completion = NULL;
|
||||
HTC_PREPARE_SEND_PKT(pSendPacket,0,0,0);
|
||||
/* send the message */
|
||||
status = HTCIssueSend(target,pSendPacket);
|
||||
|
||||
} while (false);
|
||||
|
||||
if (pSendPacket != NULL) {
|
||||
HTC_FREE_CONTROL_TX(target,pSendPacket);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
int HTCConnectService(HTC_HANDLE HTCHandle,
|
||||
struct htc_service_connect_req *pConnectReq,
|
||||
struct htc_service_connect_resp *pConnectResp)
|
||||
{
|
||||
struct htc_target *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
|
||||
int status = 0;
|
||||
struct htc_packet *pRecvPacket = NULL;
|
||||
struct htc_packet *pSendPacket = NULL;
|
||||
HTC_CONNECT_SERVICE_RESPONSE_MSG *pResponseMsg;
|
||||
HTC_CONNECT_SERVICE_MSG *pConnectMsg;
|
||||
HTC_ENDPOINT_ID assignedEndpoint = ENDPOINT_MAX;
|
||||
struct htc_endpoint *pEndpoint;
|
||||
unsigned int maxMsgSize = 0;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCConnectService, target:0x%lX SvcID:0x%X \n",
|
||||
(unsigned long)target, pConnectReq->ServiceID));
|
||||
|
||||
do {
|
||||
|
||||
AR_DEBUG_ASSERT(pConnectReq->ServiceID != 0);
|
||||
|
||||
if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) {
|
||||
/* special case for pseudo control service */
|
||||
assignedEndpoint = ENDPOINT_0;
|
||||
maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH;
|
||||
} else {
|
||||
/* allocate a packet to send to the target */
|
||||
pSendPacket = HTC_ALLOC_CONTROL_TX(target);
|
||||
|
||||
if (NULL == pSendPacket) {
|
||||
AR_DEBUG_ASSERT(false);
|
||||
status = A_NO_MEMORY;
|
||||
break;
|
||||
}
|
||||
/* assemble connect service message */
|
||||
pConnectMsg = (HTC_CONNECT_SERVICE_MSG *)pSendPacket->pBuffer;
|
||||
AR_DEBUG_ASSERT(pConnectMsg != NULL);
|
||||
A_MEMZERO(pConnectMsg,sizeof(HTC_CONNECT_SERVICE_MSG));
|
||||
pConnectMsg->MessageID = HTC_MSG_CONNECT_SERVICE_ID;
|
||||
pConnectMsg->ServiceID = pConnectReq->ServiceID;
|
||||
pConnectMsg->ConnectionFlags = pConnectReq->ConnectionFlags;
|
||||
/* check caller if it wants to transfer meta data */
|
||||
if ((pConnectReq->pMetaData != NULL) &&
|
||||
(pConnectReq->MetaDataLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
|
||||
/* copy meta data into message buffer (after header ) */
|
||||
memcpy((u8 *)pConnectMsg + sizeof(HTC_CONNECT_SERVICE_MSG),
|
||||
pConnectReq->pMetaData,
|
||||
pConnectReq->MetaDataLength);
|
||||
pConnectMsg->ServiceMetaLength = pConnectReq->MetaDataLength;
|
||||
}
|
||||
|
||||
SET_HTC_PACKET_INFO_TX(pSendPacket,
|
||||
NULL,
|
||||
(u8 *)pConnectMsg,
|
||||
sizeof(HTC_CONNECT_SERVICE_MSG) + pConnectMsg->ServiceMetaLength,
|
||||
ENDPOINT_0,
|
||||
HTC_SERVICE_TX_PACKET_TAG);
|
||||
|
||||
/* we want synchronous operation */
|
||||
pSendPacket->Completion = NULL;
|
||||
HTC_PREPARE_SEND_PKT(pSendPacket,0,0,0);
|
||||
status = HTCIssueSend(target,pSendPacket);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
/* wait for response */
|
||||
status = HTCWaitforControlMessage(target, &pRecvPacket);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
/* we controlled the buffer creation so it has to be properly aligned */
|
||||
pResponseMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)pRecvPacket->pBuffer;
|
||||
|
||||
if ((pResponseMsg->MessageID != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID) ||
|
||||
(pRecvPacket->ActualLength < sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) {
|
||||
/* this message is not valid */
|
||||
AR_DEBUG_ASSERT(false);
|
||||
status = A_EPROTO;
|
||||
break;
|
||||
}
|
||||
|
||||
pConnectResp->ConnectRespCode = pResponseMsg->Status;
|
||||
/* check response status */
|
||||
if (pResponseMsg->Status != HTC_SERVICE_SUCCESS) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
(" Target failed service 0x%X connect request (status:%d)\n",
|
||||
pResponseMsg->ServiceID, pResponseMsg->Status));
|
||||
status = A_EPROTO;
|
||||
break;
|
||||
}
|
||||
|
||||
assignedEndpoint = (HTC_ENDPOINT_ID) pResponseMsg->EndpointID;
|
||||
maxMsgSize = pResponseMsg->MaxMsgSize;
|
||||
|
||||
if ((pConnectResp->pMetaData != NULL) &&
|
||||
(pResponseMsg->ServiceMetaLength > 0) &&
|
||||
(pResponseMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
|
||||
/* caller supplied a buffer and the target responded with data */
|
||||
int copyLength = min((int)pConnectResp->BufferLength, (int)pResponseMsg->ServiceMetaLength);
|
||||
/* copy the meta data */
|
||||
memcpy(pConnectResp->pMetaData,
|
||||
((u8 *)pResponseMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG),
|
||||
copyLength);
|
||||
pConnectResp->ActualLength = copyLength;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* the rest of these are parameter checks so set the error status */
|
||||
status = A_EPROTO;
|
||||
|
||||
if (assignedEndpoint >= ENDPOINT_MAX) {
|
||||
AR_DEBUG_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
|
||||
if (0 == maxMsgSize) {
|
||||
AR_DEBUG_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
|
||||
pEndpoint = &target->EndPoint[assignedEndpoint];
|
||||
pEndpoint->Id = assignedEndpoint;
|
||||
if (pEndpoint->ServiceID != 0) {
|
||||
/* endpoint already in use! */
|
||||
AR_DEBUG_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
|
||||
/* return assigned endpoint to caller */
|
||||
pConnectResp->Endpoint = assignedEndpoint;
|
||||
pConnectResp->MaxMsgLength = maxMsgSize;
|
||||
|
||||
/* setup the endpoint */
|
||||
pEndpoint->ServiceID = pConnectReq->ServiceID; /* this marks the endpoint in use */
|
||||
pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth;
|
||||
pEndpoint->MaxMsgLength = maxMsgSize;
|
||||
/* copy all the callbacks */
|
||||
pEndpoint->EpCallBacks = pConnectReq->EpCallbacks;
|
||||
/* set the credit distribution info for this endpoint, this information is
|
||||
* passed back to the credit distribution callback function */
|
||||
pEndpoint->CreditDist.ServiceID = pConnectReq->ServiceID;
|
||||
pEndpoint->CreditDist.pHTCReserved = pEndpoint;
|
||||
pEndpoint->CreditDist.Endpoint = assignedEndpoint;
|
||||
pEndpoint->CreditDist.TxCreditSize = target->TargetCreditSize;
|
||||
|
||||
if (pConnectReq->MaxSendMsgSize != 0) {
|
||||
/* override TxCreditsPerMaxMsg calculation, this optimizes the credit-low indications
|
||||
* since the host will actually issue smaller messages in the Send path */
|
||||
if (pConnectReq->MaxSendMsgSize > maxMsgSize) {
|
||||
/* can't be larger than the maximum the target can support */
|
||||
AR_DEBUG_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
pEndpoint->CreditDist.TxCreditsPerMaxMsg = pConnectReq->MaxSendMsgSize / target->TargetCreditSize;
|
||||
} else {
|
||||
pEndpoint->CreditDist.TxCreditsPerMaxMsg = maxMsgSize / target->TargetCreditSize;
|
||||
}
|
||||
|
||||
if (0 == pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
|
||||
pEndpoint->CreditDist.TxCreditsPerMaxMsg = 1;
|
||||
}
|
||||
|
||||
/* save local connection flags */
|
||||
pEndpoint->LocalConnectionFlags = pConnectReq->LocalConnectionFlags;
|
||||
|
||||
status = 0;
|
||||
|
||||
} while (false);
|
||||
|
||||
if (pSendPacket != NULL) {
|
||||
HTC_FREE_CONTROL_TX(target,pSendPacket);
|
||||
}
|
||||
|
||||
if (pRecvPacket != NULL) {
|
||||
HTC_FREE_CONTROL_RX(target,pRecvPacket);
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCConnectService \n"));
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static void AddToEndpointDistList(struct htc_target *target, struct htc_endpoint_credit_dist *pEpDist)
|
||||
{
|
||||
struct htc_endpoint_credit_dist *pCurEntry,*pLastEntry;
|
||||
|
||||
if (NULL == target->EpCreditDistributionListHead) {
|
||||
target->EpCreditDistributionListHead = pEpDist;
|
||||
pEpDist->pNext = NULL;
|
||||
pEpDist->pPrev = NULL;
|
||||
return;
|
||||
}
|
||||
|
||||
/* queue to the end of the list, this does not have to be very
|
||||
* fast since this list is built at startup time */
|
||||
pCurEntry = target->EpCreditDistributionListHead;
|
||||
|
||||
while (pCurEntry) {
|
||||
pLastEntry = pCurEntry;
|
||||
pCurEntry = pCurEntry->pNext;
|
||||
}
|
||||
|
||||
pLastEntry->pNext = pEpDist;
|
||||
pEpDist->pPrev = pLastEntry;
|
||||
pEpDist->pNext = NULL;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* default credit init callback */
|
||||
static void HTCDefaultCreditInit(void *Context,
|
||||
struct htc_endpoint_credit_dist *pEPList,
|
||||
int TotalCredits)
|
||||
{
|
||||
struct htc_endpoint_credit_dist *pCurEpDist;
|
||||
int totalEps = 0;
|
||||
int creditsPerEndpoint;
|
||||
|
||||
pCurEpDist = pEPList;
|
||||
/* first run through the list and figure out how many endpoints we are dealing with */
|
||||
while (pCurEpDist != NULL) {
|
||||
pCurEpDist = pCurEpDist->pNext;
|
||||
totalEps++;
|
||||
}
|
||||
|
||||
/* even distribution */
|
||||
creditsPerEndpoint = TotalCredits/totalEps;
|
||||
|
||||
pCurEpDist = pEPList;
|
||||
/* run through the list and set minimum and normal credits and
|
||||
* provide the endpoint with some credits to start */
|
||||
while (pCurEpDist != NULL) {
|
||||
|
||||
if (creditsPerEndpoint < pCurEpDist->TxCreditsPerMaxMsg) {
|
||||
/* too many endpoints and not enough credits */
|
||||
AR_DEBUG_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
/* our minimum is set for at least 1 max message */
|
||||
pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
|
||||
/* this value is ignored by our credit alg, since we do
|
||||
* not dynamically adjust credits, this is the policy of
|
||||
* the "default" credit distribution, something simple and easy */
|
||||
pCurEpDist->TxCreditsNorm = 0xFFFF;
|
||||
/* give the endpoint minimum credits */
|
||||
pCurEpDist->TxCredits = creditsPerEndpoint;
|
||||
pCurEpDist->TxCreditsAssigned = creditsPerEndpoint;
|
||||
pCurEpDist = pCurEpDist->pNext;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* default credit distribution callback, NOTE, this callback holds the TX lock */
|
||||
void HTCDefaultCreditDist(void *Context,
|
||||
struct htc_endpoint_credit_dist *pEPDistList,
|
||||
HTC_CREDIT_DIST_REASON Reason)
|
||||
{
|
||||
struct htc_endpoint_credit_dist *pCurEpDist;
|
||||
|
||||
if (Reason == HTC_CREDIT_DIST_SEND_COMPLETE) {
|
||||
pCurEpDist = pEPDistList;
|
||||
/* simple distribution */
|
||||
while (pCurEpDist != NULL) {
|
||||
if (pCurEpDist->TxCreditsToDist > 0) {
|
||||
/* just give the endpoint back the credits */
|
||||
pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
|
||||
pCurEpDist->TxCreditsToDist = 0;
|
||||
}
|
||||
pCurEpDist = pCurEpDist->pNext;
|
||||
}
|
||||
}
|
||||
|
||||
/* note we do not need to handle the other reason codes as this is a very
|
||||
* simple distribution scheme, no need to seek for more credits or handle inactivity */
|
||||
}
|
||||
|
||||
void HTCSetCreditDistribution(HTC_HANDLE HTCHandle,
|
||||
void *pCreditDistContext,
|
||||
HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
|
||||
HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
|
||||
HTC_SERVICE_ID ServicePriorityOrder[],
|
||||
int ListLength)
|
||||
{
|
||||
struct htc_target *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
|
||||
int i;
|
||||
int ep;
|
||||
|
||||
if (CreditInitFunc != NULL) {
|
||||
/* caller has supplied their own distribution functions */
|
||||
target->InitCredits = CreditInitFunc;
|
||||
AR_DEBUG_ASSERT(CreditDistFunc != NULL);
|
||||
target->DistributeCredits = CreditDistFunc;
|
||||
target->pCredDistContext = pCreditDistContext;
|
||||
} else {
|
||||
/* caller wants HTC to do distribution */
|
||||
/* if caller wants service to handle distributions then
|
||||
* it must set both of these to NULL! */
|
||||
AR_DEBUG_ASSERT(CreditDistFunc == NULL);
|
||||
target->InitCredits = HTCDefaultCreditInit;
|
||||
target->DistributeCredits = HTCDefaultCreditDist;
|
||||
target->pCredDistContext = target;
|
||||
}
|
||||
|
||||
/* always add HTC control endpoint first, we only expose the list after the
|
||||
* first one, this is added for TX queue checking */
|
||||
AddToEndpointDistList(target, &target->EndPoint[ENDPOINT_0].CreditDist);
|
||||
|
||||
/* build the list of credit distribution structures in priority order
|
||||
* supplied by the caller, these will follow endpoint 0 */
|
||||
for (i = 0; i < ListLength; i++) {
|
||||
/* match services with endpoints and add the endpoints to the distribution list
|
||||
* in FIFO order */
|
||||
for (ep = ENDPOINT_1; ep < ENDPOINT_MAX; ep++) {
|
||||
if (target->EndPoint[ep].ServiceID == ServicePriorityOrder[i]) {
|
||||
/* queue this one to the list */
|
||||
AddToEndpointDistList(target, &target->EndPoint[ep].CreditDist);
|
||||
break;
|
||||
}
|
||||
}
|
||||
AR_DEBUG_ASSERT(ep < ENDPOINT_MAX);
|
||||
}
|
||||
|
||||
}
|
|
@ -1,31 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="a_config.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// This file contains software configuration options that enables
|
||||
// specific software "features"
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _A_CONFIG_H_
|
||||
#define _A_CONFIG_H_
|
||||
|
||||
#include "../os/linux/include/config_linux.h"
|
||||
|
||||
#endif
|
|
@ -1,195 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="a_debug.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _A_DEBUG_H_
|
||||
#define _A_DEBUG_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#include <a_osapi.h>
|
||||
|
||||
/* standard debug print masks bits 0..7 */
|
||||
#define ATH_DEBUG_ERR (1 << 0) /* errors */
|
||||
#define ATH_DEBUG_WARN (1 << 1) /* warnings */
|
||||
#define ATH_DEBUG_INFO (1 << 2) /* informational (module startup info) */
|
||||
#define ATH_DEBUG_TRC (1 << 3) /* generic function call tracing */
|
||||
#define ATH_DEBUG_RSVD1 (1 << 4)
|
||||
#define ATH_DEBUG_RSVD2 (1 << 5)
|
||||
#define ATH_DEBUG_RSVD3 (1 << 6)
|
||||
#define ATH_DEBUG_RSVD4 (1 << 7)
|
||||
|
||||
#define ATH_DEBUG_MASK_DEFAULTS (ATH_DEBUG_ERR | ATH_DEBUG_WARN)
|
||||
#define ATH_DEBUG_ANY 0xFFFF
|
||||
|
||||
/* other aliases used throughout */
|
||||
#define ATH_DEBUG_ERROR ATH_DEBUG_ERR
|
||||
#define ATH_LOG_ERR ATH_DEBUG_ERR
|
||||
#define ATH_LOG_INF ATH_DEBUG_INFO
|
||||
#define ATH_LOG_TRC ATH_DEBUG_TRC
|
||||
#define ATH_DEBUG_TRACE ATH_DEBUG_TRC
|
||||
#define ATH_DEBUG_INIT ATH_DEBUG_INFO
|
||||
|
||||
/* bits 8..31 are module-specific masks */
|
||||
#define ATH_DEBUG_MODULE_MASK_SHIFT 8
|
||||
|
||||
/* macro to make a module-specific masks */
|
||||
#define ATH_DEBUG_MAKE_MODULE_MASK(index) (1 << (ATH_DEBUG_MODULE_MASK_SHIFT + (index)))
|
||||
|
||||
void DebugDumpBytes(u8 *buffer, u16 length, char *pDescription);
|
||||
|
||||
/* Debug support on a per-module basis
|
||||
*
|
||||
* Usage:
|
||||
*
|
||||
* Each module can utilize it's own debug mask variable. A set of commonly used
|
||||
* masks are provided (ERRORS, WARNINGS, TRACE etc..). It is up to each module
|
||||
* to define module-specific masks using the macros above.
|
||||
*
|
||||
* Each module defines a single debug mask variable debug_XXX where the "name" of the module is
|
||||
* common to all C-files within that module. This requires every C-file that includes a_debug.h
|
||||
* to define the module name in that file.
|
||||
*
|
||||
* Example:
|
||||
*
|
||||
* #define ATH_MODULE_NAME htc
|
||||
* #include "a_debug.h"
|
||||
*
|
||||
* This will define a debug mask structure called debug_htc and all debug macros will reference this
|
||||
* variable.
|
||||
*
|
||||
* A module can define module-specific bit masks using the ATH_DEBUG_MAKE_MODULE_MASK() macro:
|
||||
*
|
||||
* #define ATH_DEBUG_MY_MASK1 ATH_DEBUG_MAKE_MODULE_MASK(0)
|
||||
* #define ATH_DEBUG_MY_MASK2 ATH_DEBUG_MAKE_MODULE_MASK(1)
|
||||
*
|
||||
* The instantiation of the debug structure should be made by the module. When a module is
|
||||
* instantiated, the module can set a description string, a default mask and an array of description
|
||||
* entries containing information on each module-defined debug mask.
|
||||
* NOTE: The instantiation is statically allocated, only one instance can exist per module.
|
||||
*
|
||||
* Example:
|
||||
*
|
||||
*
|
||||
* #define ATH_DEBUG_BMI ATH_DEBUG_MAKE_MODULE_MASK(0)
|
||||
*
|
||||
* #ifdef DEBUG
|
||||
* static struct ath_debug_mask_description bmi_debug_desc[] = {
|
||||
* { ATH_DEBUG_BMI , "BMI Tracing"}, <== description of the module specific mask
|
||||
* };
|
||||
*
|
||||
* ATH_DEBUG_INSTANTIATE_MODULE_VAR(bmi,
|
||||
* "bmi" <== module name
|
||||
* "Boot Manager Interface", <== description of module
|
||||
* ATH_DEBUG_MASK_DEFAULTS, <== defaults
|
||||
* ATH_DEBUG_DESCRIPTION_COUNT(bmi_debug_desc),
|
||||
* bmi_debug_desc);
|
||||
*
|
||||
* #endif
|
||||
*
|
||||
* A module can optionally register it's debug module information in order for other tools to change the
|
||||
* bit mask at runtime. A module can call A_REGISTER_MODULE_DEBUG_INFO() in it's module
|
||||
* init code. This macro can be called multiple times without consequence. The debug info maintains
|
||||
* state to indicate whether the information was previously registered.
|
||||
*
|
||||
* */
|
||||
|
||||
#define ATH_DEBUG_MAX_MASK_DESC_LENGTH 32
|
||||
#define ATH_DEBUG_MAX_MOD_DESC_LENGTH 64
|
||||
|
||||
struct ath_debug_mask_description {
|
||||
u32 Mask;
|
||||
char Description[ATH_DEBUG_MAX_MASK_DESC_LENGTH];
|
||||
};
|
||||
|
||||
#define ATH_DEBUG_INFO_FLAGS_REGISTERED (1 << 0)
|
||||
|
||||
typedef struct _ATH_DEBUG_MODULE_DBG_INFO{
|
||||
struct _ATH_DEBUG_MODULE_DBG_INFO *pNext;
|
||||
char ModuleName[16];
|
||||
char ModuleDescription[ATH_DEBUG_MAX_MOD_DESC_LENGTH];
|
||||
u32 Flags;
|
||||
u32 CurrentMask;
|
||||
int MaxDescriptions;
|
||||
struct ath_debug_mask_description *pMaskDescriptions; /* pointer to array of descriptions */
|
||||
} ATH_DEBUG_MODULE_DBG_INFO;
|
||||
|
||||
#define ATH_DEBUG_DESCRIPTION_COUNT(d) (int)((sizeof((d))) / (sizeof(struct ath_debug_mask_description)))
|
||||
|
||||
#define GET_ATH_MODULE_DEBUG_VAR_NAME(s) _XGET_ATH_MODULE_NAME_DEBUG_(s)
|
||||
#define GET_ATH_MODULE_DEBUG_VAR_MASK(s) _XGET_ATH_MODULE_NAME_DEBUG_(s).CurrentMask
|
||||
#define _XGET_ATH_MODULE_NAME_DEBUG_(s) debug_ ## s
|
||||
|
||||
#ifdef ATH_DEBUG_MODULE
|
||||
|
||||
/* for source files that will instantiate the debug variables */
|
||||
#define ATH_DEBUG_INSTANTIATE_MODULE_VAR(s,name,moddesc,initmask,count,descriptions) \
|
||||
ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(s) = \
|
||||
{NULL,(name),(moddesc),0,(initmask),count,(descriptions)}
|
||||
|
||||
#ifdef ATH_MODULE_NAME
|
||||
extern ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(ATH_MODULE_NAME);
|
||||
#define AR_DEBUG_LVL_CHECK(lvl) (GET_ATH_MODULE_DEBUG_VAR_MASK(ATH_MODULE_NAME) & (lvl))
|
||||
#endif /* ATH_MODULE_NAME */
|
||||
|
||||
#define ATH_DEBUG_SET_DEBUG_MASK(s,lvl) GET_ATH_MODULE_DEBUG_VAR_MASK(s) = (lvl)
|
||||
|
||||
#define ATH_DEBUG_DECLARE_EXTERN(s) \
|
||||
extern ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(s)
|
||||
|
||||
#define AR_DEBUG_PRINTBUF(buffer, length, desc) DebugDumpBytes(buffer,length,desc)
|
||||
|
||||
|
||||
#define AR_DEBUG_ASSERT A_ASSERT
|
||||
|
||||
void a_dump_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo);
|
||||
void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo);
|
||||
#define A_DUMP_MODULE_DEBUG_INFO(s) a_dump_module_debug_info(&(GET_ATH_MODULE_DEBUG_VAR_NAME(s)))
|
||||
#define A_REGISTER_MODULE_DEBUG_INFO(s) a_register_module_debug_info(&(GET_ATH_MODULE_DEBUG_VAR_NAME(s)))
|
||||
|
||||
#else /* !ATH_DEBUG_MODULE */
|
||||
/* NON ATH_DEBUG_MODULE */
|
||||
#define ATH_DEBUG_INSTANTIATE_MODULE_VAR(s,name,moddesc,initmask,count,descriptions)
|
||||
#define AR_DEBUG_LVL_CHECK(lvl) 0
|
||||
#define AR_DEBUG_PRINTBUF(buffer, length, desc)
|
||||
#define AR_DEBUG_ASSERT(test)
|
||||
#define ATH_DEBUG_DECLARE_EXTERN(s)
|
||||
#define ATH_DEBUG_SET_DEBUG_MASK(s,lvl)
|
||||
#define A_DUMP_MODULE_DEBUG_INFO(s)
|
||||
#define A_REGISTER_MODULE_DEBUG_INFO(s)
|
||||
|
||||
#endif
|
||||
|
||||
int a_get_module_mask(char *module_name, u32 *pMask);
|
||||
int a_set_module_mask(char *module_name, u32 Mask);
|
||||
void a_dump_module_debug_info_by_name(char *module_name);
|
||||
void a_module_debug_support_init(void);
|
||||
void a_module_debug_support_cleanup(void);
|
||||
|
||||
#include "../os/linux/include/debug_linux.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
|
@ -1,32 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="a_drv.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// This file contains the definitions of the basic atheros data types.
|
||||
// It is used to map the data types in atheros files to a platform specific
|
||||
// type.
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _A_DRV_H_
|
||||
#define _A_DRV_H_
|
||||
|
||||
#include "../os/linux/include/athdrv_linux.h"
|
||||
|
||||
#endif /* _ADRV_H_ */
|
|
@ -1,204 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="a_drv_api.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _A_DRV_API_H_
|
||||
#define _A_DRV_API_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/****************************************************************************/
|
||||
/****************************************************************************/
|
||||
/** **/
|
||||
/** WMI related hooks **/
|
||||
/** **/
|
||||
/****************************************************************************/
|
||||
/****************************************************************************/
|
||||
|
||||
#include <ar6000_api.h>
|
||||
|
||||
#define A_WMI_CHANNELLIST_RX(devt, numChan, chanList) \
|
||||
ar6000_channelList_rx((devt), (numChan), (chanList))
|
||||
|
||||
#define A_WMI_SET_NUMDATAENDPTS(devt, num) \
|
||||
ar6000_set_numdataendpts((devt), (num))
|
||||
|
||||
#define A_WMI_CONTROL_TX(devt, osbuf, streamID) \
|
||||
ar6000_control_tx((devt), (osbuf), (streamID))
|
||||
|
||||
#define A_WMI_TARGETSTATS_EVENT(devt, pStats, len) \
|
||||
ar6000_targetStats_event((devt), (pStats), (len))
|
||||
|
||||
#define A_WMI_SCANCOMPLETE_EVENT(devt, status) \
|
||||
ar6000_scanComplete_event((devt), (status))
|
||||
|
||||
#ifdef CONFIG_HOST_DSET_SUPPORT
|
||||
|
||||
#define A_WMI_DSET_DATA_REQ(devt, access_cookie, offset, length, targ_buf, targ_reply_fn, targ_reply_arg) \
|
||||
ar6000_dset_data_req((devt), (access_cookie), (offset), (length), (targ_buf), (targ_reply_fn), (targ_reply_arg))
|
||||
|
||||
#define A_WMI_DSET_CLOSE(devt, access_cookie) \
|
||||
ar6000_dset_close((devt), (access_cookie))
|
||||
|
||||
#endif
|
||||
|
||||
#define A_WMI_DSET_OPEN_REQ(devt, id, targ_handle, targ_reply_fn, targ_reply_arg) \
|
||||
ar6000_dset_open_req((devt), (id), (targ_handle), (targ_reply_fn), (targ_reply_arg))
|
||||
|
||||
#define A_WMI_CONNECT_EVENT(devt, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, assocReqLen, assocRespLen, assocInfo) \
|
||||
ar6000_connect_event((devt), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo))
|
||||
|
||||
#define A_WMI_PSPOLL_EVENT(devt, aid)\
|
||||
ar6000_pspoll_event((devt),(aid))
|
||||
|
||||
#define A_WMI_DTIMEXPIRY_EVENT(devt)\
|
||||
ar6000_dtimexpiry_event((devt))
|
||||
|
||||
#ifdef WAPI_ENABLE
|
||||
#define A_WMI_WAPI_REKEY_EVENT(devt, type, mac)\
|
||||
ap_wapi_rekey_event((devt),(type),(mac))
|
||||
#endif
|
||||
|
||||
#define A_WMI_REGDOMAIN_EVENT(devt, regCode) \
|
||||
ar6000_regDomain_event((devt), (regCode))
|
||||
|
||||
#define A_WMI_NEIGHBORREPORT_EVENT(devt, numAps, info) \
|
||||
ar6000_neighborReport_event((devt), (numAps), (info))
|
||||
|
||||
#define A_WMI_DISCONNECT_EVENT(devt, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus) \
|
||||
ar6000_disconnect_event((devt), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus))
|
||||
|
||||
#define A_WMI_TKIP_MICERR_EVENT(devt, keyid, ismcast) \
|
||||
ar6000_tkip_micerr_event((devt), (keyid), (ismcast))
|
||||
|
||||
#define A_WMI_BITRATE_RX(devt, rateKbps) \
|
||||
ar6000_bitrate_rx((devt), (rateKbps))
|
||||
|
||||
#define A_WMI_TXPWR_RX(devt, txPwr) \
|
||||
ar6000_txPwr_rx((devt), (txPwr))
|
||||
|
||||
#define A_WMI_READY_EVENT(devt, datap, phyCap, sw_ver, abi_ver) \
|
||||
ar6000_ready_event((devt), (datap), (phyCap), (sw_ver), (abi_ver))
|
||||
|
||||
#define A_WMI_DBGLOG_INIT_DONE(ar) \
|
||||
ar6000_dbglog_init_done(ar);
|
||||
|
||||
#define A_WMI_RSSI_THRESHOLD_EVENT(devt, newThreshold, rssi) \
|
||||
ar6000_rssiThreshold_event((devt), (newThreshold), (rssi))
|
||||
|
||||
#define A_WMI_REPORT_ERROR_EVENT(devt, errorVal) \
|
||||
ar6000_reportError_event((devt), (errorVal))
|
||||
|
||||
#define A_WMI_ROAM_TABLE_EVENT(devt, pTbl) \
|
||||
ar6000_roam_tbl_event((devt), (pTbl))
|
||||
|
||||
#define A_WMI_ROAM_DATA_EVENT(devt, p) \
|
||||
ar6000_roam_data_event((devt), (p))
|
||||
|
||||
#define A_WMI_WOW_LIST_EVENT(devt, num_filters, wow_filters) \
|
||||
ar6000_wow_list_event((devt), (num_filters), (wow_filters))
|
||||
|
||||
#define A_WMI_CAC_EVENT(devt, ac, cac_indication, statusCode, tspecSuggestion) \
|
||||
ar6000_cac_event((devt), (ac), (cac_indication), (statusCode), (tspecSuggestion))
|
||||
|
||||
#define A_WMI_CHANNEL_CHANGE_EVENT(devt, oldChannel, newChannel) \
|
||||
ar6000_channel_change_event((devt), (oldChannel), (newChannel))
|
||||
|
||||
#define A_WMI_PMKID_LIST_EVENT(devt, num_pmkid, pmkid_list, bssid_list) \
|
||||
ar6000_pmkid_list_event((devt), (num_pmkid), (pmkid_list), (bssid_list))
|
||||
|
||||
#define A_WMI_PEER_EVENT(devt, eventCode, bssid) \
|
||||
ar6000_peer_event ((devt), (eventCode), (bssid))
|
||||
|
||||
#ifdef CONFIG_HOST_TCMD_SUPPORT
|
||||
#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \
|
||||
ar6000_tcmd_rx_report_event((devt), (results), (len))
|
||||
#endif
|
||||
|
||||
#define A_WMI_HBCHALLENGERESP_EVENT(devt, cookie, source) \
|
||||
ar6000_hbChallengeResp_event((devt), (cookie), (source))
|
||||
|
||||
#define A_WMI_TX_RETRY_ERR_EVENT(devt) \
|
||||
ar6000_tx_retry_err_event((devt))
|
||||
|
||||
#define A_WMI_SNR_THRESHOLD_EVENT_RX(devt, newThreshold, snr) \
|
||||
ar6000_snrThresholdEvent_rx((devt), (newThreshold), (snr))
|
||||
|
||||
#define A_WMI_LQ_THRESHOLD_EVENT_RX(devt, range, lqVal) \
|
||||
ar6000_lqThresholdEvent_rx((devt), (range), (lqVal))
|
||||
|
||||
#define A_WMI_RATEMASK_RX(devt, ratemask) \
|
||||
ar6000_ratemask_rx((devt), (ratemask))
|
||||
|
||||
#define A_WMI_KEEPALIVE_RX(devt, configured) \
|
||||
ar6000_keepalive_rx((devt), (configured))
|
||||
|
||||
#define A_WMI_BSSINFO_EVENT_RX(ar, datp, len) \
|
||||
ar6000_bssInfo_event_rx((ar), (datap), (len))
|
||||
|
||||
#define A_WMI_DBGLOG_EVENT(ar, dropped, buffer, length) \
|
||||
ar6000_dbglog_event((ar), (dropped), (buffer), (length));
|
||||
|
||||
#define A_WMI_STREAM_TX_ACTIVE(devt,trafficClass) \
|
||||
ar6000_indicate_tx_activity((devt),(trafficClass), true)
|
||||
|
||||
#define A_WMI_STREAM_TX_INACTIVE(devt,trafficClass) \
|
||||
ar6000_indicate_tx_activity((devt),(trafficClass), false)
|
||||
#define A_WMI_Ac2EndpointID(devht, ac)\
|
||||
ar6000_ac2_endpoint_id((devht), (ac))
|
||||
|
||||
#define A_WMI_AGGR_RECV_ADDBA_REQ_EVT(devt, cmd)\
|
||||
ar6000_aggr_rcv_addba_req_evt((devt), (cmd))
|
||||
#define A_WMI_AGGR_RECV_ADDBA_RESP_EVT(devt, cmd)\
|
||||
ar6000_aggr_rcv_addba_resp_evt((devt), (cmd))
|
||||
#define A_WMI_AGGR_RECV_DELBA_REQ_EVT(devt, cmd)\
|
||||
ar6000_aggr_rcv_delba_req_evt((devt), (cmd))
|
||||
#define A_WMI_HCI_EVENT_EVT(devt, cmd)\
|
||||
ar6000_hci_event_rcv_evt((devt), (cmd))
|
||||
|
||||
#define A_WMI_Endpoint2Ac(devt, ep) \
|
||||
ar6000_endpoint_id2_ac((devt), (ep))
|
||||
|
||||
#define A_WMI_BTCOEX_CONFIG_EVENT(devt, evt, len)\
|
||||
ar6000_btcoex_config_event((devt), (evt), (len))
|
||||
|
||||
#define A_WMI_BTCOEX_STATS_EVENT(devt, datap, len)\
|
||||
ar6000_btcoex_stats_event((devt), (datap), (len))
|
||||
|
||||
/****************************************************************************/
|
||||
/****************************************************************************/
|
||||
/** **/
|
||||
/** HTC related hooks **/
|
||||
/** **/
|
||||
/****************************************************************************/
|
||||
/****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
|
||||
#define A_WMI_PROF_COUNT_RX(addr, count) prof_count_rx((addr), (count))
|
||||
#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
|
@ -1,32 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="a_osapi.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// This file contains the definitions of the basic atheros data types.
|
||||
// It is used to map the data types in atheros files to a platform specific
|
||||
// type.
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _A_OSAPI_H_
|
||||
#define _A_OSAPI_H_
|
||||
|
||||
#include "../os/linux/include/osapi_linux.h"
|
||||
|
||||
#endif /* _OSAPI_H_ */
|
|
@ -1,140 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (c) 2004-2010 Atheros Communications Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __AGGR_RECV_API_H__
|
||||
#define __AGGR_RECV_API_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef void (* RX_CALLBACK)(void * dev, void *osbuf);
|
||||
|
||||
typedef void (* ALLOC_NETBUFS)(A_NETBUF_QUEUE_T *q, u16 num);
|
||||
|
||||
/*
|
||||
* aggr_init:
|
||||
* Initialises the data structures, allocates data queues and
|
||||
* os buffers. Netbuf allocator is the input param, used by the
|
||||
* aggr module for allocation of NETBUFs from driver context.
|
||||
* These NETBUFs are used for AMSDU processing.
|
||||
* Returns the context for the aggr module.
|
||||
*/
|
||||
void *
|
||||
aggr_init(ALLOC_NETBUFS netbuf_allocator);
|
||||
|
||||
|
||||
/*
|
||||
* aggr_register_rx_dispatcher:
|
||||
* Registers OS call back function to deliver the
|
||||
* frames to OS. This is generally the topmost layer of
|
||||
* the driver context, after which the frames go to
|
||||
* IP stack via the call back function.
|
||||
* This dispatcher is active only when aggregation is ON.
|
||||
*/
|
||||
void
|
||||
aggr_register_rx_dispatcher(void *cntxt, void * dev, RX_CALLBACK fn);
|
||||
|
||||
|
||||
/*
|
||||
* aggr_process_bar:
|
||||
* When target receives BAR, it communicates to host driver
|
||||
* for modifying window parameters. Target indicates this via the
|
||||
* event: WMI_ADDBA_REQ_EVENTID. Host will dequeue all frames
|
||||
* up to the indicated sequence number.
|
||||
*/
|
||||
void
|
||||
aggr_process_bar(void *cntxt, u8 tid, u16 seq_no);
|
||||
|
||||
|
||||
/*
|
||||
* aggr_recv_addba_req_evt:
|
||||
* This event is to initiate/modify the receive side window.
|
||||
* Target will send WMI_ADDBA_REQ_EVENTID event to host - to setup
|
||||
* recv re-ordering queues. Target will negotiate ADDBA with peer,
|
||||
* and indicate via this event after successfully completing the
|
||||
* negotiation. This happens in two situations:
|
||||
* 1. Initial setup of aggregation
|
||||
* 2. Renegotiation of current recv window.
|
||||
* Window size for re-ordering is limited by target buffer
|
||||
* space, which is reflected in win_sz.
|
||||
* (Re)Start the periodic timer to deliver long standing frames,
|
||||
* in hold_q to OS.
|
||||
*/
|
||||
void
|
||||
aggr_recv_addba_req_evt(void * cntxt, u8 tid, u16 seq_no, u8 win_sz);
|
||||
|
||||
|
||||
/*
|
||||
* aggr_recv_delba_req_evt:
|
||||
* Target indicates deletion of a BA window for a tid via the
|
||||
* WMI_DELBA_EVENTID. Host would deliver all the frames in the
|
||||
* hold_q, reset tid config and disable the periodic timer, if
|
||||
* aggr is not enabled on any tid.
|
||||
*/
|
||||
void
|
||||
aggr_recv_delba_req_evt(void * cntxt, u8 tid);
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* aggr_process_recv_frm:
|
||||
* Called only for data frames. When aggr is ON for a tid, the buffer
|
||||
* is always consumed, and osbuf would be NULL. For a non-aggr case,
|
||||
* osbuf is not modified.
|
||||
* AMSDU frames are consumed and are later freed. They are sliced and
|
||||
* diced to individual frames and dispatched to stack.
|
||||
* After consuming a osbuf(when aggr is ON), a previously registered
|
||||
* callback may be called to deliver frames in order.
|
||||
*/
|
||||
void
|
||||
aggr_process_recv_frm(void *cntxt, u8 tid, u16 seq_no, bool is_amsdu, void **osbuf);
|
||||
|
||||
|
||||
/*
|
||||
* aggr_module_destroy:
|
||||
* Frees up all the queues and frames in them. Releases the cntxt to OS.
|
||||
*/
|
||||
void
|
||||
aggr_module_destroy(void *cntxt);
|
||||
|
||||
/*
|
||||
* Dumps the aggregation stats
|
||||
*/
|
||||
void
|
||||
aggr_dump_stats(void *cntxt, PACKET_LOG **log_buf);
|
||||
|
||||
/*
|
||||
* aggr_reset_state -- Called when it is deemed necessary to clear the aggregate
|
||||
* hold Q state. Examples include when a Connect event or disconnect event is
|
||||
* received.
|
||||
*/
|
||||
void
|
||||
aggr_reset_state(void *cntxt);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__AGGR_RECV_API_H__ */
|
|
@ -1,65 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
/* AR3K module configuration APIs for HCI-bridge operation */
|
||||
|
||||
#ifndef AR3KCONFIG_H_
|
||||
#define AR3KCONFIG_H_
|
||||
|
||||
#include <net/bluetooth/bluetooth.h>
|
||||
#include <net/bluetooth/hci_core.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AR3K_CONFIG_FLAG_FORCE_MINBOOT_EXIT (1 << 0)
|
||||
#define AR3K_CONFIG_FLAG_SET_AR3K_BAUD (1 << 1)
|
||||
#define AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY (1 << 2)
|
||||
#define AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP (1 << 3)
|
||||
|
||||
|
||||
struct ar3k_config_info {
|
||||
u32 Flags; /* config flags */
|
||||
void *pHCIDev; /* HCI bridge device */
|
||||
struct hci_transport_properties *pHCIProps; /* HCI bridge props */
|
||||
struct hif_device *pHIFDevice; /* HIF layer device */
|
||||
|
||||
u32 AR3KBaudRate; /* AR3K operational baud rate */
|
||||
u16 AR6KScale; /* AR6K UART scale value */
|
||||
u16 AR6KStep; /* AR6K UART step value */
|
||||
struct hci_dev *pBtStackHCIDev; /* BT Stack HCI dev */
|
||||
u32 PwrMgmtEnabled; /* TLPM enabled? */
|
||||
u16 IdleTimeout; /* TLPM idle timeout */
|
||||
u16 WakeupTimeout; /* TLPM wakeup timeout */
|
||||
u8 bdaddr[6]; /* Bluetooth device address */
|
||||
};
|
||||
|
||||
int AR3KConfigure(struct ar3k_config_info *pConfigInfo);
|
||||
|
||||
int AR3KConfigureExit(void *config);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*AR3KCONFIG_H_*/
|
|
@ -1,32 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="ar6000_api.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// This file contains the API to access the OS dependent atheros host driver
|
||||
// by the WMI or WLAN generic modules.
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _AR6000_API_H_
|
||||
#define _AR6000_API_H_
|
||||
|
||||
#include "../os/linux/include/ar6xapi_linux.h"
|
||||
|
||||
#endif /* _AR6000_API_H */
|
||||
|
|
@ -1,48 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="ar6000_diag.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef AR6000_DIAG_H_
|
||||
#define AR6000_DIAG_H_
|
||||
|
||||
|
||||
int
|
||||
ar6000_ReadRegDiag(struct hif_device *hifDevice, u32 *address, u32 *data);
|
||||
|
||||
int
|
||||
ar6000_WriteRegDiag(struct hif_device *hifDevice, u32 *address, u32 *data);
|
||||
|
||||
int
|
||||
ar6000_ReadDataDiag(struct hif_device *hifDevice, u32 address,
|
||||
u8 *data, u32 length);
|
||||
|
||||
int
|
||||
ar6000_WriteDataDiag(struct hif_device *hifDevice, u32 address,
|
||||
u8 *data, u32 length);
|
||||
|
||||
int
|
||||
ar6k_ReadTargetRegister(struct hif_device *hifDevice, int regsel, u32 *regval);
|
||||
|
||||
void
|
||||
ar6k_FetchTargetRegs(struct hif_device *hifDevice, u32 *targregs);
|
||||
|
||||
#endif /*AR6000_DIAG_H_*/
|
|
@ -1,44 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
|
||||
// <copyright file="ar6kap_common.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
//==============================================================================
|
||||
|
||||
// This file contains the definitions of common AP mode data structures.
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef _AR6KAP_COMMON_H_
|
||||
#define _AR6KAP_COMMON_H_
|
||||
/*
|
||||
* Used with AR6000_XIOCTL_AP_GET_STA_LIST
|
||||
*/
|
||||
typedef struct {
|
||||
u8 mac[ATH_MAC_LEN];
|
||||
u8 aid;
|
||||
u8 keymgmt;
|
||||
u8 ucipher;
|
||||
u8 auth;
|
||||
} station_t;
|
||||
typedef struct {
|
||||
station_t sta[AP_MAX_NUM_STA];
|
||||
} ap_get_sta_t;
|
||||
#endif /* _AR6KAP_COMMON_H_ */
|
|
@ -1,135 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="athbtfilter.h" company="Atheros">
|
||||
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Public Bluetooth filter APIs
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef ATHBTFILTER_H_
|
||||
#define ATHBTFILTER_H_
|
||||
|
||||
#define ATH_DEBUG_INFO (1 << 2)
|
||||
#define ATH_DEBUG_INF ATH_DEBUG_INFO
|
||||
|
||||
typedef enum _ATHBT_HCI_CTRL_TYPE {
|
||||
ATHBT_HCI_COMMAND = 0,
|
||||
ATHBT_HCI_EVENT = 1,
|
||||
} ATHBT_HCI_CTRL_TYPE;
|
||||
|
||||
typedef enum _ATHBT_STATE_INDICATION {
|
||||
ATH_BT_NOOP = 0,
|
||||
ATH_BT_INQUIRY = 1,
|
||||
ATH_BT_CONNECT = 2,
|
||||
ATH_BT_SCO = 3,
|
||||
ATH_BT_ACL = 4,
|
||||
ATH_BT_A2DP = 5,
|
||||
ATH_BT_ESCO = 6,
|
||||
/* new states go here.. */
|
||||
|
||||
ATH_BT_MAX_STATE_INDICATION
|
||||
} ATHBT_STATE_INDICATION;
|
||||
|
||||
/* filter function for OUTGOING commands and INCOMMING events */
|
||||
typedef void (*ATHBT_FILTER_CMD_EVENTS_FN)(void *pContext, ATHBT_HCI_CTRL_TYPE Type, unsigned char *pBuffer, int Length);
|
||||
|
||||
/* filter function for OUTGOING data HCI packets */
|
||||
typedef void (*ATHBT_FILTER_DATA_FN)(void *pContext, unsigned char *pBuffer, int Length);
|
||||
|
||||
typedef enum _ATHBT_STATE {
|
||||
STATE_OFF = 0,
|
||||
STATE_ON = 1,
|
||||
STATE_MAX
|
||||
} ATHBT_STATE;
|
||||
|
||||
/* BT state indication (when filter functions are not used) */
|
||||
|
||||
typedef void (*ATHBT_INDICATE_STATE_FN)(void *pContext, ATHBT_STATE_INDICATION Indication, ATHBT_STATE State, unsigned char LMPVersion);
|
||||
|
||||
struct athbt_filter_instance {
|
||||
#ifdef UNDER_CE
|
||||
WCHAR *pWlanAdapterName; /* filled in by user */
|
||||
#else
|
||||
char *pWlanAdapterName; /* filled in by user */
|
||||
#endif /* UNDER_CE */
|
||||
int FilterEnabled; /* filtering is enabled */
|
||||
int Attached; /* filter library is attached */
|
||||
void *pContext; /* private context for filter library */
|
||||
ATHBT_FILTER_CMD_EVENTS_FN pFilterCmdEvents; /* function ptr to filter a command or event */
|
||||
ATHBT_FILTER_DATA_FN pFilterAclDataOut; /* function ptr to filter ACL data out (to radio) */
|
||||
ATHBT_FILTER_DATA_FN pFilterAclDataIn; /* function ptr to filter ACL data in (from radio) */
|
||||
ATHBT_INDICATE_STATE_FN pIndicateState; /* function ptr to indicate a state */
|
||||
}; /* XXX: unused ? */
|
||||
|
||||
|
||||
/* API MACROS */
|
||||
|
||||
#define AthBtFilterHciCommand(instance,packet,length) \
|
||||
if ((instance)->FilterEnabled) { \
|
||||
(instance)->pFilterCmdEvents((instance)->pContext, \
|
||||
ATHBT_HCI_COMMAND, \
|
||||
(unsigned char *)(packet), \
|
||||
(length)); \
|
||||
}
|
||||
|
||||
#define AthBtFilterHciEvent(instance,packet,length) \
|
||||
if ((instance)->FilterEnabled) { \
|
||||
(instance)->pFilterCmdEvents((instance)->pContext, \
|
||||
ATHBT_HCI_EVENT, \
|
||||
(unsigned char *)(packet), \
|
||||
(length)); \
|
||||
}
|
||||
|
||||
#define AthBtFilterHciAclDataOut(instance,packet,length) \
|
||||
if ((instance)->FilterEnabled) { \
|
||||
(instance)->pFilterAclDataOut((instance)->pContext, \
|
||||
(unsigned char *)(packet), \
|
||||
(length)); \
|
||||
}
|
||||
|
||||
#define AthBtFilterHciAclDataIn(instance,packet,length) \
|
||||
if ((instance)->FilterEnabled) { \
|
||||
(instance)->pFilterAclDataIn((instance)->pContext, \
|
||||
(unsigned char *)(packet), \
|
||||
(length)); \
|
||||
}
|
||||
|
||||
/* if filtering is not desired, the application can indicate the state directly using this
|
||||
* macro:
|
||||
*/
|
||||
#define AthBtIndicateState(instance,indication,state) \
|
||||
if ((instance)->FilterEnabled) { \
|
||||
(instance)->pIndicateState((instance)->pContext, \
|
||||
(indication), \
|
||||
(state), \
|
||||
0); \
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* API prototypes */
|
||||
int AthBtFilter_Attach(ATH_BT_FILTER_INSTANCE *pInstance, unsigned int flags);
|
||||
void AthBtFilter_Detach(ATH_BT_FILTER_INSTANCE *pInstance);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*ATHBTFILTER_H_*/
|
|
@ -1,134 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="bmi.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// BMI declarations and prototypes
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _BMI_H_
|
||||
#define _BMI_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Header files */
|
||||
#include "a_config.h"
|
||||
#include "athdefs.h"
|
||||
#include "hif.h"
|
||||
#include "a_osapi.h"
|
||||
#include "bmi_msg.h"
|
||||
|
||||
void
|
||||
BMIInit(void);
|
||||
|
||||
void
|
||||
BMICleanup(void);
|
||||
|
||||
int
|
||||
BMIDone(struct hif_device *device);
|
||||
|
||||
int
|
||||
BMIGetTargetInfo(struct hif_device *device, struct bmi_target_info *targ_info);
|
||||
|
||||
int
|
||||
BMIReadMemory(struct hif_device *device,
|
||||
u32 address,
|
||||
u8 *buffer,
|
||||
u32 length);
|
||||
|
||||
int
|
||||
BMIWriteMemory(struct hif_device *device,
|
||||
u32 address,
|
||||
u8 *buffer,
|
||||
u32 length);
|
||||
|
||||
int
|
||||
BMIExecute(struct hif_device *device,
|
||||
u32 address,
|
||||
u32 *param);
|
||||
|
||||
int
|
||||
BMISetAppStart(struct hif_device *device,
|
||||
u32 address);
|
||||
|
||||
int
|
||||
BMIReadSOCRegister(struct hif_device *device,
|
||||
u32 address,
|
||||
u32 *param);
|
||||
|
||||
int
|
||||
BMIWriteSOCRegister(struct hif_device *device,
|
||||
u32 address,
|
||||
u32 param);
|
||||
|
||||
int
|
||||
BMIrompatchInstall(struct hif_device *device,
|
||||
u32 ROM_addr,
|
||||
u32 RAM_addr,
|
||||
u32 nbytes,
|
||||
u32 do_activate,
|
||||
u32 *patch_id);
|
||||
|
||||
int
|
||||
BMIrompatchUninstall(struct hif_device *device,
|
||||
u32 rompatch_id);
|
||||
|
||||
int
|
||||
BMIrompatchActivate(struct hif_device *device,
|
||||
u32 rompatch_count,
|
||||
u32 *rompatch_list);
|
||||
|
||||
int
|
||||
BMIrompatchDeactivate(struct hif_device *device,
|
||||
u32 rompatch_count,
|
||||
u32 *rompatch_list);
|
||||
|
||||
int
|
||||
BMILZStreamStart(struct hif_device *device,
|
||||
u32 address);
|
||||
|
||||
int
|
||||
BMILZData(struct hif_device *device,
|
||||
u8 *buffer,
|
||||
u32 length);
|
||||
|
||||
int
|
||||
BMIFastDownload(struct hif_device *device,
|
||||
u32 address,
|
||||
u8 *buffer,
|
||||
u32 length);
|
||||
|
||||
int
|
||||
BMIRawWrite(struct hif_device *device,
|
||||
u8 *buffer,
|
||||
u32 length);
|
||||
|
||||
int
|
||||
BMIRawRead(struct hif_device *device,
|
||||
u8 *buffer,
|
||||
u32 length,
|
||||
bool want_timeout);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _BMI_H_ */
|
|
@ -1,52 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="AR6K_version.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#define __VER_MAJOR_ 3
|
||||
#define __VER_MINOR_ 0
|
||||
#define __VER_PATCH_ 0
|
||||
|
||||
/* The makear6ksdk script (used for release builds) modifies the following line. */
|
||||
#define __BUILD_NUMBER_ 233
|
||||
|
||||
|
||||
/* Format of the version number. */
|
||||
#define VER_MAJOR_BIT_OFFSET 28
|
||||
#define VER_MINOR_BIT_OFFSET 24
|
||||
#define VER_PATCH_BIT_OFFSET 16
|
||||
#define VER_BUILD_NUM_BIT_OFFSET 0
|
||||
|
||||
|
||||
/*
|
||||
* The version has the following format:
|
||||
* Bits 28-31: Major version
|
||||
* Bits 24-27: Minor version
|
||||
* Bits 16-23: Patch version
|
||||
* Bits 0-15: Build number (automatically generated during build process )
|
||||
* E.g. Build 1.1.3.7 would be represented as 0x11030007.
|
||||
*
|
||||
* DO NOT split the following macro into multiple lines as this may confuse the build scripts.
|
||||
*/
|
||||
#define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
|
||||
|
||||
/* ABI Version. Reflects the version of binary interface exposed by AR6K target firmware. Needs to be incremented by 1 for any change in the firmware that requires upgrade of the driver on the host side for the change to work correctly */
|
||||
#define AR6K_ABI_VERSION 1
|
|
@ -1,90 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __ADDRS_H__
|
||||
#define __ADDRS_H__
|
||||
|
||||
/*
|
||||
* Special AR6002 Addresses that may be needed by special
|
||||
* applications (e.g. ART) on the Host as well as Target.
|
||||
*/
|
||||
|
||||
#if defined(AR6002_REV2)
|
||||
#define AR6K_RAM_START 0x00500000
|
||||
#define TARG_RAM_OFFSET(vaddr) ((u32)(vaddr) & 0xfffff)
|
||||
#define TARG_RAM_SZ (184*1024)
|
||||
#define TARG_ROM_SZ (80*1024)
|
||||
#endif
|
||||
#if defined(AR6002_REV4) || defined(AR6003)
|
||||
#define AR6K_RAM_START 0x00540000
|
||||
#define TARG_RAM_OFFSET(vaddr) (((u32)(vaddr) & 0xfffff) - 0x40000)
|
||||
#define TARG_RAM_SZ (256*1024)
|
||||
#define TARG_ROM_SZ (256*1024)
|
||||
#endif
|
||||
|
||||
#define AR6002_BOARD_DATA_SZ 768
|
||||
#define AR6002_BOARD_EXT_DATA_SZ 0
|
||||
#define AR6003_BOARD_DATA_SZ 1024
|
||||
#define AR6003_BOARD_EXT_DATA_SZ 768
|
||||
|
||||
#define AR6K_RAM_ADDR(byte_offset) (AR6K_RAM_START+(byte_offset))
|
||||
#define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset)
|
||||
|
||||
#define AR6K_ROM_START 0x004e0000
|
||||
#define TARG_ROM_OFFSET(vaddr) (((u32)(vaddr) & 0x1fffff) - 0xe0000)
|
||||
#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset))
|
||||
#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset)
|
||||
|
||||
/*
|
||||
* At this ROM address is a pointer to the start of the ROM DataSet Index.
|
||||
* If there are no ROM DataSets, there's a 0 at this address.
|
||||
*/
|
||||
#define ROM_DATASET_INDEX_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-8)
|
||||
#define ROM_MBIST_CKSUM_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-4)
|
||||
|
||||
/*
|
||||
* The API A_BOARD_DATA_ADDR() is the proper way to get a read pointer to
|
||||
* board data.
|
||||
*/
|
||||
|
||||
/* Size of Board Data, in bytes */
|
||||
#if defined(AR6002_REV4) || defined(AR6003)
|
||||
#define BOARD_DATA_SZ AR6003_BOARD_DATA_SZ
|
||||
#else
|
||||
#define BOARD_DATA_SZ AR6002_BOARD_DATA_SZ
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Constants used by ASM code to access fields of host_interest_s,
|
||||
* which is at a fixed location in RAM.
|
||||
*/
|
||||
#if defined(AR6002_REV4) || defined(AR6003)
|
||||
#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x60c)
|
||||
#else
|
||||
#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x40c)
|
||||
#endif
|
||||
#define FLASH_IS_PRESENT_TARGADDR HOST_INTEREST_FLASH_IS_PRESENT_ADDR
|
||||
|
||||
#endif /* __ADDRS_H__ */
|
||||
|
||||
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
// ------------------------------------------------------------------
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
// ------------------------------------------------------------------
|
||||
//===================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//===================================================================
|
||||
|
||||
|
||||
#ifndef _APB_ATHR_WLAN_MAP_H_
|
||||
#define _APB_ATHR_WLAN_MAP_H_
|
||||
|
||||
#define WLAN_RTC_BASE_ADDRESS 0x00004000
|
||||
#define WLAN_VMC_BASE_ADDRESS 0x00008000
|
||||
#define WLAN_UART_BASE_ADDRESS 0x0000c000
|
||||
#define WLAN_DBG_UART_BASE_ADDRESS 0x0000d000
|
||||
#define WLAN_UMBOX_BASE_ADDRESS 0x0000e000
|
||||
#define WLAN_SI_BASE_ADDRESS 0x00010000
|
||||
#define WLAN_GPIO_BASE_ADDRESS 0x00014000
|
||||
#define WLAN_MBOX_BASE_ADDRESS 0x00018000
|
||||
#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
|
||||
#define WLAN_MAC_BASE_ADDRESS 0x00020000
|
||||
#define WLAN_RDMA_BASE_ADDRESS 0x00030100
|
||||
#define EFUSE_BASE_ADDRESS 0x00031000
|
||||
|
||||
#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */
|
|
@ -1,40 +0,0 @@
|
|||
// ------------------------------------------------------------------
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
// ------------------------------------------------------------------
|
||||
//===================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//===================================================================
|
||||
|
||||
|
||||
#include "apb_athr_wlan_map.h"
|
||||
|
||||
#ifndef BT_HEADERS
|
||||
|
||||
#define RTC_BASE_ADDRESS WLAN_RTC_BASE_ADDRESS
|
||||
#define VMC_BASE_ADDRESS WLAN_VMC_BASE_ADDRESS
|
||||
#define UART_BASE_ADDRESS WLAN_UART_BASE_ADDRESS
|
||||
#define DBG_UART_BASE_ADDRESS WLAN_DBG_UART_BASE_ADDRESS
|
||||
#define UMBOX_BASE_ADDRESS WLAN_UMBOX_BASE_ADDRESS
|
||||
#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
|
||||
#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
|
||||
#define MBOX_BASE_ADDRESS WLAN_MBOX_BASE_ADDRESS
|
||||
#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
|
||||
#define MAC_BASE_ADDRESS WLAN_MAC_BASE_ADDRESS
|
||||
#define RDMA_BASE_ADDRESS WLAN_RDMA_BASE_ADDRESS
|
||||
|
||||
#endif
|
|
@ -1,24 +0,0 @@
|
|||
// ------------------------------------------------------------------
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
// ------------------------------------------------------------------
|
||||
//===================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//===================================================================
|
||||
|
||||
|
||||
#include "mbox_wlan_host_reg.h"
|
|
@ -1,552 +0,0 @@
|
|||
// ------------------------------------------------------------------
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
// ------------------------------------------------------------------
|
||||
//===================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//===================================================================
|
||||
|
||||
|
||||
#include "mbox_wlan_reg.h"
|
||||
|
||||
#ifndef BT_HEADERS
|
||||
|
||||
#define MBOX_FIFO_ADDRESS WLAN_MBOX_FIFO_ADDRESS
|
||||
#define MBOX_FIFO_OFFSET WLAN_MBOX_FIFO_OFFSET
|
||||
#define MBOX_FIFO_DATA_MSB WLAN_MBOX_FIFO_DATA_MSB
|
||||
#define MBOX_FIFO_DATA_LSB WLAN_MBOX_FIFO_DATA_LSB
|
||||
#define MBOX_FIFO_DATA_MASK WLAN_MBOX_FIFO_DATA_MASK
|
||||
#define MBOX_FIFO_DATA_GET(x) WLAN_MBOX_FIFO_DATA_GET(x)
|
||||
#define MBOX_FIFO_DATA_SET(x) WLAN_MBOX_FIFO_DATA_SET(x)
|
||||
#define MBOX_FIFO_STATUS_ADDRESS WLAN_MBOX_FIFO_STATUS_ADDRESS
|
||||
#define MBOX_FIFO_STATUS_OFFSET WLAN_MBOX_FIFO_STATUS_OFFSET
|
||||
#define MBOX_FIFO_STATUS_EMPTY_MSB WLAN_MBOX_FIFO_STATUS_EMPTY_MSB
|
||||
#define MBOX_FIFO_STATUS_EMPTY_LSB WLAN_MBOX_FIFO_STATUS_EMPTY_LSB
|
||||
#define MBOX_FIFO_STATUS_EMPTY_MASK WLAN_MBOX_FIFO_STATUS_EMPTY_MASK
|
||||
#define MBOX_FIFO_STATUS_EMPTY_GET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x)
|
||||
#define MBOX_FIFO_STATUS_EMPTY_SET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x)
|
||||
#define MBOX_FIFO_STATUS_FULL_MSB WLAN_MBOX_FIFO_STATUS_FULL_MSB
|
||||
#define MBOX_FIFO_STATUS_FULL_LSB WLAN_MBOX_FIFO_STATUS_FULL_LSB
|
||||
#define MBOX_FIFO_STATUS_FULL_MASK WLAN_MBOX_FIFO_STATUS_FULL_MASK
|
||||
#define MBOX_FIFO_STATUS_FULL_GET(x) WLAN_MBOX_FIFO_STATUS_FULL_GET(x)
|
||||
#define MBOX_FIFO_STATUS_FULL_SET(x) WLAN_MBOX_FIFO_STATUS_FULL_SET(x)
|
||||
#define MBOX_DMA_POLICY_ADDRESS WLAN_MBOX_DMA_POLICY_ADDRESS
|
||||
#define MBOX_DMA_POLICY_OFFSET WLAN_MBOX_DMA_POLICY_OFFSET
|
||||
#define MBOX_DMA_POLICY_TX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB
|
||||
#define MBOX_DMA_POLICY_TX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB
|
||||
#define MBOX_DMA_POLICY_TX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK
|
||||
#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x)
|
||||
#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x)
|
||||
#define MBOX_DMA_POLICY_TX_ORDER_MSB WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB
|
||||
#define MBOX_DMA_POLICY_TX_ORDER_LSB WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB
|
||||
#define MBOX_DMA_POLICY_TX_ORDER_MASK WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK
|
||||
#define MBOX_DMA_POLICY_TX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x)
|
||||
#define MBOX_DMA_POLICY_TX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x)
|
||||
#define MBOX_DMA_POLICY_RX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB
|
||||
#define MBOX_DMA_POLICY_RX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB
|
||||
#define MBOX_DMA_POLICY_RX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK
|
||||
#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x)
|
||||
#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x)
|
||||
#define MBOX_DMA_POLICY_RX_ORDER_MSB WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB
|
||||
#define MBOX_DMA_POLICY_RX_ORDER_LSB WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB
|
||||
#define MBOX_DMA_POLICY_RX_ORDER_MASK WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK
|
||||
#define MBOX_DMA_POLICY_RX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x)
|
||||
#define MBOX_DMA_POLICY_RX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x)
|
||||
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS
|
||||
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET
|
||||
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
|
||||
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
|
||||
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
|
||||
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
|
||||
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
|
||||
#define MBOX0_DMA_RX_CONTROL_ADDRESS WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS
|
||||
#define MBOX0_DMA_RX_CONTROL_OFFSET WLAN_MBOX0_DMA_RX_CONTROL_OFFSET
|
||||
#define MBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB
|
||||
#define MBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB
|
||||
#define MBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK
|
||||
#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x)
|
||||
#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x)
|
||||
#define MBOX0_DMA_RX_CONTROL_START_MSB WLAN_MBOX0_DMA_RX_CONTROL_START_MSB
|
||||
#define MBOX0_DMA_RX_CONTROL_START_LSB WLAN_MBOX0_DMA_RX_CONTROL_START_LSB
|
||||
#define MBOX0_DMA_RX_CONTROL_START_MASK WLAN_MBOX0_DMA_RX_CONTROL_START_MASK
|
||||
#define MBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x)
|
||||
#define MBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x)
|
||||
#define MBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB
|
||||
#define MBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB
|
||||
#define MBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK
|
||||
#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x)
|
||||
#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x)
|
||||
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS
|
||||
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET
|
||||
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
|
||||
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
|
||||
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
|
||||
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
|
||||
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
|
||||
#define MBOX0_DMA_TX_CONTROL_ADDRESS WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS
|
||||
#define MBOX0_DMA_TX_CONTROL_OFFSET WLAN_MBOX0_DMA_TX_CONTROL_OFFSET
|
||||
#define MBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB
|
||||
#define MBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB
|
||||
#define MBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK
|
||||
#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x)
|
||||
#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x)
|
||||
#define MBOX0_DMA_TX_CONTROL_START_MSB WLAN_MBOX0_DMA_TX_CONTROL_START_MSB
|
||||
#define MBOX0_DMA_TX_CONTROL_START_LSB WLAN_MBOX0_DMA_TX_CONTROL_START_LSB
|
||||
#define MBOX0_DMA_TX_CONTROL_START_MASK WLAN_MBOX0_DMA_TX_CONTROL_START_MASK
|
||||
#define MBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x)
|
||||
#define MBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x)
|
||||
#define MBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB
|
||||
#define MBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB
|
||||
#define MBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK
|
||||
#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x)
|
||||
#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x)
|
||||
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS
|
||||
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET
|
||||
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
|
||||
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
|
||||
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
|
||||
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
|
||||
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
|
||||
#define MBOX1_DMA_RX_CONTROL_ADDRESS WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS
|
||||
#define MBOX1_DMA_RX_CONTROL_OFFSET WLAN_MBOX1_DMA_RX_CONTROL_OFFSET
|
||||
#define MBOX1_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB
|
||||
#define MBOX1_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB
|
||||
#define MBOX1_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK
|
||||
#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x)
|
||||
#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x)
|
||||
#define MBOX1_DMA_RX_CONTROL_START_MSB WLAN_MBOX1_DMA_RX_CONTROL_START_MSB
|
||||
#define MBOX1_DMA_RX_CONTROL_START_LSB WLAN_MBOX1_DMA_RX_CONTROL_START_LSB
|
||||
#define MBOX1_DMA_RX_CONTROL_START_MASK WLAN_MBOX1_DMA_RX_CONTROL_START_MASK
|
||||
#define MBOX1_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x)
|
||||
#define MBOX1_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x)
|
||||
#define MBOX1_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB
|
||||
#define MBOX1_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB
|
||||
#define MBOX1_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK
|
||||
#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x)
|
||||
#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x)
|
||||
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS
|
||||
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET
|
||||
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
|
||||
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
|
||||
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
|
||||
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
|
||||
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
|
||||
#define MBOX1_DMA_TX_CONTROL_ADDRESS WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS
|
||||
#define MBOX1_DMA_TX_CONTROL_OFFSET WLAN_MBOX1_DMA_TX_CONTROL_OFFSET
|
||||
#define MBOX1_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB
|
||||
#define MBOX1_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB
|
||||
#define MBOX1_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK
|
||||
#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x)
|
||||
#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x)
|
||||
#define MBOX1_DMA_TX_CONTROL_START_MSB WLAN_MBOX1_DMA_TX_CONTROL_START_MSB
|
||||
#define MBOX1_DMA_TX_CONTROL_START_LSB WLAN_MBOX1_DMA_TX_CONTROL_START_LSB
|
||||
#define MBOX1_DMA_TX_CONTROL_START_MASK WLAN_MBOX1_DMA_TX_CONTROL_START_MASK
|
||||
#define MBOX1_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x)
|
||||
#define MBOX1_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x)
|
||||
#define MBOX1_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB
|
||||
#define MBOX1_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB
|
||||
#define MBOX1_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK
|
||||
#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x)
|
||||
#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x)
|
||||
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS
|
||||
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET
|
||||
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
|
||||
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
|
||||
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
|
||||
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
|
||||
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
|
||||
#define MBOX2_DMA_RX_CONTROL_ADDRESS WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS
|
||||
#define MBOX2_DMA_RX_CONTROL_OFFSET WLAN_MBOX2_DMA_RX_CONTROL_OFFSET
|
||||
#define MBOX2_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB
|
||||
#define MBOX2_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB
|
||||
#define MBOX2_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK
|
||||
#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x)
|
||||
#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x)
|
||||
#define MBOX2_DMA_RX_CONTROL_START_MSB WLAN_MBOX2_DMA_RX_CONTROL_START_MSB
|
||||
#define MBOX2_DMA_RX_CONTROL_START_LSB WLAN_MBOX2_DMA_RX_CONTROL_START_LSB
|
||||
#define MBOX2_DMA_RX_CONTROL_START_MASK WLAN_MBOX2_DMA_RX_CONTROL_START_MASK
|
||||
#define MBOX2_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x)
|
||||
#define MBOX2_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x)
|
||||
#define MBOX2_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB
|
||||
#define MBOX2_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB
|
||||
#define MBOX2_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK
|
||||
#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x)
|
||||
#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x)
|
||||
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS
|
||||
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET
|
||||
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
|
||||
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
|
||||
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
|
||||
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
|
||||
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
|
||||
#define MBOX2_DMA_TX_CONTROL_ADDRESS WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS
|
||||
#define MBOX2_DMA_TX_CONTROL_OFFSET WLAN_MBOX2_DMA_TX_CONTROL_OFFSET
|
||||
#define MBOX2_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB
|
||||
#define MBOX2_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB
|
||||
#define MBOX2_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK
|
||||
#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x)
|
||||
#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x)
|
||||
#define MBOX2_DMA_TX_CONTROL_START_MSB WLAN_MBOX2_DMA_TX_CONTROL_START_MSB
|
||||
#define MBOX2_DMA_TX_CONTROL_START_LSB WLAN_MBOX2_DMA_TX_CONTROL_START_LSB
|
||||
#define MBOX2_DMA_TX_CONTROL_START_MASK WLAN_MBOX2_DMA_TX_CONTROL_START_MASK
|
||||
#define MBOX2_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x)
|
||||
#define MBOX2_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x)
|
||||
#define MBOX2_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB
|
||||
#define MBOX2_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB
|
||||
#define MBOX2_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK
|
||||
#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x)
|
||||
#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x)
|
||||
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS
|
||||
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET
|
||||
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
|
||||
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
|
||||
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
|
||||
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
|
||||
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
|
||||
#define MBOX3_DMA_RX_CONTROL_ADDRESS WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS
|
||||
#define MBOX3_DMA_RX_CONTROL_OFFSET WLAN_MBOX3_DMA_RX_CONTROL_OFFSET
|
||||
#define MBOX3_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB
|
||||
#define MBOX3_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB
|
||||
#define MBOX3_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK
|
||||
#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x)
|
||||
#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x)
|
||||
#define MBOX3_DMA_RX_CONTROL_START_MSB WLAN_MBOX3_DMA_RX_CONTROL_START_MSB
|
||||
#define MBOX3_DMA_RX_CONTROL_START_LSB WLAN_MBOX3_DMA_RX_CONTROL_START_LSB
|
||||
#define MBOX3_DMA_RX_CONTROL_START_MASK WLAN_MBOX3_DMA_RX_CONTROL_START_MASK
|
||||
#define MBOX3_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x)
|
||||
#define MBOX3_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x)
|
||||
#define MBOX3_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB
|
||||
#define MBOX3_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB
|
||||
#define MBOX3_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK
|
||||
#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x)
|
||||
#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x)
|
||||
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS
|
||||
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET
|
||||
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
|
||||
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
|
||||
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
|
||||
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
|
||||
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
|
||||
#define MBOX3_DMA_TX_CONTROL_ADDRESS WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS
|
||||
#define MBOX3_DMA_TX_CONTROL_OFFSET WLAN_MBOX3_DMA_TX_CONTROL_OFFSET
|
||||
#define MBOX3_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB
|
||||
#define MBOX3_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB
|
||||
#define MBOX3_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK
|
||||
#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x)
|
||||
#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x)
|
||||
#define MBOX3_DMA_TX_CONTROL_START_MSB WLAN_MBOX3_DMA_TX_CONTROL_START_MSB
|
||||
#define MBOX3_DMA_TX_CONTROL_START_LSB WLAN_MBOX3_DMA_TX_CONTROL_START_LSB
|
||||
#define MBOX3_DMA_TX_CONTROL_START_MASK WLAN_MBOX3_DMA_TX_CONTROL_START_MASK
|
||||
#define MBOX3_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x)
|
||||
#define MBOX3_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x)
|
||||
#define MBOX3_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB
|
||||
#define MBOX3_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB
|
||||
#define MBOX3_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK
|
||||
#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x)
|
||||
#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x)
|
||||
#define MBOX_INT_STATUS_ADDRESS WLAN_MBOX_INT_STATUS_ADDRESS
|
||||
#define MBOX_INT_STATUS_OFFSET WLAN_MBOX_INT_STATUS_OFFSET
|
||||
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB
|
||||
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB
|
||||
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK
|
||||
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)
|
||||
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)
|
||||
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB
|
||||
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB
|
||||
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK
|
||||
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x)
|
||||
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x)
|
||||
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB
|
||||
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB
|
||||
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK
|
||||
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)
|
||||
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)
|
||||
#define MBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB
|
||||
#define MBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB
|
||||
#define MBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK
|
||||
#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x)
|
||||
#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x)
|
||||
#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB
|
||||
#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB
|
||||
#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK
|
||||
#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x)
|
||||
#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x)
|
||||
#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB
|
||||
#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB
|
||||
#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK
|
||||
#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)
|
||||
#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)
|
||||
#define MBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB
|
||||
#define MBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB
|
||||
#define MBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK
|
||||
#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x)
|
||||
#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x)
|
||||
#define MBOX_INT_STATUS_HOST_MSB WLAN_MBOX_INT_STATUS_HOST_MSB
|
||||
#define MBOX_INT_STATUS_HOST_LSB WLAN_MBOX_INT_STATUS_HOST_LSB
|
||||
#define MBOX_INT_STATUS_HOST_MASK WLAN_MBOX_INT_STATUS_HOST_MASK
|
||||
#define MBOX_INT_STATUS_HOST_GET(x) WLAN_MBOX_INT_STATUS_HOST_GET(x)
|
||||
#define MBOX_INT_STATUS_HOST_SET(x) WLAN_MBOX_INT_STATUS_HOST_SET(x)
|
||||
#define MBOX_INT_ENABLE_ADDRESS WLAN_MBOX_INT_ENABLE_ADDRESS
|
||||
#define MBOX_INT_ENABLE_OFFSET WLAN_MBOX_INT_ENABLE_OFFSET
|
||||
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB
|
||||
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB
|
||||
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK
|
||||
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)
|
||||
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)
|
||||
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB
|
||||
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB
|
||||
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK
|
||||
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x)
|
||||
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x)
|
||||
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB
|
||||
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB
|
||||
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK
|
||||
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)
|
||||
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)
|
||||
#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB
|
||||
#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB
|
||||
#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK
|
||||
#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x)
|
||||
#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x)
|
||||
#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB
|
||||
#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB
|
||||
#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK
|
||||
#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)
|
||||
#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)
|
||||
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB
|
||||
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB
|
||||
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK
|
||||
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)
|
||||
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)
|
||||
#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB
|
||||
#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB
|
||||
#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK
|
||||
#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x)
|
||||
#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x)
|
||||
#define MBOX_INT_ENABLE_HOST_MSB WLAN_MBOX_INT_ENABLE_HOST_MSB
|
||||
#define MBOX_INT_ENABLE_HOST_LSB WLAN_MBOX_INT_ENABLE_HOST_LSB
|
||||
#define MBOX_INT_ENABLE_HOST_MASK WLAN_MBOX_INT_ENABLE_HOST_MASK
|
||||
#define MBOX_INT_ENABLE_HOST_GET(x) WLAN_MBOX_INT_ENABLE_HOST_GET(x)
|
||||
#define MBOX_INT_ENABLE_HOST_SET(x) WLAN_MBOX_INT_ENABLE_HOST_SET(x)
|
||||
#define INT_HOST_ADDRESS WLAN_INT_HOST_ADDRESS
|
||||
#define INT_HOST_OFFSET WLAN_INT_HOST_OFFSET
|
||||
#define INT_HOST_VECTOR_MSB WLAN_INT_HOST_VECTOR_MSB
|
||||
#define INT_HOST_VECTOR_LSB WLAN_INT_HOST_VECTOR_LSB
|
||||
#define INT_HOST_VECTOR_MASK WLAN_INT_HOST_VECTOR_MASK
|
||||
#define INT_HOST_VECTOR_GET(x) WLAN_INT_HOST_VECTOR_GET(x)
|
||||
#define INT_HOST_VECTOR_SET(x) WLAN_INT_HOST_VECTOR_SET(x)
|
||||
#define LOCAL_COUNT_ADDRESS WLAN_LOCAL_COUNT_ADDRESS
|
||||
#define LOCAL_COUNT_OFFSET WLAN_LOCAL_COUNT_OFFSET
|
||||
#define LOCAL_COUNT_VALUE_MSB WLAN_LOCAL_COUNT_VALUE_MSB
|
||||
#define LOCAL_COUNT_VALUE_LSB WLAN_LOCAL_COUNT_VALUE_LSB
|
||||
#define LOCAL_COUNT_VALUE_MASK WLAN_LOCAL_COUNT_VALUE_MASK
|
||||
#define LOCAL_COUNT_VALUE_GET(x) WLAN_LOCAL_COUNT_VALUE_GET(x)
|
||||
#define LOCAL_COUNT_VALUE_SET(x) WLAN_LOCAL_COUNT_VALUE_SET(x)
|
||||
#define COUNT_INC_ADDRESS WLAN_COUNT_INC_ADDRESS
|
||||
#define COUNT_INC_OFFSET WLAN_COUNT_INC_OFFSET
|
||||
#define COUNT_INC_VALUE_MSB WLAN_COUNT_INC_VALUE_MSB
|
||||
#define COUNT_INC_VALUE_LSB WLAN_COUNT_INC_VALUE_LSB
|
||||
#define COUNT_INC_VALUE_MASK WLAN_COUNT_INC_VALUE_MASK
|
||||
#define COUNT_INC_VALUE_GET(x) WLAN_COUNT_INC_VALUE_GET(x)
|
||||
#define COUNT_INC_VALUE_SET(x) WLAN_COUNT_INC_VALUE_SET(x)
|
||||
#define LOCAL_SCRATCH_ADDRESS WLAN_LOCAL_SCRATCH_ADDRESS
|
||||
#define LOCAL_SCRATCH_OFFSET WLAN_LOCAL_SCRATCH_OFFSET
|
||||
#define LOCAL_SCRATCH_VALUE_MSB WLAN_LOCAL_SCRATCH_VALUE_MSB
|
||||
#define LOCAL_SCRATCH_VALUE_LSB WLAN_LOCAL_SCRATCH_VALUE_LSB
|
||||
#define LOCAL_SCRATCH_VALUE_MASK WLAN_LOCAL_SCRATCH_VALUE_MASK
|
||||
#define LOCAL_SCRATCH_VALUE_GET(x) WLAN_LOCAL_SCRATCH_VALUE_GET(x)
|
||||
#define LOCAL_SCRATCH_VALUE_SET(x) WLAN_LOCAL_SCRATCH_VALUE_SET(x)
|
||||
#define USE_LOCAL_BUS_ADDRESS WLAN_USE_LOCAL_BUS_ADDRESS
|
||||
#define USE_LOCAL_BUS_OFFSET WLAN_USE_LOCAL_BUS_OFFSET
|
||||
#define USE_LOCAL_BUS_PIN_INIT_MSB WLAN_USE_LOCAL_BUS_PIN_INIT_MSB
|
||||
#define USE_LOCAL_BUS_PIN_INIT_LSB WLAN_USE_LOCAL_BUS_PIN_INIT_LSB
|
||||
#define USE_LOCAL_BUS_PIN_INIT_MASK WLAN_USE_LOCAL_BUS_PIN_INIT_MASK
|
||||
#define USE_LOCAL_BUS_PIN_INIT_GET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x)
|
||||
#define USE_LOCAL_BUS_PIN_INIT_SET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x)
|
||||
#define SDIO_CONFIG_ADDRESS WLAN_SDIO_CONFIG_ADDRESS
|
||||
#define SDIO_CONFIG_OFFSET WLAN_SDIO_CONFIG_OFFSET
|
||||
#define SDIO_CONFIG_CCCR_IOR1_MSB WLAN_SDIO_CONFIG_CCCR_IOR1_MSB
|
||||
#define SDIO_CONFIG_CCCR_IOR1_LSB WLAN_SDIO_CONFIG_CCCR_IOR1_LSB
|
||||
#define SDIO_CONFIG_CCCR_IOR1_MASK WLAN_SDIO_CONFIG_CCCR_IOR1_MASK
|
||||
#define SDIO_CONFIG_CCCR_IOR1_GET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x)
|
||||
#define SDIO_CONFIG_CCCR_IOR1_SET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x)
|
||||
#define MBOX_DEBUG_ADDRESS WLAN_MBOX_DEBUG_ADDRESS
|
||||
#define MBOX_DEBUG_OFFSET WLAN_MBOX_DEBUG_OFFSET
|
||||
#define MBOX_DEBUG_SEL_MSB WLAN_MBOX_DEBUG_SEL_MSB
|
||||
#define MBOX_DEBUG_SEL_LSB WLAN_MBOX_DEBUG_SEL_LSB
|
||||
#define MBOX_DEBUG_SEL_MASK WLAN_MBOX_DEBUG_SEL_MASK
|
||||
#define MBOX_DEBUG_SEL_GET(x) WLAN_MBOX_DEBUG_SEL_GET(x)
|
||||
#define MBOX_DEBUG_SEL_SET(x) WLAN_MBOX_DEBUG_SEL_SET(x)
|
||||
#define MBOX_FIFO_RESET_ADDRESS WLAN_MBOX_FIFO_RESET_ADDRESS
|
||||
#define MBOX_FIFO_RESET_OFFSET WLAN_MBOX_FIFO_RESET_OFFSET
|
||||
#define MBOX_FIFO_RESET_INIT_MSB WLAN_MBOX_FIFO_RESET_INIT_MSB
|
||||
#define MBOX_FIFO_RESET_INIT_LSB WLAN_MBOX_FIFO_RESET_INIT_LSB
|
||||
#define MBOX_FIFO_RESET_INIT_MASK WLAN_MBOX_FIFO_RESET_INIT_MASK
|
||||
#define MBOX_FIFO_RESET_INIT_GET(x) WLAN_MBOX_FIFO_RESET_INIT_GET(x)
|
||||
#define MBOX_FIFO_RESET_INIT_SET(x) WLAN_MBOX_FIFO_RESET_INIT_SET(x)
|
||||
#define MBOX_TXFIFO_POP_ADDRESS WLAN_MBOX_TXFIFO_POP_ADDRESS
|
||||
#define MBOX_TXFIFO_POP_OFFSET WLAN_MBOX_TXFIFO_POP_OFFSET
|
||||
#define MBOX_TXFIFO_POP_DATA_MSB WLAN_MBOX_TXFIFO_POP_DATA_MSB
|
||||
#define MBOX_TXFIFO_POP_DATA_LSB WLAN_MBOX_TXFIFO_POP_DATA_LSB
|
||||
#define MBOX_TXFIFO_POP_DATA_MASK WLAN_MBOX_TXFIFO_POP_DATA_MASK
|
||||
#define MBOX_TXFIFO_POP_DATA_GET(x) WLAN_MBOX_TXFIFO_POP_DATA_GET(x)
|
||||
#define MBOX_TXFIFO_POP_DATA_SET(x) WLAN_MBOX_TXFIFO_POP_DATA_SET(x)
|
||||
#define MBOX_RXFIFO_POP_ADDRESS WLAN_MBOX_RXFIFO_POP_ADDRESS
|
||||
#define MBOX_RXFIFO_POP_OFFSET WLAN_MBOX_RXFIFO_POP_OFFSET
|
||||
#define MBOX_RXFIFO_POP_DATA_MSB WLAN_MBOX_RXFIFO_POP_DATA_MSB
|
||||
#define MBOX_RXFIFO_POP_DATA_LSB WLAN_MBOX_RXFIFO_POP_DATA_LSB
|
||||
#define MBOX_RXFIFO_POP_DATA_MASK WLAN_MBOX_RXFIFO_POP_DATA_MASK
|
||||
#define MBOX_RXFIFO_POP_DATA_GET(x) WLAN_MBOX_RXFIFO_POP_DATA_GET(x)
|
||||
#define MBOX_RXFIFO_POP_DATA_SET(x) WLAN_MBOX_RXFIFO_POP_DATA_SET(x)
|
||||
#define SDIO_DEBUG_ADDRESS WLAN_SDIO_DEBUG_ADDRESS
|
||||
#define SDIO_DEBUG_OFFSET WLAN_SDIO_DEBUG_OFFSET
|
||||
#define SDIO_DEBUG_SEL_MSB WLAN_SDIO_DEBUG_SEL_MSB
|
||||
#define SDIO_DEBUG_SEL_LSB WLAN_SDIO_DEBUG_SEL_LSB
|
||||
#define SDIO_DEBUG_SEL_MASK WLAN_SDIO_DEBUG_SEL_MASK
|
||||
#define SDIO_DEBUG_SEL_GET(x) WLAN_SDIO_DEBUG_SEL_GET(x)
|
||||
#define SDIO_DEBUG_SEL_SET(x) WLAN_SDIO_DEBUG_SEL_SET(x)
|
||||
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS
|
||||
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET
|
||||
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
|
||||
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
|
||||
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
|
||||
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
|
||||
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
|
||||
#define GMBOX0_DMA_RX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS
|
||||
#define GMBOX0_DMA_RX_CONTROL_OFFSET WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET
|
||||
#define GMBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB
|
||||
#define GMBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB
|
||||
#define GMBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK
|
||||
#define GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x)
|
||||
#define GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x)
|
||||
#define GMBOX0_DMA_RX_CONTROL_START_MSB WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB
|
||||
#define GMBOX0_DMA_RX_CONTROL_START_LSB WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB
|
||||
#define GMBOX0_DMA_RX_CONTROL_START_MASK WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK
|
||||
#define GMBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x)
|
||||
#define GMBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x)
|
||||
#define GMBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB
|
||||
#define GMBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB
|
||||
#define GMBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK
|
||||
#define GMBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x)
|
||||
#define GMBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x)
|
||||
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS
|
||||
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET
|
||||
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
|
||||
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
|
||||
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
|
||||
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
|
||||
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
|
||||
#define GMBOX0_DMA_TX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS
|
||||
#define GMBOX0_DMA_TX_CONTROL_OFFSET WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET
|
||||
#define GMBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB
|
||||
#define GMBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB
|
||||
#define GMBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK
|
||||
#define GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x)
|
||||
#define GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x)
|
||||
#define GMBOX0_DMA_TX_CONTROL_START_MSB WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB
|
||||
#define GMBOX0_DMA_TX_CONTROL_START_LSB WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB
|
||||
#define GMBOX0_DMA_TX_CONTROL_START_MASK WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK
|
||||
#define GMBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x)
|
||||
#define GMBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x)
|
||||
#define GMBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB
|
||||
#define GMBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB
|
||||
#define GMBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK
|
||||
#define GMBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x)
|
||||
#define GMBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x)
|
||||
#define GMBOX_INT_STATUS_ADDRESS WLAN_GMBOX_INT_STATUS_ADDRESS
|
||||
#define GMBOX_INT_STATUS_OFFSET WLAN_GMBOX_INT_STATUS_OFFSET
|
||||
#define GMBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB
|
||||
#define GMBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB
|
||||
#define GMBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK
|
||||
#define GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x)
|
||||
#define GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x)
|
||||
#define GMBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB
|
||||
#define GMBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB
|
||||
#define GMBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK
|
||||
#define GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x)
|
||||
#define GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x)
|
||||
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB
|
||||
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB
|
||||
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK
|
||||
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)
|
||||
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)
|
||||
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB
|
||||
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB
|
||||
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK
|
||||
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x)
|
||||
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x)
|
||||
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB
|
||||
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB
|
||||
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK
|
||||
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)
|
||||
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)
|
||||
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB
|
||||
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB
|
||||
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK
|
||||
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)
|
||||
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)
|
||||
#define GMBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB
|
||||
#define GMBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB
|
||||
#define GMBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK
|
||||
#define GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x)
|
||||
#define GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x)
|
||||
#define GMBOX_INT_ENABLE_ADDRESS WLAN_GMBOX_INT_ENABLE_ADDRESS
|
||||
#define GMBOX_INT_ENABLE_OFFSET WLAN_GMBOX_INT_ENABLE_OFFSET
|
||||
#define GMBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB
|
||||
#define GMBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB
|
||||
#define GMBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK
|
||||
#define GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x)
|
||||
#define GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x)
|
||||
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB
|
||||
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB
|
||||
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK
|
||||
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)
|
||||
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)
|
||||
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB
|
||||
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB
|
||||
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK
|
||||
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)
|
||||
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)
|
||||
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB
|
||||
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB
|
||||
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK
|
||||
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x)
|
||||
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x)
|
||||
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB
|
||||
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB
|
||||
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK
|
||||
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)
|
||||
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)
|
||||
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB
|
||||
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB
|
||||
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK
|
||||
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)
|
||||
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)
|
||||
#define GMBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB
|
||||
#define GMBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB
|
||||
#define GMBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK
|
||||
#define GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x)
|
||||
#define GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x)
|
||||
#define HOST_IF_WINDOW_ADDRESS WLAN_HOST_IF_WINDOW_ADDRESS
|
||||
#define HOST_IF_WINDOW_OFFSET WLAN_HOST_IF_WINDOW_OFFSET
|
||||
#define HOST_IF_WINDOW_DATA_MSB WLAN_HOST_IF_WINDOW_DATA_MSB
|
||||
#define HOST_IF_WINDOW_DATA_LSB WLAN_HOST_IF_WINDOW_DATA_LSB
|
||||
#define HOST_IF_WINDOW_DATA_MASK WLAN_HOST_IF_WINDOW_DATA_MASK
|
||||
#define HOST_IF_WINDOW_DATA_GET(x) WLAN_HOST_IF_WINDOW_DATA_GET(x)
|
||||
#define HOST_IF_WINDOW_DATA_SET(x) WLAN_HOST_IF_WINDOW_DATA_SET(x)
|
||||
|
||||
#endif
|
|
@ -1,471 +0,0 @@
|
|||
// ------------------------------------------------------------------
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
// ------------------------------------------------------------------
|
||||
//===================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//===================================================================
|
||||
|
||||
|
||||
#ifndef _MBOX_WLAN_HOST_REG_REG_H_
|
||||
#define _MBOX_WLAN_HOST_REG_REG_H_
|
||||
|
||||
#define HOST_INT_STATUS_ADDRESS 0x00000400
|
||||
#define HOST_INT_STATUS_OFFSET 0x00000400
|
||||
#define HOST_INT_STATUS_ERROR_MSB 7
|
||||
#define HOST_INT_STATUS_ERROR_LSB 7
|
||||
#define HOST_INT_STATUS_ERROR_MASK 0x00000080
|
||||
#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
|
||||
#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
|
||||
#define HOST_INT_STATUS_CPU_MSB 6
|
||||
#define HOST_INT_STATUS_CPU_LSB 6
|
||||
#define HOST_INT_STATUS_CPU_MASK 0x00000040
|
||||
#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
|
||||
#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
|
||||
#define HOST_INT_STATUS_INT_MSB 5
|
||||
#define HOST_INT_STATUS_INT_LSB 5
|
||||
#define HOST_INT_STATUS_INT_MASK 0x00000020
|
||||
#define HOST_INT_STATUS_INT_GET(x) (((x) & HOST_INT_STATUS_INT_MASK) >> HOST_INT_STATUS_INT_LSB)
|
||||
#define HOST_INT_STATUS_INT_SET(x) (((x) << HOST_INT_STATUS_INT_LSB) & HOST_INT_STATUS_INT_MASK)
|
||||
#define HOST_INT_STATUS_COUNTER_MSB 4
|
||||
#define HOST_INT_STATUS_COUNTER_LSB 4
|
||||
#define HOST_INT_STATUS_COUNTER_MASK 0x00000010
|
||||
#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
|
||||
#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
|
||||
#define HOST_INT_STATUS_MBOX_DATA_MSB 3
|
||||
#define HOST_INT_STATUS_MBOX_DATA_LSB 0
|
||||
#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f
|
||||
#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
|
||||
#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
|
||||
|
||||
#define CPU_INT_STATUS_ADDRESS 0x00000401
|
||||
#define CPU_INT_STATUS_OFFSET 0x00000401
|
||||
#define CPU_INT_STATUS_BIT_MSB 7
|
||||
#define CPU_INT_STATUS_BIT_LSB 0
|
||||
#define CPU_INT_STATUS_BIT_MASK 0x000000ff
|
||||
#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
|
||||
#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
|
||||
|
||||
#define ERROR_INT_STATUS_ADDRESS 0x00000402
|
||||
#define ERROR_INT_STATUS_OFFSET 0x00000402
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB)
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK)
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MSB 5
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB 5
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB)
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK)
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MSB 4
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB 4
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB)
|
||||
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK)
|
||||
#define ERROR_INT_STATUS_SPI_MSB 3
|
||||
#define ERROR_INT_STATUS_SPI_LSB 3
|
||||
#define ERROR_INT_STATUS_SPI_MASK 0x00000008
|
||||
#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
|
||||
#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
|
||||
#define ERROR_INT_STATUS_WAKEUP_MSB 2
|
||||
#define ERROR_INT_STATUS_WAKEUP_LSB 2
|
||||
#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
|
||||
#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
|
||||
#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
|
||||
#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
|
||||
#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
|
||||
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
|
||||
#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
|
||||
#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
|
||||
#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
|
||||
#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
|
||||
#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
|
||||
#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
|
||||
#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
|
||||
|
||||
#define COUNTER_INT_STATUS_ADDRESS 0x00000403
|
||||
#define COUNTER_INT_STATUS_OFFSET 0x00000403
|
||||
#define COUNTER_INT_STATUS_COUNTER_MSB 7
|
||||
#define COUNTER_INT_STATUS_COUNTER_LSB 0
|
||||
#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
|
||||
#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
|
||||
#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
|
||||
|
||||
#define MBOX_FRAME_ADDRESS 0x00000404
|
||||
#define MBOX_FRAME_OFFSET 0x00000404
|
||||
#define MBOX_FRAME_RX_EOM_MSB 7
|
||||
#define MBOX_FRAME_RX_EOM_LSB 4
|
||||
#define MBOX_FRAME_RX_EOM_MASK 0x000000f0
|
||||
#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
|
||||
#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
|
||||
#define MBOX_FRAME_RX_SOM_MSB 3
|
||||
#define MBOX_FRAME_RX_SOM_LSB 0
|
||||
#define MBOX_FRAME_RX_SOM_MASK 0x0000000f
|
||||
#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
|
||||
#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
|
||||
|
||||
#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
|
||||
#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405
|
||||
#define RX_LOOKAHEAD_VALID_MBOX_MSB 3
|
||||
#define RX_LOOKAHEAD_VALID_MBOX_LSB 0
|
||||
#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f
|
||||
#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
|
||||
#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
|
||||
|
||||
#define HOST_INT_STATUS2_ADDRESS 0x00000406
|
||||
#define HOST_INT_STATUS2_OFFSET 0x00000406
|
||||
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MSB 2
|
||||
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB 2
|
||||
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK 0x00000004
|
||||
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB)
|
||||
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK)
|
||||
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MSB 1
|
||||
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB 1
|
||||
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK 0x00000002
|
||||
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB)
|
||||
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK)
|
||||
#define HOST_INT_STATUS2_GMBOX_DATA_MSB 0
|
||||
#define HOST_INT_STATUS2_GMBOX_DATA_LSB 0
|
||||
#define HOST_INT_STATUS2_GMBOX_DATA_MASK 0x00000001
|
||||
#define HOST_INT_STATUS2_GMBOX_DATA_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_DATA_MASK) >> HOST_INT_STATUS2_GMBOX_DATA_LSB)
|
||||
#define HOST_INT_STATUS2_GMBOX_DATA_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_DATA_LSB) & HOST_INT_STATUS2_GMBOX_DATA_MASK)
|
||||
|
||||
#define GMBOX_RX_AVAIL_ADDRESS 0x00000407
|
||||
#define GMBOX_RX_AVAIL_OFFSET 0x00000407
|
||||
#define GMBOX_RX_AVAIL_BYTE_MSB 6
|
||||
#define GMBOX_RX_AVAIL_BYTE_LSB 0
|
||||
#define GMBOX_RX_AVAIL_BYTE_MASK 0x0000007f
|
||||
#define GMBOX_RX_AVAIL_BYTE_GET(x) (((x) & GMBOX_RX_AVAIL_BYTE_MASK) >> GMBOX_RX_AVAIL_BYTE_LSB)
|
||||
#define GMBOX_RX_AVAIL_BYTE_SET(x) (((x) << GMBOX_RX_AVAIL_BYTE_LSB) & GMBOX_RX_AVAIL_BYTE_MASK)
|
||||
|
||||
#define RX_LOOKAHEAD0_ADDRESS 0x00000408
|
||||
#define RX_LOOKAHEAD0_OFFSET 0x00000408
|
||||
#define RX_LOOKAHEAD0_DATA_MSB 7
|
||||
#define RX_LOOKAHEAD0_DATA_LSB 0
|
||||
#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff
|
||||
#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
|
||||
#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
|
||||
|
||||
#define RX_LOOKAHEAD1_ADDRESS 0x0000040c
|
||||
#define RX_LOOKAHEAD1_OFFSET 0x0000040c
|
||||
#define RX_LOOKAHEAD1_DATA_MSB 7
|
||||
#define RX_LOOKAHEAD1_DATA_LSB 0
|
||||
#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff
|
||||
#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
|
||||
#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
|
||||
|
||||
#define RX_LOOKAHEAD2_ADDRESS 0x00000410
|
||||
#define RX_LOOKAHEAD2_OFFSET 0x00000410
|
||||
#define RX_LOOKAHEAD2_DATA_MSB 7
|
||||
#define RX_LOOKAHEAD2_DATA_LSB 0
|
||||
#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff
|
||||
#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
|
||||
#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
|
||||
|
||||
#define RX_LOOKAHEAD3_ADDRESS 0x00000414
|
||||
#define RX_LOOKAHEAD3_OFFSET 0x00000414
|
||||
#define RX_LOOKAHEAD3_DATA_MSB 7
|
||||
#define RX_LOOKAHEAD3_DATA_LSB 0
|
||||
#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff
|
||||
#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
|
||||
#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
|
||||
|
||||
#define INT_STATUS_ENABLE_ADDRESS 0x00000418
|
||||
#define INT_STATUS_ENABLE_OFFSET 0x00000418
|
||||
#define INT_STATUS_ENABLE_ERROR_MSB 7
|
||||
#define INT_STATUS_ENABLE_ERROR_LSB 7
|
||||
#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
|
||||
#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
|
||||
#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
|
||||
#define INT_STATUS_ENABLE_CPU_MSB 6
|
||||
#define INT_STATUS_ENABLE_CPU_LSB 6
|
||||
#define INT_STATUS_ENABLE_CPU_MASK 0x00000040
|
||||
#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
|
||||
#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
|
||||
#define INT_STATUS_ENABLE_INT_MSB 5
|
||||
#define INT_STATUS_ENABLE_INT_LSB 5
|
||||
#define INT_STATUS_ENABLE_INT_MASK 0x00000020
|
||||
#define INT_STATUS_ENABLE_INT_GET(x) (((x) & INT_STATUS_ENABLE_INT_MASK) >> INT_STATUS_ENABLE_INT_LSB)
|
||||
#define INT_STATUS_ENABLE_INT_SET(x) (((x) << INT_STATUS_ENABLE_INT_LSB) & INT_STATUS_ENABLE_INT_MASK)
|
||||
#define INT_STATUS_ENABLE_COUNTER_MSB 4
|
||||
#define INT_STATUS_ENABLE_COUNTER_LSB 4
|
||||
#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
|
||||
#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
|
||||
#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
|
||||
#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
|
||||
#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
|
||||
#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
|
||||
#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
|
||||
#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
|
||||
|
||||
#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
|
||||
#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419
|
||||
#define CPU_INT_STATUS_ENABLE_BIT_MSB 7
|
||||
#define CPU_INT_STATUS_ENABLE_BIT_LSB 0
|
||||
#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
|
||||
#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
|
||||
#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
|
||||
|
||||
#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
|
||||
#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB)
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK)
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MSB 5
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB 5
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB)
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK)
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MSB 4
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB 4
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB)
|
||||
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK)
|
||||
#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2
|
||||
#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2
|
||||
#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004
|
||||
#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
|
||||
#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
|
||||
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
|
||||
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
|
||||
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
|
||||
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
|
||||
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
|
||||
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
|
||||
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
|
||||
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
|
||||
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
|
||||
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
|
||||
|
||||
#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
|
||||
#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b
|
||||
#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
|
||||
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
|
||||
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
|
||||
#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
|
||||
#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
|
||||
|
||||
#define COUNT_ADDRESS 0x00000420
|
||||
#define COUNT_OFFSET 0x00000420
|
||||
#define COUNT_VALUE_MSB 7
|
||||
#define COUNT_VALUE_LSB 0
|
||||
#define COUNT_VALUE_MASK 0x000000ff
|
||||
#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
|
||||
#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
|
||||
|
||||
#define COUNT_DEC_ADDRESS 0x00000440
|
||||
#define COUNT_DEC_OFFSET 0x00000440
|
||||
#define COUNT_DEC_VALUE_MSB 7
|
||||
#define COUNT_DEC_VALUE_LSB 0
|
||||
#define COUNT_DEC_VALUE_MASK 0x000000ff
|
||||
#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
|
||||
#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
|
||||
|
||||
#define SCRATCH_ADDRESS 0x00000460
|
||||
#define SCRATCH_OFFSET 0x00000460
|
||||
#define SCRATCH_VALUE_MSB 7
|
||||
#define SCRATCH_VALUE_LSB 0
|
||||
#define SCRATCH_VALUE_MASK 0x000000ff
|
||||
#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
|
||||
#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
|
||||
|
||||
#define FIFO_TIMEOUT_ADDRESS 0x00000468
|
||||
#define FIFO_TIMEOUT_OFFSET 0x00000468
|
||||
#define FIFO_TIMEOUT_VALUE_MSB 7
|
||||
#define FIFO_TIMEOUT_VALUE_LSB 0
|
||||
#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff
|
||||
#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
|
||||
#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
|
||||
|
||||
#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469
|
||||
#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469
|
||||
#define FIFO_TIMEOUT_ENABLE_SET_MSB 0
|
||||
#define FIFO_TIMEOUT_ENABLE_SET_LSB 0
|
||||
#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001
|
||||
#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
|
||||
#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
|
||||
|
||||
#define DISABLE_SLEEP_ADDRESS 0x0000046a
|
||||
#define DISABLE_SLEEP_OFFSET 0x0000046a
|
||||
#define DISABLE_SLEEP_FOR_INT_MSB 1
|
||||
#define DISABLE_SLEEP_FOR_INT_LSB 1
|
||||
#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002
|
||||
#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
|
||||
#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
|
||||
#define DISABLE_SLEEP_ON_MSB 0
|
||||
#define DISABLE_SLEEP_ON_LSB 0
|
||||
#define DISABLE_SLEEP_ON_MASK 0x00000001
|
||||
#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
|
||||
#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
|
||||
|
||||
#define LOCAL_BUS_ADDRESS 0x00000470
|
||||
#define LOCAL_BUS_OFFSET 0x00000470
|
||||
#define LOCAL_BUS_STATE_MSB 1
|
||||
#define LOCAL_BUS_STATE_LSB 0
|
||||
#define LOCAL_BUS_STATE_MASK 0x00000003
|
||||
#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
|
||||
#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
|
||||
|
||||
#define INT_WLAN_ADDRESS 0x00000472
|
||||
#define INT_WLAN_OFFSET 0x00000472
|
||||
#define INT_WLAN_VECTOR_MSB 7
|
||||
#define INT_WLAN_VECTOR_LSB 0
|
||||
#define INT_WLAN_VECTOR_MASK 0x000000ff
|
||||
#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
|
||||
#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
|
||||
|
||||
#define WINDOW_DATA_ADDRESS 0x00000474
|
||||
#define WINDOW_DATA_OFFSET 0x00000474
|
||||
#define WINDOW_DATA_DATA_MSB 7
|
||||
#define WINDOW_DATA_DATA_LSB 0
|
||||
#define WINDOW_DATA_DATA_MASK 0x000000ff
|
||||
#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
|
||||
#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
|
||||
|
||||
#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
|
||||
#define WINDOW_WRITE_ADDR_OFFSET 0x00000478
|
||||
#define WINDOW_WRITE_ADDR_ADDR_MSB 7
|
||||
#define WINDOW_WRITE_ADDR_ADDR_LSB 0
|
||||
#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff
|
||||
#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
|
||||
#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
|
||||
|
||||
#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
|
||||
#define WINDOW_READ_ADDR_OFFSET 0x0000047c
|
||||
#define WINDOW_READ_ADDR_ADDR_MSB 7
|
||||
#define WINDOW_READ_ADDR_ADDR_LSB 0
|
||||
#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff
|
||||
#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
|
||||
#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
|
||||
|
||||
#define HOST_CTRL_SPI_CONFIG_ADDRESS 0x00000480
|
||||
#define HOST_CTRL_SPI_CONFIG_OFFSET 0x00000480
|
||||
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MSB 4
|
||||
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB 4
|
||||
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK 0x00000010
|
||||
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) >> HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB)
|
||||
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK)
|
||||
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
|
||||
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
|
||||
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
|
||||
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB)
|
||||
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK)
|
||||
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MSB 2
|
||||
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB 2
|
||||
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK 0x00000004
|
||||
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) >> HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB)
|
||||
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK)
|
||||
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MSB 1
|
||||
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB 0
|
||||
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK 0x00000003
|
||||
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) >> HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB)
|
||||
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK)
|
||||
|
||||
#define HOST_CTRL_SPI_STATUS_ADDRESS 0x00000481
|
||||
#define HOST_CTRL_SPI_STATUS_OFFSET 0x00000481
|
||||
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MSB 3
|
||||
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB 3
|
||||
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK 0x00000008
|
||||
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB)
|
||||
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK)
|
||||
#define HOST_CTRL_SPI_STATUS_RD_ERR_MSB 2
|
||||
#define HOST_CTRL_SPI_STATUS_RD_ERR_LSB 2
|
||||
#define HOST_CTRL_SPI_STATUS_RD_ERR_MASK 0x00000004
|
||||
#define HOST_CTRL_SPI_STATUS_RD_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) >> HOST_CTRL_SPI_STATUS_RD_ERR_LSB)
|
||||
#define HOST_CTRL_SPI_STATUS_RD_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_RD_ERR_LSB) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK)
|
||||
#define HOST_CTRL_SPI_STATUS_WR_ERR_MSB 1
|
||||
#define HOST_CTRL_SPI_STATUS_WR_ERR_LSB 1
|
||||
#define HOST_CTRL_SPI_STATUS_WR_ERR_MASK 0x00000002
|
||||
#define HOST_CTRL_SPI_STATUS_WR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_WR_ERR_LSB)
|
||||
#define HOST_CTRL_SPI_STATUS_WR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_WR_ERR_LSB) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK)
|
||||
#define HOST_CTRL_SPI_STATUS_READY_MSB 0
|
||||
#define HOST_CTRL_SPI_STATUS_READY_LSB 0
|
||||
#define HOST_CTRL_SPI_STATUS_READY_MASK 0x00000001
|
||||
#define HOST_CTRL_SPI_STATUS_READY_GET(x) (((x) & HOST_CTRL_SPI_STATUS_READY_MASK) >> HOST_CTRL_SPI_STATUS_READY_LSB)
|
||||
#define HOST_CTRL_SPI_STATUS_READY_SET(x) (((x) << HOST_CTRL_SPI_STATUS_READY_LSB) & HOST_CTRL_SPI_STATUS_READY_MASK)
|
||||
|
||||
#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482
|
||||
#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482
|
||||
#define NON_ASSOC_SLEEP_EN_BIT_MSB 0
|
||||
#define NON_ASSOC_SLEEP_EN_BIT_LSB 0
|
||||
#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001
|
||||
#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
|
||||
#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
|
||||
|
||||
#define CPU_DBG_SEL_ADDRESS 0x00000483
|
||||
#define CPU_DBG_SEL_OFFSET 0x00000483
|
||||
#define CPU_DBG_SEL_BIT_MSB 5
|
||||
#define CPU_DBG_SEL_BIT_LSB 0
|
||||
#define CPU_DBG_SEL_BIT_MASK 0x0000003f
|
||||
#define CPU_DBG_SEL_BIT_GET(x) (((x) & CPU_DBG_SEL_BIT_MASK) >> CPU_DBG_SEL_BIT_LSB)
|
||||
#define CPU_DBG_SEL_BIT_SET(x) (((x) << CPU_DBG_SEL_BIT_LSB) & CPU_DBG_SEL_BIT_MASK)
|
||||
|
||||
#define CPU_DBG_ADDRESS 0x00000484
|
||||
#define CPU_DBG_OFFSET 0x00000484
|
||||
#define CPU_DBG_DATA_MSB 7
|
||||
#define CPU_DBG_DATA_LSB 0
|
||||
#define CPU_DBG_DATA_MASK 0x000000ff
|
||||
#define CPU_DBG_DATA_GET(x) (((x) & CPU_DBG_DATA_MASK) >> CPU_DBG_DATA_LSB)
|
||||
#define CPU_DBG_DATA_SET(x) (((x) << CPU_DBG_DATA_LSB) & CPU_DBG_DATA_MASK)
|
||||
|
||||
#define INT_STATUS2_ENABLE_ADDRESS 0x00000488
|
||||
#define INT_STATUS2_ENABLE_OFFSET 0x00000488
|
||||
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MSB 2
|
||||
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB 2
|
||||
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK 0x00000004
|
||||
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB)
|
||||
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK)
|
||||
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MSB 1
|
||||
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB 1
|
||||
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK 0x00000002
|
||||
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB)
|
||||
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK)
|
||||
#define INT_STATUS2_ENABLE_GMBOX_DATA_MSB 0
|
||||
#define INT_STATUS2_ENABLE_GMBOX_DATA_LSB 0
|
||||
#define INT_STATUS2_ENABLE_GMBOX_DATA_MASK 0x00000001
|
||||
#define INT_STATUS2_ENABLE_GMBOX_DATA_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) >> INT_STATUS2_ENABLE_GMBOX_DATA_LSB)
|
||||
#define INT_STATUS2_ENABLE_GMBOX_DATA_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_DATA_LSB) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK)
|
||||
|
||||
#define GMBOX_RX_LOOKAHEAD_ADDRESS 0x00000490
|
||||
#define GMBOX_RX_LOOKAHEAD_OFFSET 0x00000490
|
||||
#define GMBOX_RX_LOOKAHEAD_DATA_MSB 7
|
||||
#define GMBOX_RX_LOOKAHEAD_DATA_LSB 0
|
||||
#define GMBOX_RX_LOOKAHEAD_DATA_MASK 0x000000ff
|
||||
#define GMBOX_RX_LOOKAHEAD_DATA_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_DATA_MASK) >> GMBOX_RX_LOOKAHEAD_DATA_LSB)
|
||||
#define GMBOX_RX_LOOKAHEAD_DATA_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_DATA_LSB) & GMBOX_RX_LOOKAHEAD_DATA_MASK)
|
||||
|
||||
#define GMBOX_RX_LOOKAHEAD_MUX_ADDRESS 0x00000498
|
||||
#define GMBOX_RX_LOOKAHEAD_MUX_OFFSET 0x00000498
|
||||
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MSB 0
|
||||
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB 0
|
||||
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK 0x00000001
|
||||
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) >> GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB)
|
||||
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK)
|
||||
|
||||
#define CIS_WINDOW_ADDRESS 0x00000600
|
||||
#define CIS_WINDOW_OFFSET 0x00000600
|
||||
#define CIS_WINDOW_DATA_MSB 7
|
||||
#define CIS_WINDOW_DATA_LSB 0
|
||||
#define CIS_WINDOW_DATA_MASK 0x000000ff
|
||||
#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
|
||||
#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
|
||||
|
||||
|
||||
#endif /* _MBOX_WLAN_HOST_REG_H_ */
|
|
@ -1,589 +0,0 @@
|
|||
// ------------------------------------------------------------------
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
// ------------------------------------------------------------------
|
||||
//===================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//===================================================================
|
||||
|
||||
|
||||
#ifndef _MBOX_WLAN_REG_REG_H_
|
||||
#define _MBOX_WLAN_REG_REG_H_
|
||||
|
||||
#define WLAN_MBOX_FIFO_ADDRESS 0x00000000
|
||||
#define WLAN_MBOX_FIFO_OFFSET 0x00000000
|
||||
#define WLAN_MBOX_FIFO_DATA_MSB 19
|
||||
#define WLAN_MBOX_FIFO_DATA_LSB 0
|
||||
#define WLAN_MBOX_FIFO_DATA_MASK 0x000fffff
|
||||
#define WLAN_MBOX_FIFO_DATA_GET(x) (((x) & WLAN_MBOX_FIFO_DATA_MASK) >> WLAN_MBOX_FIFO_DATA_LSB)
|
||||
#define WLAN_MBOX_FIFO_DATA_SET(x) (((x) << WLAN_MBOX_FIFO_DATA_LSB) & WLAN_MBOX_FIFO_DATA_MASK)
|
||||
|
||||
#define WLAN_MBOX_FIFO_STATUS_ADDRESS 0x00000010
|
||||
#define WLAN_MBOX_FIFO_STATUS_OFFSET 0x00000010
|
||||
#define WLAN_MBOX_FIFO_STATUS_EMPTY_MSB 19
|
||||
#define WLAN_MBOX_FIFO_STATUS_EMPTY_LSB 16
|
||||
#define WLAN_MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000
|
||||
#define WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) >> WLAN_MBOX_FIFO_STATUS_EMPTY_LSB)
|
||||
#define WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK)
|
||||
#define WLAN_MBOX_FIFO_STATUS_FULL_MSB 15
|
||||
#define WLAN_MBOX_FIFO_STATUS_FULL_LSB 12
|
||||
#define WLAN_MBOX_FIFO_STATUS_FULL_MASK 0x0000f000
|
||||
#define WLAN_MBOX_FIFO_STATUS_FULL_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) >> WLAN_MBOX_FIFO_STATUS_FULL_LSB)
|
||||
#define WLAN_MBOX_FIFO_STATUS_FULL_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_FULL_LSB) & WLAN_MBOX_FIFO_STATUS_FULL_MASK)
|
||||
|
||||
#define WLAN_MBOX_DMA_POLICY_ADDRESS 0x00000014
|
||||
#define WLAN_MBOX_DMA_POLICY_OFFSET 0x00000014
|
||||
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB 3
|
||||
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB 3
|
||||
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
|
||||
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB)
|
||||
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK)
|
||||
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB 2
|
||||
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB 2
|
||||
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
|
||||
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB)
|
||||
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK)
|
||||
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB 1
|
||||
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB 1
|
||||
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
|
||||
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB)
|
||||
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK)
|
||||
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB 0
|
||||
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB 0
|
||||
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
|
||||
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB)
|
||||
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK)
|
||||
|
||||
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018
|
||||
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018
|
||||
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
|
||||
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
|
||||
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
|
||||
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
|
||||
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
|
||||
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB 2
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB 2
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB)
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK)
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_START_MSB 1
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_START_LSB 1
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_START_LSB)
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK)
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB 0
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB 0
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB)
|
||||
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK)
|
||||
|
||||
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020
|
||||
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020
|
||||
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
|
||||
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
|
||||
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
|
||||
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
|
||||
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
|
||||
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB 2
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB 2
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB)
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK)
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_START_MSB 1
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_START_LSB 1
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_START_LSB)
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK)
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB 0
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB 0
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB)
|
||||
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK)
|
||||
|
||||
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028
|
||||
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028
|
||||
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
|
||||
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
|
||||
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
|
||||
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
|
||||
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
|
||||
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB 2
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB 2
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB)
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK)
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_START_MSB 1
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_START_LSB 1
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_START_LSB)
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK)
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB 0
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB 0
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB)
|
||||
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK)
|
||||
|
||||
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030
|
||||
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030
|
||||
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
|
||||
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
|
||||
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
|
||||
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
|
||||
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
|
||||
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB 2
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB 2
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB)
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK)
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_START_MSB 1
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_START_LSB 1
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_START_LSB)
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK)
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB 0
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB 0
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB)
|
||||
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK)
|
||||
|
||||
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038
|
||||
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038
|
||||
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
|
||||
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
|
||||
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
|
||||
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
|
||||
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
|
||||
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB 2
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB 2
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB)
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK)
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_START_MSB 1
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_START_LSB 1
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_START_LSB)
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK)
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB 0
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB 0
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB)
|
||||
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK)
|
||||
|
||||
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040
|
||||
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040
|
||||
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
|
||||
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
|
||||
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
|
||||
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
|
||||
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
|
||||
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB 2
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB 2
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB)
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK)
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_START_MSB 1
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_START_LSB 1
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_START_LSB)
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK)
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB 0
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB 0
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB)
|
||||
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK)
|
||||
|
||||
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048
|
||||
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048
|
||||
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
|
||||
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
|
||||
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
|
||||
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
|
||||
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
|
||||
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB 2
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB 2
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB)
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK)
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_START_MSB 1
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_START_LSB 1
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_START_LSB)
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK)
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB 0
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB 0
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB)
|
||||
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK)
|
||||
|
||||
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050
|
||||
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050
|
||||
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
|
||||
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
|
||||
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
|
||||
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
|
||||
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
|
||||
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB 2
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB 2
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB)
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK)
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_START_MSB 1
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_START_LSB 1
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_START_LSB)
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK)
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB 0
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB 0
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB)
|
||||
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK)
|
||||
|
||||
#define WLAN_MBOX_INT_STATUS_ADDRESS 0x00000058
|
||||
#define WLAN_MBOX_INT_STATUS_OFFSET 0x00000058
|
||||
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31
|
||||
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28
|
||||
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000
|
||||
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
|
||||
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
|
||||
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27
|
||||
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24
|
||||
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
|
||||
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
|
||||
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
|
||||
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23
|
||||
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20
|
||||
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000
|
||||
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
|
||||
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
|
||||
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB 17
|
||||
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB 17
|
||||
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000
|
||||
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB)
|
||||
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK)
|
||||
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16
|
||||
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16
|
||||
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000
|
||||
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
|
||||
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
|
||||
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15
|
||||
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12
|
||||
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000
|
||||
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
|
||||
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
|
||||
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB 11
|
||||
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB 8
|
||||
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00
|
||||
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB)
|
||||
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK)
|
||||
#define WLAN_MBOX_INT_STATUS_HOST_MSB 7
|
||||
#define WLAN_MBOX_INT_STATUS_HOST_LSB 0
|
||||
#define WLAN_MBOX_INT_STATUS_HOST_MASK 0x000000ff
|
||||
#define WLAN_MBOX_INT_STATUS_HOST_GET(x) (((x) & WLAN_MBOX_INT_STATUS_HOST_MASK) >> WLAN_MBOX_INT_STATUS_HOST_LSB)
|
||||
#define WLAN_MBOX_INT_STATUS_HOST_SET(x) (((x) << WLAN_MBOX_INT_STATUS_HOST_LSB) & WLAN_MBOX_INT_STATUS_HOST_MASK)
|
||||
|
||||
#define WLAN_MBOX_INT_ENABLE_ADDRESS 0x0000005c
|
||||
#define WLAN_MBOX_INT_ENABLE_OFFSET 0x0000005c
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
|
||||
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
|
||||
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
|
||||
#define WLAN_MBOX_INT_ENABLE_HOST_MSB 7
|
||||
#define WLAN_MBOX_INT_ENABLE_HOST_LSB 0
|
||||
#define WLAN_MBOX_INT_ENABLE_HOST_MASK 0x000000ff
|
||||
#define WLAN_MBOX_INT_ENABLE_HOST_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_HOST_MASK) >> WLAN_MBOX_INT_ENABLE_HOST_LSB)
|
||||
#define WLAN_MBOX_INT_ENABLE_HOST_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_HOST_LSB) & WLAN_MBOX_INT_ENABLE_HOST_MASK)
|
||||
|
||||
#define WLAN_INT_HOST_ADDRESS 0x00000060
|
||||
#define WLAN_INT_HOST_OFFSET 0x00000060
|
||||
#define WLAN_INT_HOST_VECTOR_MSB 7
|
||||
#define WLAN_INT_HOST_VECTOR_LSB 0
|
||||
#define WLAN_INT_HOST_VECTOR_MASK 0x000000ff
|
||||
#define WLAN_INT_HOST_VECTOR_GET(x) (((x) & WLAN_INT_HOST_VECTOR_MASK) >> WLAN_INT_HOST_VECTOR_LSB)
|
||||
#define WLAN_INT_HOST_VECTOR_SET(x) (((x) << WLAN_INT_HOST_VECTOR_LSB) & WLAN_INT_HOST_VECTOR_MASK)
|
||||
|
||||
#define WLAN_LOCAL_COUNT_ADDRESS 0x00000080
|
||||
#define WLAN_LOCAL_COUNT_OFFSET 0x00000080
|
||||
#define WLAN_LOCAL_COUNT_VALUE_MSB 7
|
||||
#define WLAN_LOCAL_COUNT_VALUE_LSB 0
|
||||
#define WLAN_LOCAL_COUNT_VALUE_MASK 0x000000ff
|
||||
#define WLAN_LOCAL_COUNT_VALUE_GET(x) (((x) & WLAN_LOCAL_COUNT_VALUE_MASK) >> WLAN_LOCAL_COUNT_VALUE_LSB)
|
||||
#define WLAN_LOCAL_COUNT_VALUE_SET(x) (((x) << WLAN_LOCAL_COUNT_VALUE_LSB) & WLAN_LOCAL_COUNT_VALUE_MASK)
|
||||
|
||||
#define WLAN_COUNT_INC_ADDRESS 0x000000a0
|
||||
#define WLAN_COUNT_INC_OFFSET 0x000000a0
|
||||
#define WLAN_COUNT_INC_VALUE_MSB 7
|
||||
#define WLAN_COUNT_INC_VALUE_LSB 0
|
||||
#define WLAN_COUNT_INC_VALUE_MASK 0x000000ff
|
||||
#define WLAN_COUNT_INC_VALUE_GET(x) (((x) & WLAN_COUNT_INC_VALUE_MASK) >> WLAN_COUNT_INC_VALUE_LSB)
|
||||
#define WLAN_COUNT_INC_VALUE_SET(x) (((x) << WLAN_COUNT_INC_VALUE_LSB) & WLAN_COUNT_INC_VALUE_MASK)
|
||||
|
||||
#define WLAN_LOCAL_SCRATCH_ADDRESS 0x000000c0
|
||||
#define WLAN_LOCAL_SCRATCH_OFFSET 0x000000c0
|
||||
#define WLAN_LOCAL_SCRATCH_VALUE_MSB 7
|
||||
#define WLAN_LOCAL_SCRATCH_VALUE_LSB 0
|
||||
#define WLAN_LOCAL_SCRATCH_VALUE_MASK 0x000000ff
|
||||
#define WLAN_LOCAL_SCRATCH_VALUE_GET(x) (((x) & WLAN_LOCAL_SCRATCH_VALUE_MASK) >> WLAN_LOCAL_SCRATCH_VALUE_LSB)
|
||||
#define WLAN_LOCAL_SCRATCH_VALUE_SET(x) (((x) << WLAN_LOCAL_SCRATCH_VALUE_LSB) & WLAN_LOCAL_SCRATCH_VALUE_MASK)
|
||||
|
||||
#define WLAN_USE_LOCAL_BUS_ADDRESS 0x000000e0
|
||||
#define WLAN_USE_LOCAL_BUS_OFFSET 0x000000e0
|
||||
#define WLAN_USE_LOCAL_BUS_PIN_INIT_MSB 0
|
||||
#define WLAN_USE_LOCAL_BUS_PIN_INIT_LSB 0
|
||||
#define WLAN_USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001
|
||||
#define WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) >> WLAN_USE_LOCAL_BUS_PIN_INIT_LSB)
|
||||
#define WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK)
|
||||
|
||||
#define WLAN_SDIO_CONFIG_ADDRESS 0x000000e4
|
||||
#define WLAN_SDIO_CONFIG_OFFSET 0x000000e4
|
||||
#define WLAN_SDIO_CONFIG_CCCR_IOR1_MSB 0
|
||||
#define WLAN_SDIO_CONFIG_CCCR_IOR1_LSB 0
|
||||
#define WLAN_SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001
|
||||
#define WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) >> WLAN_SDIO_CONFIG_CCCR_IOR1_LSB)
|
||||
#define WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK)
|
||||
|
||||
#define WLAN_MBOX_DEBUG_ADDRESS 0x000000e8
|
||||
#define WLAN_MBOX_DEBUG_OFFSET 0x000000e8
|
||||
#define WLAN_MBOX_DEBUG_SEL_MSB 2
|
||||
#define WLAN_MBOX_DEBUG_SEL_LSB 0
|
||||
#define WLAN_MBOX_DEBUG_SEL_MASK 0x00000007
|
||||
#define WLAN_MBOX_DEBUG_SEL_GET(x) (((x) & WLAN_MBOX_DEBUG_SEL_MASK) >> WLAN_MBOX_DEBUG_SEL_LSB)
|
||||
#define WLAN_MBOX_DEBUG_SEL_SET(x) (((x) << WLAN_MBOX_DEBUG_SEL_LSB) & WLAN_MBOX_DEBUG_SEL_MASK)
|
||||
|
||||
#define WLAN_MBOX_FIFO_RESET_ADDRESS 0x000000ec
|
||||
#define WLAN_MBOX_FIFO_RESET_OFFSET 0x000000ec
|
||||
#define WLAN_MBOX_FIFO_RESET_INIT_MSB 0
|
||||
#define WLAN_MBOX_FIFO_RESET_INIT_LSB 0
|
||||
#define WLAN_MBOX_FIFO_RESET_INIT_MASK 0x00000001
|
||||
#define WLAN_MBOX_FIFO_RESET_INIT_GET(x) (((x) & WLAN_MBOX_FIFO_RESET_INIT_MASK) >> WLAN_MBOX_FIFO_RESET_INIT_LSB)
|
||||
#define WLAN_MBOX_FIFO_RESET_INIT_SET(x) (((x) << WLAN_MBOX_FIFO_RESET_INIT_LSB) & WLAN_MBOX_FIFO_RESET_INIT_MASK)
|
||||
|
||||
#define WLAN_MBOX_TXFIFO_POP_ADDRESS 0x000000f0
|
||||
#define WLAN_MBOX_TXFIFO_POP_OFFSET 0x000000f0
|
||||
#define WLAN_MBOX_TXFIFO_POP_DATA_MSB 0
|
||||
#define WLAN_MBOX_TXFIFO_POP_DATA_LSB 0
|
||||
#define WLAN_MBOX_TXFIFO_POP_DATA_MASK 0x00000001
|
||||
#define WLAN_MBOX_TXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) >> WLAN_MBOX_TXFIFO_POP_DATA_LSB)
|
||||
#define WLAN_MBOX_TXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_TXFIFO_POP_DATA_LSB) & WLAN_MBOX_TXFIFO_POP_DATA_MASK)
|
||||
|
||||
#define WLAN_MBOX_RXFIFO_POP_ADDRESS 0x00000100
|
||||
#define WLAN_MBOX_RXFIFO_POP_OFFSET 0x00000100
|
||||
#define WLAN_MBOX_RXFIFO_POP_DATA_MSB 0
|
||||
#define WLAN_MBOX_RXFIFO_POP_DATA_LSB 0
|
||||
#define WLAN_MBOX_RXFIFO_POP_DATA_MASK 0x00000001
|
||||
#define WLAN_MBOX_RXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) >> WLAN_MBOX_RXFIFO_POP_DATA_LSB)
|
||||
#define WLAN_MBOX_RXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_RXFIFO_POP_DATA_LSB) & WLAN_MBOX_RXFIFO_POP_DATA_MASK)
|
||||
|
||||
#define WLAN_SDIO_DEBUG_ADDRESS 0x00000110
|
||||
#define WLAN_SDIO_DEBUG_OFFSET 0x00000110
|
||||
#define WLAN_SDIO_DEBUG_SEL_MSB 3
|
||||
#define WLAN_SDIO_DEBUG_SEL_LSB 0
|
||||
#define WLAN_SDIO_DEBUG_SEL_MASK 0x0000000f
|
||||
#define WLAN_SDIO_DEBUG_SEL_GET(x) (((x) & WLAN_SDIO_DEBUG_SEL_MASK) >> WLAN_SDIO_DEBUG_SEL_LSB)
|
||||
#define WLAN_SDIO_DEBUG_SEL_SET(x) (((x) << WLAN_SDIO_DEBUG_SEL_LSB) & WLAN_SDIO_DEBUG_SEL_MASK)
|
||||
|
||||
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000114
|
||||
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000114
|
||||
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
|
||||
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
|
||||
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
|
||||
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
|
||||
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
|
||||
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000118
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET 0x00000118
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB 2
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB 2
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB)
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK)
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB 1
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB 1
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB)
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK)
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB 0
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB 0
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB)
|
||||
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK)
|
||||
|
||||
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0000011c
|
||||
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x0000011c
|
||||
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
|
||||
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
|
||||
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
|
||||
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
|
||||
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
|
||||
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS 0x00000120
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET 0x00000120
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB 2
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB 2
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB)
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK)
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB 1
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB 1
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB)
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK)
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB 0
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB 0
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB)
|
||||
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK)
|
||||
|
||||
#define WLAN_GMBOX_INT_STATUS_ADDRESS 0x00000124
|
||||
#define WLAN_GMBOX_INT_STATUS_OFFSET 0x00000124
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB 6
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB 6
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000040
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB)
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK)
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB 5
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB 5
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000020
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 4
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 4
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000010
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 3
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 3
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000008
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 2
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 2
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000004
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
|
||||
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB 0
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB 0
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB)
|
||||
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK)
|
||||
|
||||
#define WLAN_GMBOX_INT_ENABLE_ADDRESS 0x00000128
|
||||
#define WLAN_GMBOX_INT_ENABLE_OFFSET 0x00000128
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB 6
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB 6
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000040
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 5
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 5
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000020
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 4
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 4
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000010
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 3
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 3
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000008
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 2
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 2
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000004
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
|
||||
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
|
||||
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
|
||||
|
||||
#define WLAN_HOST_IF_WINDOW_ADDRESS 0x00002000
|
||||
#define WLAN_HOST_IF_WINDOW_OFFSET 0x00002000
|
||||
#define WLAN_HOST_IF_WINDOW_DATA_MSB 7
|
||||
#define WLAN_HOST_IF_WINDOW_DATA_LSB 0
|
||||
#define WLAN_HOST_IF_WINDOW_DATA_MASK 0x000000ff
|
||||
#define WLAN_HOST_IF_WINDOW_DATA_GET(x) (((x) & WLAN_HOST_IF_WINDOW_DATA_MASK) >> WLAN_HOST_IF_WINDOW_DATA_LSB)
|
||||
#define WLAN_HOST_IF_WINDOW_DATA_SET(x) (((x) << WLAN_HOST_IF_WINDOW_DATA_LSB) & WLAN_HOST_IF_WINDOW_DATA_MASK)
|
||||
|
||||
#endif /* _MBOX_WLAN_REG_H_ */
|
|
@ -1,187 +0,0 @@
|
|||
// ------------------------------------------------------------------
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
// ------------------------------------------------------------------
|
||||
//===================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//===================================================================
|
||||
|
||||
|
||||
#include "rtc_wlan_reg.h"
|
||||
|
||||
#ifndef BT_HEADERS
|
||||
|
||||
#define RESET_CONTROL_ADDRESS WLAN_RESET_CONTROL_ADDRESS
|
||||
#define RESET_CONTROL_OFFSET WLAN_RESET_CONTROL_OFFSET
|
||||
#define RESET_CONTROL_DEBUG_UART_RST_MSB WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB
|
||||
#define RESET_CONTROL_DEBUG_UART_RST_LSB WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB
|
||||
#define RESET_CONTROL_DEBUG_UART_RST_MASK WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK
|
||||
#define RESET_CONTROL_DEBUG_UART_RST_GET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x)
|
||||
#define RESET_CONTROL_DEBUG_UART_RST_SET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x)
|
||||
#define RESET_CONTROL_BB_COLD_RST_MSB WLAN_RESET_CONTROL_BB_COLD_RST_MSB
|
||||
#define RESET_CONTROL_BB_COLD_RST_LSB WLAN_RESET_CONTROL_BB_COLD_RST_LSB
|
||||
#define RESET_CONTROL_BB_COLD_RST_MASK WLAN_RESET_CONTROL_BB_COLD_RST_MASK
|
||||
#define RESET_CONTROL_BB_COLD_RST_GET(x) WLAN_RESET_CONTROL_BB_COLD_RST_GET(x)
|
||||
#define RESET_CONTROL_BB_COLD_RST_SET(x) WLAN_RESET_CONTROL_BB_COLD_RST_SET(x)
|
||||
#define RESET_CONTROL_BB_WARM_RST_MSB WLAN_RESET_CONTROL_BB_WARM_RST_MSB
|
||||
#define RESET_CONTROL_BB_WARM_RST_LSB WLAN_RESET_CONTROL_BB_WARM_RST_LSB
|
||||
#define RESET_CONTROL_BB_WARM_RST_MASK WLAN_RESET_CONTROL_BB_WARM_RST_MASK
|
||||
#define RESET_CONTROL_BB_WARM_RST_GET(x) WLAN_RESET_CONTROL_BB_WARM_RST_GET(x)
|
||||
#define RESET_CONTROL_BB_WARM_RST_SET(x) WLAN_RESET_CONTROL_BB_WARM_RST_SET(x)
|
||||
#define RESET_CONTROL_CPU_INIT_RESET_MSB WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB
|
||||
#define RESET_CONTROL_CPU_INIT_RESET_LSB WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB
|
||||
#define RESET_CONTROL_CPU_INIT_RESET_MASK WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK
|
||||
#define RESET_CONTROL_CPU_INIT_RESET_GET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x)
|
||||
#define RESET_CONTROL_CPU_INIT_RESET_SET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x)
|
||||
#define RESET_CONTROL_VMC_REMAP_RESET_MSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB
|
||||
#define RESET_CONTROL_VMC_REMAP_RESET_LSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB
|
||||
#define RESET_CONTROL_VMC_REMAP_RESET_MASK WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK
|
||||
#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x)
|
||||
#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x)
|
||||
#define RESET_CONTROL_RST_OUT_MSB WLAN_RESET_CONTROL_RST_OUT_MSB
|
||||
#define RESET_CONTROL_RST_OUT_LSB WLAN_RESET_CONTROL_RST_OUT_LSB
|
||||
#define RESET_CONTROL_RST_OUT_MASK WLAN_RESET_CONTROL_RST_OUT_MASK
|
||||
#define RESET_CONTROL_RST_OUT_GET(x) WLAN_RESET_CONTROL_RST_OUT_GET(x)
|
||||
#define RESET_CONTROL_RST_OUT_SET(x) WLAN_RESET_CONTROL_RST_OUT_SET(x)
|
||||
#define RESET_CONTROL_COLD_RST_MSB WLAN_RESET_CONTROL_COLD_RST_MSB
|
||||
#define RESET_CONTROL_COLD_RST_LSB WLAN_RESET_CONTROL_COLD_RST_LSB
|
||||
#define RESET_CONTROL_COLD_RST_MASK WLAN_RESET_CONTROL_COLD_RST_MASK
|
||||
#define RESET_CONTROL_COLD_RST_GET(x) WLAN_RESET_CONTROL_COLD_RST_GET(x)
|
||||
#define RESET_CONTROL_COLD_RST_SET(x) WLAN_RESET_CONTROL_COLD_RST_SET(x)
|
||||
#define RESET_CONTROL_WARM_RST_MSB WLAN_RESET_CONTROL_WARM_RST_MSB
|
||||
#define RESET_CONTROL_WARM_RST_LSB WLAN_RESET_CONTROL_WARM_RST_LSB
|
||||
#define RESET_CONTROL_WARM_RST_MASK WLAN_RESET_CONTROL_WARM_RST_MASK
|
||||
#define RESET_CONTROL_WARM_RST_GET(x) WLAN_RESET_CONTROL_WARM_RST_GET(x)
|
||||
#define RESET_CONTROL_WARM_RST_SET(x) WLAN_RESET_CONTROL_WARM_RST_SET(x)
|
||||
#define RESET_CONTROL_CPU_WARM_RST_MSB WLAN_RESET_CONTROL_CPU_WARM_RST_MSB
|
||||
#define RESET_CONTROL_CPU_WARM_RST_LSB WLAN_RESET_CONTROL_CPU_WARM_RST_LSB
|
||||
#define RESET_CONTROL_CPU_WARM_RST_MASK WLAN_RESET_CONTROL_CPU_WARM_RST_MASK
|
||||
#define RESET_CONTROL_CPU_WARM_RST_GET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x)
|
||||
#define RESET_CONTROL_CPU_WARM_RST_SET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x)
|
||||
#define RESET_CONTROL_MAC_COLD_RST_MSB WLAN_RESET_CONTROL_MAC_COLD_RST_MSB
|
||||
#define RESET_CONTROL_MAC_COLD_RST_LSB WLAN_RESET_CONTROL_MAC_COLD_RST_LSB
|
||||
#define RESET_CONTROL_MAC_COLD_RST_MASK WLAN_RESET_CONTROL_MAC_COLD_RST_MASK
|
||||
#define RESET_CONTROL_MAC_COLD_RST_GET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x)
|
||||
#define RESET_CONTROL_MAC_COLD_RST_SET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x)
|
||||
#define RESET_CONTROL_MAC_WARM_RST_MSB WLAN_RESET_CONTROL_MAC_WARM_RST_MSB
|
||||
#define RESET_CONTROL_MAC_WARM_RST_LSB WLAN_RESET_CONTROL_MAC_WARM_RST_LSB
|
||||
#define RESET_CONTROL_MAC_WARM_RST_MASK WLAN_RESET_CONTROL_MAC_WARM_RST_MASK
|
||||
#define RESET_CONTROL_MAC_WARM_RST_GET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x)
|
||||
#define RESET_CONTROL_MAC_WARM_RST_SET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x)
|
||||
#define RESET_CONTROL_MBOX_RST_MSB WLAN_RESET_CONTROL_MBOX_RST_MSB
|
||||
#define RESET_CONTROL_MBOX_RST_LSB WLAN_RESET_CONTROL_MBOX_RST_LSB
|
||||
#define RESET_CONTROL_MBOX_RST_MASK WLAN_RESET_CONTROL_MBOX_RST_MASK
|
||||
#define RESET_CONTROL_MBOX_RST_GET(x) WLAN_RESET_CONTROL_MBOX_RST_GET(x)
|
||||
#define RESET_CONTROL_MBOX_RST_SET(x) WLAN_RESET_CONTROL_MBOX_RST_SET(x)
|
||||
#define RESET_CONTROL_UART_RST_MSB WLAN_RESET_CONTROL_UART_RST_MSB
|
||||
#define RESET_CONTROL_UART_RST_LSB WLAN_RESET_CONTROL_UART_RST_LSB
|
||||
#define RESET_CONTROL_UART_RST_MASK WLAN_RESET_CONTROL_UART_RST_MASK
|
||||
#define RESET_CONTROL_UART_RST_GET(x) WLAN_RESET_CONTROL_UART_RST_GET(x)
|
||||
#define RESET_CONTROL_UART_RST_SET(x) WLAN_RESET_CONTROL_UART_RST_SET(x)
|
||||
#define RESET_CONTROL_SI0_RST_MSB WLAN_RESET_CONTROL_SI0_RST_MSB
|
||||
#define RESET_CONTROL_SI0_RST_LSB WLAN_RESET_CONTROL_SI0_RST_LSB
|
||||
#define RESET_CONTROL_SI0_RST_MASK WLAN_RESET_CONTROL_SI0_RST_MASK
|
||||
#define RESET_CONTROL_SI0_RST_GET(x) WLAN_RESET_CONTROL_SI0_RST_GET(x)
|
||||
#define RESET_CONTROL_SI0_RST_SET(x) WLAN_RESET_CONTROL_SI0_RST_SET(x)
|
||||
#define CPU_CLOCK_ADDRESS WLAN_CPU_CLOCK_ADDRESS
|
||||
#define CPU_CLOCK_OFFSET WLAN_CPU_CLOCK_OFFSET
|
||||
#define CPU_CLOCK_STANDARD_MSB WLAN_CPU_CLOCK_STANDARD_MSB
|
||||
#define CPU_CLOCK_STANDARD_LSB WLAN_CPU_CLOCK_STANDARD_LSB
|
||||
#define CPU_CLOCK_STANDARD_MASK WLAN_CPU_CLOCK_STANDARD_MASK
|
||||
#define CPU_CLOCK_STANDARD_GET(x) WLAN_CPU_CLOCK_STANDARD_GET(x)
|
||||
#define CPU_CLOCK_STANDARD_SET(x) WLAN_CPU_CLOCK_STANDARD_SET(x)
|
||||
#define CLOCK_OUT_ADDRESS WLAN_CLOCK_OUT_ADDRESS
|
||||
#define CLOCK_OUT_OFFSET WLAN_CLOCK_OUT_OFFSET
|
||||
#define CLOCK_OUT_SELECT_MSB WLAN_CLOCK_OUT_SELECT_MSB
|
||||
#define CLOCK_OUT_SELECT_LSB WLAN_CLOCK_OUT_SELECT_LSB
|
||||
#define CLOCK_OUT_SELECT_MASK WLAN_CLOCK_OUT_SELECT_MASK
|
||||
#define CLOCK_OUT_SELECT_GET(x) WLAN_CLOCK_OUT_SELECT_GET(x)
|
||||
#define CLOCK_OUT_SELECT_SET(x) WLAN_CLOCK_OUT_SELECT_SET(x)
|
||||
#define CLOCK_CONTROL_ADDRESS WLAN_CLOCK_CONTROL_ADDRESS
|
||||
#define CLOCK_CONTROL_OFFSET WLAN_CLOCK_CONTROL_OFFSET
|
||||
#define CLOCK_CONTROL_LF_CLK32_MSB WLAN_CLOCK_CONTROL_LF_CLK32_MSB
|
||||
#define CLOCK_CONTROL_LF_CLK32_LSB WLAN_CLOCK_CONTROL_LF_CLK32_LSB
|
||||
#define CLOCK_CONTROL_LF_CLK32_MASK WLAN_CLOCK_CONTROL_LF_CLK32_MASK
|
||||
#define CLOCK_CONTROL_LF_CLK32_GET(x) WLAN_CLOCK_CONTROL_LF_CLK32_GET(x)
|
||||
#define CLOCK_CONTROL_LF_CLK32_SET(x) WLAN_CLOCK_CONTROL_LF_CLK32_SET(x)
|
||||
#define CLOCK_CONTROL_SI0_CLK_MSB WLAN_CLOCK_CONTROL_SI0_CLK_MSB
|
||||
#define CLOCK_CONTROL_SI0_CLK_LSB WLAN_CLOCK_CONTROL_SI0_CLK_LSB
|
||||
#define CLOCK_CONTROL_SI0_CLK_MASK WLAN_CLOCK_CONTROL_SI0_CLK_MASK
|
||||
#define CLOCK_CONTROL_SI0_CLK_GET(x) WLAN_CLOCK_CONTROL_SI0_CLK_GET(x)
|
||||
#define CLOCK_CONTROL_SI0_CLK_SET(x) WLAN_CLOCK_CONTROL_SI0_CLK_SET(x)
|
||||
#define RESET_CAUSE_ADDRESS WLAN_RESET_CAUSE_ADDRESS
|
||||
#define RESET_CAUSE_OFFSET WLAN_RESET_CAUSE_OFFSET
|
||||
#define RESET_CAUSE_LAST_MSB WLAN_RESET_CAUSE_LAST_MSB
|
||||
#define RESET_CAUSE_LAST_LSB WLAN_RESET_CAUSE_LAST_LSB
|
||||
#define RESET_CAUSE_LAST_MASK WLAN_RESET_CAUSE_LAST_MASK
|
||||
#define RESET_CAUSE_LAST_GET(x) WLAN_RESET_CAUSE_LAST_GET(x)
|
||||
#define RESET_CAUSE_LAST_SET(x) WLAN_RESET_CAUSE_LAST_SET(x)
|
||||
#define SYSTEM_SLEEP_ADDRESS WLAN_SYSTEM_SLEEP_ADDRESS
|
||||
#define SYSTEM_SLEEP_OFFSET WLAN_SYSTEM_SLEEP_OFFSET
|
||||
#define SYSTEM_SLEEP_HOST_IF_MSB WLAN_SYSTEM_SLEEP_HOST_IF_MSB
|
||||
#define SYSTEM_SLEEP_HOST_IF_LSB WLAN_SYSTEM_SLEEP_HOST_IF_LSB
|
||||
#define SYSTEM_SLEEP_HOST_IF_MASK WLAN_SYSTEM_SLEEP_HOST_IF_MASK
|
||||
#define SYSTEM_SLEEP_HOST_IF_GET(x) WLAN_SYSTEM_SLEEP_HOST_IF_GET(x)
|
||||
#define SYSTEM_SLEEP_HOST_IF_SET(x) WLAN_SYSTEM_SLEEP_HOST_IF_SET(x)
|
||||
#define SYSTEM_SLEEP_MBOX_MSB WLAN_SYSTEM_SLEEP_MBOX_MSB
|
||||
#define SYSTEM_SLEEP_MBOX_LSB WLAN_SYSTEM_SLEEP_MBOX_LSB
|
||||
#define SYSTEM_SLEEP_MBOX_MASK WLAN_SYSTEM_SLEEP_MBOX_MASK
|
||||
#define SYSTEM_SLEEP_MBOX_GET(x) WLAN_SYSTEM_SLEEP_MBOX_GET(x)
|
||||
#define SYSTEM_SLEEP_MBOX_SET(x) WLAN_SYSTEM_SLEEP_MBOX_SET(x)
|
||||
#define SYSTEM_SLEEP_MAC_IF_MSB WLAN_SYSTEM_SLEEP_MAC_IF_MSB
|
||||
#define SYSTEM_SLEEP_MAC_IF_LSB WLAN_SYSTEM_SLEEP_MAC_IF_LSB
|
||||
#define SYSTEM_SLEEP_MAC_IF_MASK WLAN_SYSTEM_SLEEP_MAC_IF_MASK
|
||||
#define SYSTEM_SLEEP_MAC_IF_GET(x) WLAN_SYSTEM_SLEEP_MAC_IF_GET(x)
|
||||
#define SYSTEM_SLEEP_MAC_IF_SET(x) WLAN_SYSTEM_SLEEP_MAC_IF_SET(x)
|
||||
#define SYSTEM_SLEEP_LIGHT_MSB WLAN_SYSTEM_SLEEP_LIGHT_MSB
|
||||
#define SYSTEM_SLEEP_LIGHT_LSB WLAN_SYSTEM_SLEEP_LIGHT_LSB
|
||||
#define SYSTEM_SLEEP_LIGHT_MASK WLAN_SYSTEM_SLEEP_LIGHT_MASK
|
||||
#define SYSTEM_SLEEP_LIGHT_GET(x) WLAN_SYSTEM_SLEEP_LIGHT_GET(x)
|
||||
#define SYSTEM_SLEEP_LIGHT_SET(x) WLAN_SYSTEM_SLEEP_LIGHT_SET(x)
|
||||
#define SYSTEM_SLEEP_DISABLE_MSB WLAN_SYSTEM_SLEEP_DISABLE_MSB
|
||||
#define SYSTEM_SLEEP_DISABLE_LSB WLAN_SYSTEM_SLEEP_DISABLE_LSB
|
||||
#define SYSTEM_SLEEP_DISABLE_MASK WLAN_SYSTEM_SLEEP_DISABLE_MASK
|
||||
#define SYSTEM_SLEEP_DISABLE_GET(x) WLAN_SYSTEM_SLEEP_DISABLE_GET(x)
|
||||
#define SYSTEM_SLEEP_DISABLE_SET(x) WLAN_SYSTEM_SLEEP_DISABLE_SET(x)
|
||||
#define LPO_INIT_DIVIDEND_INT_ADDRESS WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS
|
||||
#define LPO_INIT_DIVIDEND_INT_OFFSET WLAN_LPO_INIT_DIVIDEND_INT_OFFSET
|
||||
#define LPO_INIT_DIVIDEND_INT_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB
|
||||
#define LPO_INIT_DIVIDEND_INT_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB
|
||||
#define LPO_INIT_DIVIDEND_INT_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK
|
||||
#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x)
|
||||
#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x)
|
||||
#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS
|
||||
#define LPO_INIT_DIVIDEND_FRACTION_OFFSET WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET
|
||||
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB
|
||||
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB
|
||||
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK
|
||||
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x)
|
||||
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x)
|
||||
#define LPO_CAL_ADDRESS WLAN_LPO_CAL_ADDRESS
|
||||
#define LPO_CAL_OFFSET WLAN_LPO_CAL_OFFSET
|
||||
#define LPO_CAL_ENABLE_MSB WLAN_LPO_CAL_ENABLE_MSB
|
||||
#define LPO_CAL_ENABLE_LSB WLAN_LPO_CAL_ENABLE_LSB
|
||||
#define LPO_CAL_ENABLE_MASK WLAN_LPO_CAL_ENABLE_MASK
|
||||
#define LPO_CAL_ENABLE_GET(x) WLAN_LPO_CAL_ENABLE_GET(x)
|
||||
#define LPO_CAL_ENABLE_SET(x) WLAN_LPO_CAL_ENABLE_SET(x)
|
||||
#define LPO_CAL_COUNT_MSB WLAN_LPO_CAL_COUNT_MSB
|
||||
#define LPO_CAL_COUNT_LSB WLAN_LPO_CAL_COUNT_LSB
|
||||
#define LPO_CAL_COUNT_MASK WLAN_LPO_CAL_COUNT_MASK
|
||||
#define LPO_CAL_COUNT_GET(x) WLAN_LPO_CAL_COUNT_GET(x)
|
||||
#define LPO_CAL_COUNT_SET(x) WLAN_LPO_CAL_COUNT_SET(x)
|
||||
|
||||
#endif
|
|
@ -1,162 +0,0 @@
|
|||
// ------------------------------------------------------------------
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
// ------------------------------------------------------------------
|
||||
//===================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//===================================================================
|
||||
|
||||
|
||||
#ifndef _RTC_WLAN_REG_REG_H_
|
||||
#define _RTC_WLAN_REG_REG_H_
|
||||
|
||||
#define WLAN_RESET_CONTROL_ADDRESS 0x00000000
|
||||
#define WLAN_RESET_CONTROL_OFFSET 0x00000000
|
||||
#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB 14
|
||||
#define WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB 14
|
||||
#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK 0x00004000
|
||||
#define WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) >> WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB)
|
||||
#define WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK)
|
||||
#define WLAN_RESET_CONTROL_BB_COLD_RST_MSB 13
|
||||
#define WLAN_RESET_CONTROL_BB_COLD_RST_LSB 13
|
||||
#define WLAN_RESET_CONTROL_BB_COLD_RST_MASK 0x00002000
|
||||
#define WLAN_RESET_CONTROL_BB_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK) >> WLAN_RESET_CONTROL_BB_COLD_RST_LSB)
|
||||
#define WLAN_RESET_CONTROL_BB_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_BB_COLD_RST_LSB) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK)
|
||||
#define WLAN_RESET_CONTROL_BB_WARM_RST_MSB 12
|
||||
#define WLAN_RESET_CONTROL_BB_WARM_RST_LSB 12
|
||||
#define WLAN_RESET_CONTROL_BB_WARM_RST_MASK 0x00001000
|
||||
#define WLAN_RESET_CONTROL_BB_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK) >> WLAN_RESET_CONTROL_BB_WARM_RST_LSB)
|
||||
#define WLAN_RESET_CONTROL_BB_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_BB_WARM_RST_LSB) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK)
|
||||
#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB 11
|
||||
#define WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB 11
|
||||
#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800
|
||||
#define WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) >> WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB)
|
||||
#define WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK)
|
||||
#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB 10
|
||||
#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB 10
|
||||
#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400
|
||||
#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) >> WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB)
|
||||
#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK)
|
||||
#define WLAN_RESET_CONTROL_RST_OUT_MSB 9
|
||||
#define WLAN_RESET_CONTROL_RST_OUT_LSB 9
|
||||
#define WLAN_RESET_CONTROL_RST_OUT_MASK 0x00000200
|
||||
#define WLAN_RESET_CONTROL_RST_OUT_GET(x) (((x) & WLAN_RESET_CONTROL_RST_OUT_MASK) >> WLAN_RESET_CONTROL_RST_OUT_LSB)
|
||||
#define WLAN_RESET_CONTROL_RST_OUT_SET(x) (((x) << WLAN_RESET_CONTROL_RST_OUT_LSB) & WLAN_RESET_CONTROL_RST_OUT_MASK)
|
||||
#define WLAN_RESET_CONTROL_COLD_RST_MSB 8
|
||||
#define WLAN_RESET_CONTROL_COLD_RST_LSB 8
|
||||
#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000100
|
||||
#define WLAN_RESET_CONTROL_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_COLD_RST_MASK) >> WLAN_RESET_CONTROL_COLD_RST_LSB)
|
||||
#define WLAN_RESET_CONTROL_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_COLD_RST_LSB) & WLAN_RESET_CONTROL_COLD_RST_MASK)
|
||||
#define WLAN_RESET_CONTROL_WARM_RST_MSB 7
|
||||
#define WLAN_RESET_CONTROL_WARM_RST_LSB 7
|
||||
#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000080
|
||||
#define WLAN_RESET_CONTROL_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_WARM_RST_MASK) >> WLAN_RESET_CONTROL_WARM_RST_LSB)
|
||||
#define WLAN_RESET_CONTROL_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_WARM_RST_LSB) & WLAN_RESET_CONTROL_WARM_RST_MASK)
|
||||
#define WLAN_RESET_CONTROL_CPU_WARM_RST_MSB 6
|
||||
#define WLAN_RESET_CONTROL_CPU_WARM_RST_LSB 6
|
||||
#define WLAN_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
|
||||
#define WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) >> WLAN_RESET_CONTROL_CPU_WARM_RST_LSB)
|
||||
#define WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK)
|
||||
#define WLAN_RESET_CONTROL_MAC_COLD_RST_MSB 5
|
||||
#define WLAN_RESET_CONTROL_MAC_COLD_RST_LSB 5
|
||||
#define WLAN_RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020
|
||||
#define WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) >> WLAN_RESET_CONTROL_MAC_COLD_RST_LSB)
|
||||
#define WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK)
|
||||
#define WLAN_RESET_CONTROL_MAC_WARM_RST_MSB 4
|
||||
#define WLAN_RESET_CONTROL_MAC_WARM_RST_LSB 4
|
||||
#define WLAN_RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010
|
||||
#define WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) >> WLAN_RESET_CONTROL_MAC_WARM_RST_LSB)
|
||||
#define WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK)
|
||||
#define WLAN_RESET_CONTROL_MBOX_RST_MSB 2
|
||||
#define WLAN_RESET_CONTROL_MBOX_RST_LSB 2
|
||||
#define WLAN_RESET_CONTROL_MBOX_RST_MASK 0x00000004
|
||||
#define WLAN_RESET_CONTROL_MBOX_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MBOX_RST_MASK) >> WLAN_RESET_CONTROL_MBOX_RST_LSB)
|
||||
#define WLAN_RESET_CONTROL_MBOX_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MBOX_RST_LSB) & WLAN_RESET_CONTROL_MBOX_RST_MASK)
|
||||
#define WLAN_RESET_CONTROL_UART_RST_MSB 1
|
||||
#define WLAN_RESET_CONTROL_UART_RST_LSB 1
|
||||
#define WLAN_RESET_CONTROL_UART_RST_MASK 0x00000002
|
||||
#define WLAN_RESET_CONTROL_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_UART_RST_MASK) >> WLAN_RESET_CONTROL_UART_RST_LSB)
|
||||
#define WLAN_RESET_CONTROL_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_UART_RST_LSB) & WLAN_RESET_CONTROL_UART_RST_MASK)
|
||||
#define WLAN_RESET_CONTROL_SI0_RST_MSB 0
|
||||
#define WLAN_RESET_CONTROL_SI0_RST_LSB 0
|
||||
#define WLAN_RESET_CONTROL_SI0_RST_MASK 0x00000001
|
||||
#define WLAN_RESET_CONTROL_SI0_RST_GET(x) (((x) & WLAN_RESET_CONTROL_SI0_RST_MASK) >> WLAN_RESET_CONTROL_SI0_RST_LSB)
|
||||
#define WLAN_RESET_CONTROL_SI0_RST_SET(x) (((x) << WLAN_RESET_CONTROL_SI0_RST_LSB) & WLAN_RESET_CONTROL_SI0_RST_MASK)
|
||||
|
||||
#define WLAN_CPU_CLOCK_ADDRESS 0x00000020
|
||||
#define WLAN_CPU_CLOCK_OFFSET 0x00000020
|
||||
#define WLAN_CPU_CLOCK_STANDARD_MSB 1
|
||||
#define WLAN_CPU_CLOCK_STANDARD_LSB 0
|
||||
#define WLAN_CPU_CLOCK_STANDARD_MASK 0x00000003
|
||||
#define WLAN_CPU_CLOCK_STANDARD_GET(x) (((x) & WLAN_CPU_CLOCK_STANDARD_MASK) >> WLAN_CPU_CLOCK_STANDARD_LSB)
|
||||
#define WLAN_CPU_CLOCK_STANDARD_SET(x) (((x) << WLAN_CPU_CLOCK_STANDARD_LSB) & WLAN_CPU_CLOCK_STANDARD_MASK)
|
||||
|
||||
#define WLAN_CLOCK_CONTROL_ADDRESS 0x00000028
|
||||
#define WLAN_CLOCK_CONTROL_OFFSET 0x00000028
|
||||
#define WLAN_CLOCK_CONTROL_LF_CLK32_MSB 2
|
||||
#define WLAN_CLOCK_CONTROL_LF_CLK32_LSB 2
|
||||
#define WLAN_CLOCK_CONTROL_LF_CLK32_MASK 0x00000004
|
||||
#define WLAN_CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK) >> WLAN_CLOCK_CONTROL_LF_CLK32_LSB)
|
||||
#define WLAN_CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << WLAN_CLOCK_CONTROL_LF_CLK32_LSB) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK)
|
||||
#define WLAN_CLOCK_CONTROL_SI0_CLK_MSB 0
|
||||
#define WLAN_CLOCK_CONTROL_SI0_CLK_LSB 0
|
||||
#define WLAN_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
|
||||
#define WLAN_CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) >> WLAN_CLOCK_CONTROL_SI0_CLK_LSB)
|
||||
#define WLAN_CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << WLAN_CLOCK_CONTROL_SI0_CLK_LSB) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK)
|
||||
|
||||
#define WLAN_SYSTEM_SLEEP_ADDRESS 0x000000c4
|
||||
#define WLAN_SYSTEM_SLEEP_OFFSET 0x000000c4
|
||||
#define WLAN_SYSTEM_SLEEP_HOST_IF_MSB 4
|
||||
#define WLAN_SYSTEM_SLEEP_HOST_IF_LSB 4
|
||||
#define WLAN_SYSTEM_SLEEP_HOST_IF_MASK 0x00000010
|
||||
#define WLAN_SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK) >> WLAN_SYSTEM_SLEEP_HOST_IF_LSB)
|
||||
#define WLAN_SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_HOST_IF_LSB) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK)
|
||||
#define WLAN_SYSTEM_SLEEP_MBOX_MSB 3
|
||||
#define WLAN_SYSTEM_SLEEP_MBOX_LSB 3
|
||||
#define WLAN_SYSTEM_SLEEP_MBOX_MASK 0x00000008
|
||||
#define WLAN_SYSTEM_SLEEP_MBOX_GET(x) (((x) & WLAN_SYSTEM_SLEEP_MBOX_MASK) >> WLAN_SYSTEM_SLEEP_MBOX_LSB)
|
||||
#define WLAN_SYSTEM_SLEEP_MBOX_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MBOX_LSB) & WLAN_SYSTEM_SLEEP_MBOX_MASK)
|
||||
#define WLAN_SYSTEM_SLEEP_MAC_IF_MSB 2
|
||||
#define WLAN_SYSTEM_SLEEP_MAC_IF_LSB 2
|
||||
#define WLAN_SYSTEM_SLEEP_MAC_IF_MASK 0x00000004
|
||||
#define WLAN_SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK) >> WLAN_SYSTEM_SLEEP_MAC_IF_LSB)
|
||||
#define WLAN_SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MAC_IF_LSB) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK)
|
||||
#define WLAN_SYSTEM_SLEEP_LIGHT_MSB 1
|
||||
#define WLAN_SYSTEM_SLEEP_LIGHT_LSB 1
|
||||
#define WLAN_SYSTEM_SLEEP_LIGHT_MASK 0x00000002
|
||||
#define WLAN_SYSTEM_SLEEP_LIGHT_GET(x) (((x) & WLAN_SYSTEM_SLEEP_LIGHT_MASK) >> WLAN_SYSTEM_SLEEP_LIGHT_LSB)
|
||||
#define WLAN_SYSTEM_SLEEP_LIGHT_SET(x) (((x) << WLAN_SYSTEM_SLEEP_LIGHT_LSB) & WLAN_SYSTEM_SLEEP_LIGHT_MASK)
|
||||
#define WLAN_SYSTEM_SLEEP_DISABLE_MSB 0
|
||||
#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
|
||||
#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
|
||||
#define WLAN_SYSTEM_SLEEP_DISABLE_GET(x) (((x) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) >> WLAN_SYSTEM_SLEEP_DISABLE_LSB)
|
||||
#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & WLAN_SYSTEM_SLEEP_DISABLE_MASK)
|
||||
|
||||
#define WLAN_LPO_CAL_ADDRESS 0x000000e0
|
||||
#define WLAN_LPO_CAL_OFFSET 0x000000e0
|
||||
#define WLAN_LPO_CAL_ENABLE_MSB 20
|
||||
#define WLAN_LPO_CAL_ENABLE_LSB 20
|
||||
#define WLAN_LPO_CAL_ENABLE_MASK 0x00100000
|
||||
#define WLAN_LPO_CAL_ENABLE_GET(x) (((x) & WLAN_LPO_CAL_ENABLE_MASK) >> WLAN_LPO_CAL_ENABLE_LSB)
|
||||
#define WLAN_LPO_CAL_ENABLE_SET(x) (((x) << WLAN_LPO_CAL_ENABLE_LSB) & WLAN_LPO_CAL_ENABLE_MASK)
|
||||
#define WLAN_LPO_CAL_COUNT_MSB 19
|
||||
#define WLAN_LPO_CAL_COUNT_LSB 0
|
||||
#define WLAN_LPO_CAL_COUNT_MASK 0x000fffff
|
||||
#define WLAN_LPO_CAL_COUNT_GET(x) (((x) & WLAN_LPO_CAL_COUNT_MASK) >> WLAN_LPO_CAL_COUNT_LSB)
|
||||
#define WLAN_LPO_CAL_COUNT_SET(x) (((x) << WLAN_LPO_CAL_COUNT_LSB) & WLAN_LPO_CAL_COUNT_MASK)
|
||||
|
||||
#endif /* _RTC_WLAN_REG_H_ */
|
|
@ -1,40 +0,0 @@
|
|||
// ------------------------------------------------------------------
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
// ------------------------------------------------------------------
|
||||
//===================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//===================================================================
|
||||
|
||||
|
||||
#ifndef _UART_REG_REG_H_
|
||||
#define _UART_REG_REG_H_
|
||||
|
||||
#define UART_CLKDIV_ADDRESS 0x00000008
|
||||
#define UART_CLKDIV_OFFSET 0x00000008
|
||||
#define UART_CLKDIV_CLK_SCALE_MSB 23
|
||||
#define UART_CLKDIV_CLK_SCALE_LSB 16
|
||||
#define UART_CLKDIV_CLK_SCALE_MASK 0x00ff0000
|
||||
#define UART_CLKDIV_CLK_SCALE_GET(x) (((x) & UART_CLKDIV_CLK_SCALE_MASK) >> UART_CLKDIV_CLK_SCALE_LSB)
|
||||
#define UART_CLKDIV_CLK_SCALE_SET(x) (((x) << UART_CLKDIV_CLK_SCALE_LSB) & UART_CLKDIV_CLK_SCALE_MASK)
|
||||
#define UART_CLKDIV_CLK_STEP_MSB 15
|
||||
#define UART_CLKDIV_CLK_STEP_LSB 0
|
||||
#define UART_CLKDIV_CLK_STEP_MASK 0x0000ffff
|
||||
#define UART_CLKDIV_CLK_STEP_GET(x) (((x) & UART_CLKDIV_CLK_STEP_MASK) >> UART_CLKDIV_CLK_STEP_LSB)
|
||||
#define UART_CLKDIV_CLK_STEP_SET(x) (((x) << UART_CLKDIV_CLK_STEP_LSB) & UART_CLKDIV_CLK_STEP_MASK)
|
||||
|
||||
#endif /* _UART_REG_H_ */
|
|
@ -1,75 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="athdefs.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef __ATHDEFS_H__
|
||||
#define __ATHDEFS_H__
|
||||
|
||||
/*
|
||||
* This file contains definitions that may be used across both
|
||||
* Host and Target software. Nothing here is module-dependent
|
||||
* or platform-dependent.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Generic error codes that can be used by hw, sta, ap, sim, dk
|
||||
* and any other environments.
|
||||
* Feel free to add any more non-zero codes that you need.
|
||||
*/
|
||||
|
||||
#define A_ERROR (-1) /* Generic error return */
|
||||
#define A_DEVICE_NOT_FOUND 1 /* not able to find PCI device */
|
||||
#define A_NO_MEMORY 2 /* not able to allocate memory,
|
||||
* not avail#defineable */
|
||||
#define A_MEMORY_NOT_AVAIL 3 /* memory region is not free for
|
||||
* mapping */
|
||||
#define A_NO_FREE_DESC 4 /* no free descriptors available */
|
||||
#define A_BAD_ADDRESS 5 /* address does not match descriptor */
|
||||
#define A_WIN_DRIVER_ERROR 6 /* used in NT_HW version,
|
||||
* if problem at init */
|
||||
#define A_REGS_NOT_MAPPED 7 /* registers not correctly mapped */
|
||||
#define A_EPERM 8 /* Not superuser */
|
||||
#define A_EACCES 0 /* Access denied */
|
||||
#define A_ENOENT 10 /* No such entry, search failed, etc. */
|
||||
#define A_EEXIST 11 /* The object already exists
|
||||
* (can't create) */
|
||||
#define A_EFAULT 12 /* Bad address fault */
|
||||
#define A_EBUSY 13 /* Object is busy */
|
||||
#define A_EINVAL 14 /* Invalid parameter */
|
||||
#define A_EMSGSIZE 15 /* Bad message buffer length */
|
||||
#define A_ECANCELED 16 /* Operation canceled */
|
||||
#define A_ENOTSUP 17 /* Operation not supported */
|
||||
#define A_ECOMM 18 /* Communication error on send */
|
||||
#define A_EPROTO 19 /* Protocol error */
|
||||
#define A_ENODEV 20 /* No such device */
|
||||
#define A_EDEVNOTUP 21 /* device is not UP */
|
||||
#define A_NO_RESOURCE 22 /* No resources for
|
||||
* requested operation */
|
||||
#define A_HARDWARE 23 /* Hardware failure */
|
||||
#define A_PENDING 24 /* Asynchronous routine; will send up
|
||||
* results later
|
||||
* (typically in callback) */
|
||||
#define A_EBADCHANNEL 25 /* The channel cannot be used */
|
||||
#define A_DECRYPT_ERROR 26 /* Decryption error */
|
||||
#define A_PHY_ERROR 27 /* RX PHY error */
|
||||
#define A_CONSUMED 28 /* Object was consumed */
|
||||
|
||||
#endif /* __ATHDEFS_H__ */
|
|
@ -1,233 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __BMI_MSG_H__
|
||||
#define __BMI_MSG_H__
|
||||
|
||||
/*
|
||||
* Bootloader Messaging Interface (BMI)
|
||||
*
|
||||
* BMI is a very simple messaging interface used during initialization
|
||||
* to read memory, write memory, execute code, and to define an
|
||||
* application entry PC.
|
||||
*
|
||||
* It is used to download an application to AR6K, to provide
|
||||
* patches to code that is already resident on AR6K, and generally
|
||||
* to examine and modify state. The Host has an opportunity to use
|
||||
* BMI only once during bootup. Once the Host issues a BMI_DONE
|
||||
* command, this opportunity ends.
|
||||
*
|
||||
* The Host writes BMI requests to mailbox0, and reads BMI responses
|
||||
* from mailbox0. BMI requests all begin with a command
|
||||
* (see below for specific commands), and are followed by
|
||||
* command-specific data.
|
||||
*
|
||||
* Flow control:
|
||||
* The Host can only issue a command once the Target gives it a
|
||||
* "BMI Command Credit", using AR6K Counter #4. As soon as the
|
||||
* Target has completed a command, it issues another BMI Command
|
||||
* Credit (so the Host can issue the next command).
|
||||
*
|
||||
* BMI handles all required Target-side cache flushing.
|
||||
*/
|
||||
|
||||
|
||||
/* Maximum data size used for BMI transfers */
|
||||
#define BMI_DATASZ_MAX 256
|
||||
|
||||
/* BMI Commands */
|
||||
|
||||
#define BMI_NO_COMMAND 0
|
||||
|
||||
#define BMI_DONE 1
|
||||
/*
|
||||
* Semantics: Host is done using BMI
|
||||
* Request format:
|
||||
* u32 command (BMI_DONE)
|
||||
* Response format: none
|
||||
*/
|
||||
|
||||
#define BMI_READ_MEMORY 2
|
||||
/*
|
||||
* Semantics: Host reads AR6K memory
|
||||
* Request format:
|
||||
* u32 command (BMI_READ_MEMORY)
|
||||
* u32 address
|
||||
* u32 length, at most BMI_DATASZ_MAX
|
||||
* Response format:
|
||||
* u8 data[length]
|
||||
*/
|
||||
|
||||
#define BMI_WRITE_MEMORY 3
|
||||
/*
|
||||
* Semantics: Host writes AR6K memory
|
||||
* Request format:
|
||||
* u32 command (BMI_WRITE_MEMORY)
|
||||
* u32 address
|
||||
* u32 length, at most BMI_DATASZ_MAX
|
||||
* u8 data[length]
|
||||
* Response format: none
|
||||
*/
|
||||
|
||||
#define BMI_EXECUTE 4
|
||||
/*
|
||||
* Semantics: Causes AR6K to execute code
|
||||
* Request format:
|
||||
* u32 command (BMI_EXECUTE)
|
||||
* u32 address
|
||||
* u32 parameter
|
||||
* Response format:
|
||||
* u32 return value
|
||||
*/
|
||||
|
||||
#define BMI_SET_APP_START 5
|
||||
/*
|
||||
* Semantics: Set Target application starting address
|
||||
* Request format:
|
||||
* u32 command (BMI_SET_APP_START)
|
||||
* u32 address
|
||||
* Response format: none
|
||||
*/
|
||||
|
||||
#define BMI_READ_SOC_REGISTER 6
|
||||
/*
|
||||
* Semantics: Read a 32-bit Target SOC register.
|
||||
* Request format:
|
||||
* u32 command (BMI_READ_REGISTER)
|
||||
* u32 address
|
||||
* Response format:
|
||||
* u32 value
|
||||
*/
|
||||
|
||||
#define BMI_WRITE_SOC_REGISTER 7
|
||||
/*
|
||||
* Semantics: Write a 32-bit Target SOC register.
|
||||
* Request format:
|
||||
* u32 command (BMI_WRITE_REGISTER)
|
||||
* u32 address
|
||||
* u32 value
|
||||
*
|
||||
* Response format: none
|
||||
*/
|
||||
|
||||
#define BMI_GET_TARGET_ID 8
|
||||
#define BMI_GET_TARGET_INFO 8
|
||||
/*
|
||||
* Semantics: Fetch the 4-byte Target information
|
||||
* Request format:
|
||||
* u32 command (BMI_GET_TARGET_ID/INFO)
|
||||
* Response format1 (old firmware):
|
||||
* u32 TargetVersionID
|
||||
* Response format2 (newer firmware):
|
||||
* u32 TARGET_VERSION_SENTINAL
|
||||
* struct bmi_target_info;
|
||||
*/
|
||||
|
||||
PREPACK struct bmi_target_info {
|
||||
u32 target_info_byte_count; /* size of this structure */
|
||||
u32 target_ver; /* Target Version ID */
|
||||
u32 target_type; /* Target type */
|
||||
} POSTPACK;
|
||||
#define TARGET_VERSION_SENTINAL 0xffffffff
|
||||
#define TARGET_TYPE_AR6001 1
|
||||
#define TARGET_TYPE_AR6002 2
|
||||
#define TARGET_TYPE_AR6003 3
|
||||
|
||||
|
||||
#define BMI_ROMPATCH_INSTALL 9
|
||||
/*
|
||||
* Semantics: Install a ROM Patch.
|
||||
* Request format:
|
||||
* u32 command (BMI_ROMPATCH_INSTALL)
|
||||
* u32 Target ROM Address
|
||||
* u32 Target RAM Address or Value (depending on Target Type)
|
||||
* u32 Size, in bytes
|
||||
* u32 Activate? 1-->activate;
|
||||
* 0-->install but do not activate
|
||||
* Response format:
|
||||
* u32 PatchID
|
||||
*/
|
||||
|
||||
#define BMI_ROMPATCH_UNINSTALL 10
|
||||
/*
|
||||
* Semantics: Uninstall a previously-installed ROM Patch,
|
||||
* automatically deactivating, if necessary.
|
||||
* Request format:
|
||||
* u32 command (BMI_ROMPATCH_UNINSTALL)
|
||||
* u32 PatchID
|
||||
*
|
||||
* Response format: none
|
||||
*/
|
||||
|
||||
#define BMI_ROMPATCH_ACTIVATE 11
|
||||
/*
|
||||
* Semantics: Activate a list of previously-installed ROM Patches.
|
||||
* Request format:
|
||||
* u32 command (BMI_ROMPATCH_ACTIVATE)
|
||||
* u32 rompatch_count
|
||||
* u32 PatchID[rompatch_count]
|
||||
*
|
||||
* Response format: none
|
||||
*/
|
||||
|
||||
#define BMI_ROMPATCH_DEACTIVATE 12
|
||||
/*
|
||||
* Semantics: Deactivate a list of active ROM Patches.
|
||||
* Request format:
|
||||
* u32 command (BMI_ROMPATCH_DEACTIVATE)
|
||||
* u32 rompatch_count
|
||||
* u32 PatchID[rompatch_count]
|
||||
*
|
||||
* Response format: none
|
||||
*/
|
||||
|
||||
|
||||
#define BMI_LZ_STREAM_START 13
|
||||
/*
|
||||
* Semantics: Begin an LZ-compressed stream of input
|
||||
* which is to be uncompressed by the Target to an
|
||||
* output buffer at address. The output buffer must
|
||||
* be sufficiently large to hold the uncompressed
|
||||
* output from the compressed input stream. This BMI
|
||||
* command should be followed by a series of 1 or more
|
||||
* BMI_LZ_DATA commands.
|
||||
* u32 command (BMI_LZ_STREAM_START)
|
||||
* u32 address
|
||||
* Note: Not supported on all versions of ROM firmware.
|
||||
*/
|
||||
|
||||
#define BMI_LZ_DATA 14
|
||||
/*
|
||||
* Semantics: Host writes AR6K memory with LZ-compressed
|
||||
* data which is uncompressed by the Target. This command
|
||||
* must be preceded by a BMI_LZ_STREAM_START command. A series
|
||||
* of BMI_LZ_DATA commands are considered part of a single
|
||||
* input stream until another BMI_LZ_STREAM_START is issued.
|
||||
* Request format:
|
||||
* u32 command (BMI_LZ_DATA)
|
||||
* u32 length (of compressed data),
|
||||
* at most BMI_DATASZ_MAX
|
||||
* u8 CompressedData[length]
|
||||
* Response format: none
|
||||
* Note: Not supported on all versions of ROM firmware.
|
||||
*/
|
||||
|
||||
#endif /* __BMI_MSG_H__ */
|
|
@ -1,36 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="cnxmgmt.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef _CNXMGMT_H_
|
||||
#define _CNXMGMT_H_
|
||||
|
||||
typedef enum {
|
||||
CM_CONNECT_WITHOUT_SCAN = 0x0001,
|
||||
CM_CONNECT_ASSOC_POLICY_USER = 0x0002,
|
||||
CM_CONNECT_SEND_REASSOC = 0x0004,
|
||||
CM_CONNECT_WITHOUT_ROAMTABLE_UPDATE = 0x0008,
|
||||
CM_CONNECT_DO_WPA_OFFLOAD = 0x0010,
|
||||
CM_CONNECT_DO_NOT_DEAUTH = 0x0020,
|
||||
} CM_CONNECT_TYPE;
|
||||
|
||||
#endif /* _CNXMGMT_H_ */
|
|
@ -1,126 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="dbglog.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef _DBGLOG_H_
|
||||
#define _DBGLOG_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DBGLOG_TIMESTAMP_OFFSET 0
|
||||
#define DBGLOG_TIMESTAMP_MASK 0x0000FFFF /* Bit 0-15. Contains bit
|
||||
8-23 of the LF0 timer */
|
||||
#define DBGLOG_DBGID_OFFSET 16
|
||||
#define DBGLOG_DBGID_MASK 0x03FF0000 /* Bit 16-25 */
|
||||
#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */
|
||||
|
||||
#define DBGLOG_MODULEID_OFFSET 26
|
||||
#define DBGLOG_MODULEID_MASK 0x3C000000 /* Bit 26-29 */
|
||||
#define DBGLOG_MODULEID_NUM_MAX 16 /* Upper limit is width of mask */
|
||||
|
||||
/*
|
||||
* Please ensure that the definition of any new module introduced is captured
|
||||
* between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The
|
||||
* structure is required for the parser to correctly pick up the values for
|
||||
* different modules.
|
||||
*/
|
||||
#define DBGLOG_MODULEID_START
|
||||
#define DBGLOG_MODULEID_INF 0
|
||||
#define DBGLOG_MODULEID_WMI 1
|
||||
#define DBGLOG_MODULEID_MISC 2
|
||||
#define DBGLOG_MODULEID_PM 3
|
||||
#define DBGLOG_MODULEID_TXRX_MGMTBUF 4
|
||||
#define DBGLOG_MODULEID_TXRX_TXBUF 5
|
||||
#define DBGLOG_MODULEID_TXRX_RXBUF 6
|
||||
#define DBGLOG_MODULEID_WOW 7
|
||||
#define DBGLOG_MODULEID_WHAL 8
|
||||
#define DBGLOG_MODULEID_DC 9
|
||||
#define DBGLOG_MODULEID_CO 10
|
||||
#define DBGLOG_MODULEID_RO 11
|
||||
#define DBGLOG_MODULEID_CM 12
|
||||
#define DBGLOG_MODULEID_MGMT 13
|
||||
#define DBGLOG_MODULEID_TMR 14
|
||||
#define DBGLOG_MODULEID_BTCOEX 15
|
||||
#define DBGLOG_MODULEID_END
|
||||
|
||||
#define DBGLOG_NUM_ARGS_OFFSET 30
|
||||
#define DBGLOG_NUM_ARGS_MASK 0xC0000000 /* Bit 30-31 */
|
||||
#define DBGLOG_NUM_ARGS_MAX 2 /* Upper limit is width of mask */
|
||||
|
||||
#define DBGLOG_MODULE_LOG_ENABLE_OFFSET 0
|
||||
#define DBGLOG_MODULE_LOG_ENABLE_MASK 0x0000FFFF
|
||||
|
||||
#define DBGLOG_REPORTING_ENABLED_OFFSET 16
|
||||
#define DBGLOG_REPORTING_ENABLED_MASK 0x00010000
|
||||
|
||||
#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17
|
||||
#define DBGLOG_TIMESTAMP_RESOLUTION_MASK 0x000E0000
|
||||
|
||||
#define DBGLOG_REPORT_SIZE_OFFSET 20
|
||||
#define DBGLOG_REPORT_SIZE_MASK 0x3FF00000
|
||||
|
||||
#define DBGLOG_LOG_BUFFER_SIZE 1500
|
||||
#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90
|
||||
|
||||
PREPACK struct dbglog_buf_s {
|
||||
struct dbglog_buf_s *next;
|
||||
u8 *buffer;
|
||||
u32 bufsize;
|
||||
u32 length;
|
||||
u32 count;
|
||||
u32 free;
|
||||
} POSTPACK;
|
||||
|
||||
PREPACK struct dbglog_hdr_s {
|
||||
struct dbglog_buf_s *dbuf;
|
||||
u32 dropped;
|
||||
} POSTPACK;
|
||||
|
||||
PREPACK struct dbglog_config_s {
|
||||
u32 cfgvalid; /* Mask with valid config bits */
|
||||
union {
|
||||
/* TODO: Take care of endianness */
|
||||
struct {
|
||||
u32 mmask:16; /* Mask of modules with logging on */
|
||||
u32 rep:1; /* Reporting enabled or not */
|
||||
u32 tsr:3; /* Time stamp resolution. Def: 1 ms */
|
||||
u32 size:10; /* Report size in number of messages */
|
||||
u32 reserved:2;
|
||||
} dbglog_config;
|
||||
|
||||
u32 value;
|
||||
} u;
|
||||
} POSTPACK;
|
||||
|
||||
#define cfgmmask u.dbglog_config.mmask
|
||||
#define cfgrep u.dbglog_config.rep
|
||||
#define cfgtsr u.dbglog_config.tsr
|
||||
#define cfgsize u.dbglog_config.size
|
||||
#define cfgvalue u.value
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DBGLOG_H_ */
|
|
@ -1,558 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="dbglog_id.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef _DBGLOG_ID_H_
|
||||
#define _DBGLOG_ID_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The nomenclature for the debug identifiers is MODULE_DESCRIPTION.
|
||||
* Please ensure that the definition of any new debugid introduced is captured
|
||||
* between the <MODULE>_DBGID_DEFINITION_START and
|
||||
* <MODULE>_DBGID_DEFINITION_END defines. The structure is required for the
|
||||
* parser to correctly pick up the values for different debug identifiers.
|
||||
*/
|
||||
|
||||
/* INF debug identifier definitions */
|
||||
#define INF_DBGID_DEFINITION_START
|
||||
#define INF_ASSERTION_FAILED 1
|
||||
#define INF_TARGET_ID 2
|
||||
#define INF_DBGID_DEFINITION_END
|
||||
|
||||
/* WMI debug identifier definitions */
|
||||
#define WMI_DBGID_DEFINITION_START
|
||||
#define WMI_CMD_RX_XTND_PKT_TOO_SHORT 1
|
||||
#define WMI_EXTENDED_CMD_NOT_HANDLED 2
|
||||
#define WMI_CMD_RX_PKT_TOO_SHORT 3
|
||||
#define WMI_CALLING_WMI_EXTENSION_FN 4
|
||||
#define WMI_CMD_NOT_HANDLED 5
|
||||
#define WMI_IN_SYNC 6
|
||||
#define WMI_TARGET_WMI_SYNC_CMD 7
|
||||
#define WMI_SET_SNR_THRESHOLD_PARAMS 8
|
||||
#define WMI_SET_RSSI_THRESHOLD_PARAMS 9
|
||||
#define WMI_SET_LQ_TRESHOLD_PARAMS 10
|
||||
#define WMI_TARGET_CREATE_PSTREAM_CMD 11
|
||||
#define WMI_WI_DTM_INUSE 12
|
||||
#define WMI_TARGET_DELETE_PSTREAM_CMD 13
|
||||
#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD 14
|
||||
#define WMI_TARGET_GET_BIT_RATE_CMD 15
|
||||
#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS 16
|
||||
#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD 17
|
||||
#define WMI_TARGET_GET_TX_PWR_CMD 18
|
||||
#define WMI_FREE_EVBUF_WMIBUF 19
|
||||
#define WMI_FREE_EVBUF_DATABUF 20
|
||||
#define WMI_FREE_EVBUF_BADFLAG 21
|
||||
#define WMI_HTC_RX_ERROR_DATA_PACKET 22
|
||||
#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX 23
|
||||
#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT 24
|
||||
#define WMI_SENDING_READY_EVENT 25
|
||||
#define WMI_SETPOWER_MDOE_TO_MAXPERF 26
|
||||
#define WMI_SETPOWER_MDOE_TO_REC 27
|
||||
#define WMI_BSSINFO_EVENT_FROM 28
|
||||
#define WMI_TARGET_GET_STATS_CMD 29
|
||||
#define WMI_SENDING_SCAN_COMPLETE_EVENT 30
|
||||
#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT 31
|
||||
#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT 32
|
||||
#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT 33
|
||||
#define WMI_SENDING_ERROR_REPORT_EVENT 34
|
||||
#define WMI_SENDING_CAC_EVENT 35
|
||||
#define WMI_TARGET_GET_ROAM_TABLE_CMD 36
|
||||
#define WMI_TARGET_GET_ROAM_DATA_CMD 37
|
||||
#define WMI_SENDING_GPIO_INTR_EVENT 38
|
||||
#define WMI_SENDING_GPIO_ACK_EVENT 39
|
||||
#define WMI_SENDING_GPIO_DATA_EVENT 40
|
||||
#define WMI_CMD_RX 41
|
||||
#define WMI_CMD_RX_XTND 42
|
||||
#define WMI_EVENT_SEND 43
|
||||
#define WMI_EVENT_SEND_XTND 44
|
||||
#define WMI_CMD_PARAMS_DUMP_START 45
|
||||
#define WMI_CMD_PARAMS_DUMP_END 46
|
||||
#define WMI_CMD_PARAMS 47
|
||||
#define WMI_DBGID_DEFINITION_END
|
||||
|
||||
/* MISC debug identifier definitions */
|
||||
#define MISC_DBGID_DEFINITION_START
|
||||
#define MISC_WLAN_SCHEDULER_EVENT_REGISTER_ERROR 1
|
||||
#define TLPM_INIT 2
|
||||
#define TLPM_FILTER_POWER_STATE 3
|
||||
#define TLPM_NOTIFY_NOT_IDLE 4
|
||||
#define TLPM_TIMEOUT_IDLE_HANDLER 5
|
||||
#define TLPM_TIMEOUT_WAKEUP_HANDLER 6
|
||||
#define TLPM_WAKEUP_SIGNAL_HANDLER 7
|
||||
#define TLPM_UNEXPECTED_GPIO_INTR_ERROR 8
|
||||
#define TLPM_BREAK_ON_NOT_RECEIVED_ERROR 9
|
||||
#define TLPM_BREAK_OFF_NOT_RECIVED_ERROR 10
|
||||
#define TLPM_ACK_GPIO_INTR 11
|
||||
#define TLPM_ON 12
|
||||
#define TLPM_OFF 13
|
||||
#define TLPM_WAKEUP_FROM_HOST 14
|
||||
#define TLPM_WAKEUP_FROM_BT 15
|
||||
#define TLPM_TX_BREAK_RECIVED 16
|
||||
#define TLPM_IDLE_TIMER_NOT_RUNNING 17
|
||||
#define MISC_DBGID_DEFINITION_END
|
||||
|
||||
/* TXRX debug identifier definitions */
|
||||
#define TXRX_TXBUF_DBGID_DEFINITION_START
|
||||
#define TXRX_TXBUF_ALLOCATE_BUF 1
|
||||
#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX 2
|
||||
#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ 3
|
||||
#define TXRX_TXBUF_TXQ_DEPTH 4
|
||||
#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ 5
|
||||
#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ 6
|
||||
#define TXRX_TXBUF_INITIALIZE_TIMER 7
|
||||
#define TXRX_TXBUF_ARM_TIMER 8
|
||||
#define TXRX_TXBUF_DISARM_TIMER 9
|
||||
#define TXRX_TXBUF_UNINITIALIZE_TIMER 10
|
||||
#define TXRX_TXBUF_DBGID_DEFINITION_END
|
||||
|
||||
#define TXRX_RXBUF_DBGID_DEFINITION_START
|
||||
#define TXRX_RXBUF_ALLOCATE_BUF 1
|
||||
#define TXRX_RXBUF_QUEUE_TO_HOST 2
|
||||
#define TXRX_RXBUF_QUEUE_TO_WLAN 3
|
||||
#define TXRX_RXBUF_ZERO_LEN_BUF 4
|
||||
#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN 5
|
||||
#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF 6
|
||||
#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN 7
|
||||
#define TXRX_RXBUF_SEND_TO_RECV_MGMT 8
|
||||
#define TXRX_RXBUF_SEND_TO_IEEE_LAYER 9
|
||||
#define TXRX_RXBUF_REQUEUE_ERROR 10
|
||||
#define TXRX_RXBUF_DBGID_DEFINITION_END
|
||||
|
||||
#define TXRX_MGMTBUF_DBGID_DEFINITION_START
|
||||
#define TXRX_MGMTBUF_ALLOCATE_BUF 1
|
||||
#define TXRX_MGMTBUF_ALLOCATE_SM_BUF 2
|
||||
#define TXRX_MGMTBUF_ALLOCATE_RMBUF 3
|
||||
#define TXRX_MGMTBUF_GET_BUF 4
|
||||
#define TXRX_MGMTBUF_GET_SM_BUF 5
|
||||
#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ 6
|
||||
#define TXRX_MGMTBUF_REAPED_BUF 7
|
||||
#define TXRX_MGMTBUF_REAPED_SM_BUF 8
|
||||
#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN 9
|
||||
#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN 10
|
||||
#define TXRX_MGMTBUF_ENQUEUE_INTO_DATA_SFQ 11
|
||||
#define TXRX_MGMTBUF_DEQUEUE_FROM_DATA_SFQ 12
|
||||
#define TXRX_MGMTBUF_PAUSE_DATA_TXQ 13
|
||||
#define TXRX_MGMTBUF_RESUME_DATA_TXQ 14
|
||||
#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT 15
|
||||
#define TXRX_MGMTBUF_DRAINQ 16
|
||||
#define TXRX_MGMTBUF_INDICATE_Q_DRAINED 17
|
||||
#define TXRX_MGMTBUF_ENQUEUE_INTO_HW_SFQ 18
|
||||
#define TXRX_MGMTBUF_DEQUEUE_FROM_HW_SFQ 19
|
||||
#define TXRX_MGMTBUF_PAUSE_HW_TXQ 20
|
||||
#define TXRX_MGMTBUF_RESUME_HW_TXQ 21
|
||||
#define TXRX_MGMTBUF_TEAR_DOWN_BA 22
|
||||
#define TXRX_MGMTBUF_PROCESS_ADDBA_REQ 23
|
||||
#define TXRX_MGMTBUF_PROCESS_DELBA 24
|
||||
#define TXRX_MGMTBUF_PERFORM_BA 25
|
||||
#define TXRX_MGMTBUF_WLAN_RESET_ON_ERROR 26
|
||||
#define TXRX_MGMTBUF_DBGID_DEFINITION_END
|
||||
|
||||
/* PM (Power Module) debug identifier definitions */
|
||||
#define PM_DBGID_DEFINITION_START
|
||||
#define PM_INIT 1
|
||||
#define PM_ENABLE 2
|
||||
#define PM_SET_STATE 3
|
||||
#define PM_SET_POWERMODE 4
|
||||
#define PM_CONN_NOTIFY 5
|
||||
#define PM_REF_COUNT_NEGATIVE 6
|
||||
#define PM_INFRA_STA_APSD_ENABLE 7
|
||||
#define PM_INFRA_STA_UPDATE_APSD_STATE 8
|
||||
#define PM_CHAN_OP_REQ 9
|
||||
#define PM_SET_MY_BEACON_POLICY 10
|
||||
#define PM_SET_ALL_BEACON_POLICY 11
|
||||
#define PM_INFRA_STA_SET_PM_PARAMS1 12
|
||||
#define PM_INFRA_STA_SET_PM_PARAMS2 13
|
||||
#define PM_ADHOC_SET_PM_CAPS_FAIL 14
|
||||
#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID 15
|
||||
#define PM_ADHOC_SET_PM_PARAMS 16
|
||||
#define PM_ADHOC_STATE1 18
|
||||
#define PM_ADHOC_STATE2 19
|
||||
#define PM_ADHOC_CONN_MAP 20
|
||||
#define PM_FAKE_SLEEP 21
|
||||
#define PM_AP_STATE1 22
|
||||
#define PM_AP_SET_PM_PARAMS 23
|
||||
#define PM_DBGID_DEFINITION_END
|
||||
|
||||
/* Wake on Wireless debug identifier definitions */
|
||||
#define WOW_DBGID_DEFINITION_START
|
||||
#define WOW_INIT 1
|
||||
#define WOW_GET_CONFIG_DSET 2
|
||||
#define WOW_NO_CONFIG_DSET 3
|
||||
#define WOW_INVALID_CONFIG_DSET 4
|
||||
#define WOW_USE_DEFAULT_CONFIG 5
|
||||
#define WOW_SETUP_GPIO 6
|
||||
#define WOW_INIT_DONE 7
|
||||
#define WOW_SET_GPIO_PIN 8
|
||||
#define WOW_CLEAR_GPIO_PIN 9
|
||||
#define WOW_SET_WOW_MODE_CMD 10
|
||||
#define WOW_SET_HOST_MODE_CMD 11
|
||||
#define WOW_ADD_WOW_PATTERN_CMD 12
|
||||
#define WOW_NEW_WOW_PATTERN_AT_INDEX 13
|
||||
#define WOW_DEL_WOW_PATTERN_CMD 14
|
||||
#define WOW_LIST_CONTAINS_PATTERNS 15
|
||||
#define WOW_GET_WOW_LIST_CMD 16
|
||||
#define WOW_INVALID_FILTER_ID 17
|
||||
#define WOW_INVALID_FILTER_LISTID 18
|
||||
#define WOW_NO_VALID_FILTER_AT_ID 19
|
||||
#define WOW_NO_VALID_LIST_AT_ID 20
|
||||
#define WOW_NUM_PATTERNS_EXCEEDED 21
|
||||
#define WOW_NUM_LISTS_EXCEEDED 22
|
||||
#define WOW_GET_WOW_STATS 23
|
||||
#define WOW_CLEAR_WOW_STATS 24
|
||||
#define WOW_WAKEUP_HOST 25
|
||||
#define WOW_EVENT_WAKEUP_HOST 26
|
||||
#define WOW_EVENT_DISCARD 27
|
||||
#define WOW_PATTERN_MATCH 28
|
||||
#define WOW_PATTERN_NOT_MATCH 29
|
||||
#define WOW_PATTERN_NOT_MATCH_OFFSET 30
|
||||
#define WOW_DISABLED_HOST_ASLEEP 31
|
||||
#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS 32
|
||||
#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND 33
|
||||
#define WOW_DBGID_DEFINITION_END
|
||||
|
||||
/* WHAL debug identifier definitions */
|
||||
#define WHAL_DBGID_DEFINITION_START
|
||||
#define WHAL_ERROR_ANI_CONTROL 1
|
||||
#define WHAL_ERROR_CHIP_TEST1 2
|
||||
#define WHAL_ERROR_CHIP_TEST2 3
|
||||
#define WHAL_ERROR_EEPROM_CHECKSUM 4
|
||||
#define WHAL_ERROR_EEPROM_MACADDR 5
|
||||
#define WHAL_ERROR_INTERRUPT_HIU 6
|
||||
#define WHAL_ERROR_KEYCACHE_RESET 7
|
||||
#define WHAL_ERROR_KEYCACHE_SET 8
|
||||
#define WHAL_ERROR_KEYCACHE_TYPE 9
|
||||
#define WHAL_ERROR_KEYCACHE_TKIPENTRY 10
|
||||
#define WHAL_ERROR_KEYCACHE_WEPLENGTH 11
|
||||
#define WHAL_ERROR_PHY_INVALID_CHANNEL 12
|
||||
#define WHAL_ERROR_POWER_AWAKE 13
|
||||
#define WHAL_ERROR_POWER_SET 14
|
||||
#define WHAL_ERROR_RECV_STOPDMA 15
|
||||
#define WHAL_ERROR_RECV_STOPPCU 16
|
||||
#define WHAL_ERROR_RESET_CHANNF1 17
|
||||
#define WHAL_ERROR_RESET_CHANNF2 18
|
||||
#define WHAL_ERROR_RESET_PM 19
|
||||
#define WHAL_ERROR_RESET_OFFSETCAL 20
|
||||
#define WHAL_ERROR_RESET_RFGRANT 21
|
||||
#define WHAL_ERROR_RESET_RXFRAME 22
|
||||
#define WHAL_ERROR_RESET_STOPDMA 23
|
||||
#define WHAL_ERROR_RESET_RECOVER 24
|
||||
#define WHAL_ERROR_XMIT_COMPUTE 25
|
||||
#define WHAL_ERROR_XMIT_NOQUEUE 26
|
||||
#define WHAL_ERROR_XMIT_ACTIVEQUEUE 27
|
||||
#define WHAL_ERROR_XMIT_BADTYPE 28
|
||||
#define WHAL_ERROR_XMIT_STOPDMA 29
|
||||
#define WHAL_ERROR_INTERRUPT_BB_PANIC 30
|
||||
#define WHAL_ERROR_RESET_TXIQCAL 31
|
||||
#define WHAL_ERROR_PAPRD_MAXGAIN_ABOVE_WINDOW 32
|
||||
#define WHAL_DBGID_DEFINITION_END
|
||||
|
||||
/* DC debug identifier definitions */
|
||||
#define DC_DBGID_DEFINITION_START
|
||||
#define DC_SCAN_CHAN_START 1
|
||||
#define DC_SCAN_CHAN_FINISH 2
|
||||
#define DC_BEACON_RECEIVE7 3
|
||||
#define DC_SSID_PROBE_CB 4
|
||||
#define DC_SEND_NEXT_SSID_PROBE 5
|
||||
#define DC_START_SEARCH 6
|
||||
#define DC_CANCEL_SEARCH_CB 7
|
||||
#define DC_STOP_SEARCH 8
|
||||
#define DC_END_SEARCH 9
|
||||
#define DC_MIN_CHDWELL_TIMEOUT 10
|
||||
#define DC_START_SEARCH_CANCELED 11
|
||||
#define DC_SET_POWER_MODE 12
|
||||
#define DC_INIT 13
|
||||
#define DC_SEARCH_OPPORTUNITY 14
|
||||
#define DC_RECEIVED_ANY_BEACON 15
|
||||
#define DC_RECEIVED_MY_BEACON 16
|
||||
#define DC_PROFILE_IS_ADHOC_BUT_BSS_IS_INFRA 17
|
||||
#define DC_PS_ENABLED_BUT_ATHEROS_IE_ABSENT 18
|
||||
#define DC_BSS_ADHOC_CHANNEL_NOT_ALLOWED 19
|
||||
#define DC_SET_BEACON_UPDATE 20
|
||||
#define DC_BEACON_UPDATE_COMPLETE 21
|
||||
#define DC_END_SEARCH_BEACON_UPDATE_COMP_CB 22
|
||||
#define DC_BSSINFO_EVENT_DROPPED 23
|
||||
#define DC_IEEEPS_ENABLED_BUT_ATIM_ABSENT 24
|
||||
#define DC_DBGID_DEFINITION_END
|
||||
|
||||
/* CO debug identifier definitions */
|
||||
#define CO_DBGID_DEFINITION_START
|
||||
#define CO_INIT 1
|
||||
#define CO_ACQUIRE_LOCK 2
|
||||
#define CO_START_OP1 3
|
||||
#define CO_START_OP2 4
|
||||
#define CO_DRAIN_TX_COMPLETE_CB 5
|
||||
#define CO_CHANGE_CHANNEL_CB 6
|
||||
#define CO_RETURN_TO_HOME_CHANNEL 7
|
||||
#define CO_FINISH_OP_TIMEOUT 8
|
||||
#define CO_OP_END 9
|
||||
#define CO_CANCEL_OP 10
|
||||
#define CO_CHANGE_CHANNEL 11
|
||||
#define CO_RELEASE_LOCK 12
|
||||
#define CO_CHANGE_STATE 13
|
||||
#define CO_DBGID_DEFINITION_END
|
||||
|
||||
/* RO debug identifier definitions */
|
||||
#define RO_DBGID_DEFINITION_START
|
||||
#define RO_REFRESH_ROAM_TABLE 1
|
||||
#define RO_UPDATE_ROAM_CANDIDATE 2
|
||||
#define RO_UPDATE_ROAM_CANDIDATE_CB 3
|
||||
#define RO_UPDATE_ROAM_CANDIDATE_FINISH 4
|
||||
#define RO_REFRESH_ROAM_TABLE_DONE 5
|
||||
#define RO_PERIODIC_SEARCH_CB 6
|
||||
#define RO_PERIODIC_SEARCH_TIMEOUT 7
|
||||
#define RO_INIT 8
|
||||
#define RO_BMISS_STATE1 9
|
||||
#define RO_BMISS_STATE2 10
|
||||
#define RO_SET_PERIODIC_SEARCH_ENABLE 11
|
||||
#define RO_SET_PERIODIC_SEARCH_DISABLE 12
|
||||
#define RO_ENABLE_SQ_THRESHOLD 13
|
||||
#define RO_DISABLE_SQ_THRESHOLD 14
|
||||
#define RO_ADD_BSS_TO_ROAM_TABLE 15
|
||||
#define RO_SET_PERIODIC_SEARCH_MODE 16
|
||||
#define RO_CONFIGURE_SQ_THRESHOLD1 17
|
||||
#define RO_CONFIGURE_SQ_THRESHOLD2 18
|
||||
#define RO_CONFIGURE_SQ_PARAMS 19
|
||||
#define RO_LOW_SIGNAL_QUALITY_EVENT 20
|
||||
#define RO_HIGH_SIGNAL_QUALITY_EVENT 21
|
||||
#define RO_REMOVE_BSS_FROM_ROAM_TABLE 22
|
||||
#define RO_UPDATE_CONNECTION_STATE_METRIC 23
|
||||
#define RO_DBGID_DEFINITION_END
|
||||
|
||||
/* CM debug identifier definitions */
|
||||
#define CM_DBGID_DEFINITION_START
|
||||
#define CM_INITIATE_HANDOFF 1
|
||||
#define CM_INITIATE_HANDOFF_CB 2
|
||||
#define CM_CONNECT_EVENT 3
|
||||
#define CM_DISCONNECT_EVENT 4
|
||||
#define CM_INIT 5
|
||||
#define CM_HANDOFF_SOURCE 6
|
||||
#define CM_SET_HANDOFF_TRIGGERS 7
|
||||
#define CM_CONNECT_REQUEST 8
|
||||
#define CM_CONNECT_REQUEST_CB 9
|
||||
#define CM_CONTINUE_SCAN_CB 10
|
||||
#define CM_DBGID_DEFINITION_END
|
||||
|
||||
|
||||
/* mgmt debug identifier definitions */
|
||||
#define MGMT_DBGID_DEFINITION_START
|
||||
#define KEYMGMT_CONNECTION_INIT 1
|
||||
#define KEYMGMT_CONNECTION_COMPLETE 2
|
||||
#define KEYMGMT_CONNECTION_CLOSE 3
|
||||
#define KEYMGMT_ADD_KEY 4
|
||||
#define MLME_NEW_STATE 5
|
||||
#define MLME_CONN_INIT 6
|
||||
#define MLME_CONN_COMPLETE 7
|
||||
#define MLME_CONN_CLOSE 8
|
||||
#define MGMT_DBGID_DEFINITION_END
|
||||
|
||||
/* TMR debug identifier definitions */
|
||||
#define TMR_DBGID_DEFINITION_START
|
||||
#define TMR_HANG_DETECTED 1
|
||||
#define TMR_WDT_TRIGGERED 2
|
||||
#define TMR_WDT_RESET 3
|
||||
#define TMR_HANDLER_ENTRY 4
|
||||
#define TMR_HANDLER_EXIT 5
|
||||
#define TMR_SAVED_START 6
|
||||
#define TMR_SAVED_END 7
|
||||
#define TMR_DBGID_DEFINITION_END
|
||||
|
||||
/* BTCOEX debug identifier definitions */
|
||||
#define BTCOEX_DBGID_DEFINITION_START
|
||||
#define BTCOEX_STATUS_CMD 1
|
||||
#define BTCOEX_PARAMS_CMD 2
|
||||
#define BTCOEX_ANT_CONFIG 3
|
||||
#define BTCOEX_COLOCATED_BT_DEVICE 4
|
||||
#define BTCOEX_CLOSE_RANGE_SCO_ON 5
|
||||
#define BTCOEX_CLOSE_RANGE_SCO_OFF 6
|
||||
#define BTCOEX_CLOSE_RANGE_A2DP_ON 7
|
||||
#define BTCOEX_CLOSE_RANGE_A2DP_OFF 8
|
||||
#define BTCOEX_A2DP_PROTECT_ON 9
|
||||
#define BTCOEX_A2DP_PROTECT_OFF 10
|
||||
#define BTCOEX_SCO_PROTECT_ON 11
|
||||
#define BTCOEX_SCO_PROTECT_OFF 12
|
||||
#define BTCOEX_CLOSE_RANGE_DETECTOR_START 13
|
||||
#define BTCOEX_CLOSE_RANGE_DETECTOR_STOP 14
|
||||
#define BTCOEX_CLOSE_RANGE_TOGGLE 15
|
||||
#define BTCOEX_CLOSE_RANGE_TOGGLE_RSSI_LRCNT 16
|
||||
#define BTCOEX_CLOSE_RANGE_RSSI_THRESH 17
|
||||
#define BTCOEX_CLOSE_RANGE_LOW_RATE_THRESH 18
|
||||
#define BTCOEX_PTA_PRI_INTR_HANDLER 19
|
||||
#define BTCOEX_PSPOLL_QUEUED 20
|
||||
#define BTCOEX_PSPOLL_COMPLETE 21
|
||||
#define BTCOEX_DBG_PM_AWAKE 22
|
||||
#define BTCOEX_DBG_PM_SLEEP 23
|
||||
#define BTCOEX_DBG_SCO_COEX_ON 24
|
||||
#define BTCOEX_SCO_DATARECEIVE 25
|
||||
#define BTCOEX_INTR_INIT 26
|
||||
#define BTCOEX_PTA_PRI_DIFF 27
|
||||
#define BTCOEX_TIM_NOTIFICATION 28
|
||||
#define BTCOEX_SCO_WAKEUP_ON_DATA 29
|
||||
#define BTCOEX_SCO_SLEEP 30
|
||||
#define BTCOEX_SET_WEIGHTS 31
|
||||
#define BTCOEX_SCO_DATARECEIVE_LATENCY_VAL 32
|
||||
#define BTCOEX_SCO_MEASURE_TIME_DIFF 33
|
||||
#define BTCOEX_SET_EOL_VAL 34
|
||||
#define BTCOEX_OPT_DETECT_HANDLER 35
|
||||
#define BTCOEX_SCO_TOGGLE_STATE 36
|
||||
#define BTCOEX_SCO_STOMP 37
|
||||
#define BTCOEX_NULL_COMP_CALLBACK 38
|
||||
#define BTCOEX_RX_INCOMING 39
|
||||
#define BTCOEX_RX_INCOMING_CTL 40
|
||||
#define BTCOEX_RX_INCOMING_MGMT 41
|
||||
#define BTCOEX_RX_INCOMING_DATA 42
|
||||
#define BTCOEX_RTS_RECEPTION 43
|
||||
#define BTCOEX_FRAME_PRI_LOW_RATE_THRES 44
|
||||
#define BTCOEX_PM_FAKE_SLEEP 45
|
||||
#define BTCOEX_ACL_COEX_STATUS 46
|
||||
#define BTCOEX_ACL_COEX_DETECTION 47
|
||||
#define BTCOEX_A2DP_COEX_STATUS 48
|
||||
#define BTCOEX_SCO_STATUS 49
|
||||
#define BTCOEX_WAKEUP_ON_DATA 50
|
||||
#define BTCOEX_DATARECEIVE 51
|
||||
#define BTCOEX_GET_MAX_AGGR_SIZE 53
|
||||
#define BTCOEX_MAX_AGGR_AVAIL_TIME 54
|
||||
#define BTCOEX_DBG_WBTIMER_INTR 55
|
||||
#define BTCOEX_DBG_SCO_SYNC 57
|
||||
#define BTCOEX_UPLINK_QUEUED_RATE 59
|
||||
#define BTCOEX_DBG_UPLINK_ENABLE_EOL 60
|
||||
#define BTCOEX_UPLINK_FRAME_DURATION 61
|
||||
#define BTCOEX_UPLINK_SET_EOL 62
|
||||
#define BTCOEX_DBG_EOL_EXPIRED 63
|
||||
#define BTCOEX_DBG_DATA_COMPLETE 64
|
||||
#define BTCOEX_UPLINK_QUEUED_TIMESTAMP 65
|
||||
#define BTCOEX_DBG_DATA_COMPLETE_TIME 66
|
||||
#define BTCOEX_DBG_A2DP_ROLE_IS_SLAVE 67
|
||||
#define BTCOEX_DBG_A2DP_ROLE_IS_MASTER 68
|
||||
#define BTCOEX_DBG_UPLINK_SEQ_NUM 69
|
||||
#define BTCOEX_UPLINK_AGGR_SEQ 70
|
||||
#define BTCOEX_DBG_TX_COMP_SEQ_NO 71
|
||||
#define BTCOEX_DBG_MAX_AGGR_PAUSE_STATE 72
|
||||
#define BTCOEX_DBG_ACL_TRAFFIC 73
|
||||
#define BTCOEX_CURR_AGGR_PROP 74
|
||||
#define BTCOEX_DBG_SCO_GET_PER_TIME_DIFF 75
|
||||
#define BTCOEX_PSPOLL_PROCESS 76
|
||||
#define BTCOEX_RETURN_FROM_MAC 77
|
||||
#define BTCOEX_FREED_REQUEUED_CNT 78
|
||||
#define BTCOEX_DBG_TOGGLE_LOW_RATES 79
|
||||
#define BTCOEX_MAC_GOES_TO_SLEEP 80
|
||||
#define BTCOEX_DBG_A2DP_NO_SYNC 81
|
||||
#define BTCOEX_RETURN_FROM_MAC_HOLD_Q_INFO 82
|
||||
#define BTCOEX_RETURN_FROM_MAC_AC 83
|
||||
#define BTCOEX_DBG_DTIM_RECV 84
|
||||
#define BTCOEX_IS_PRE_UPDATE 86
|
||||
#define BTCOEX_ENQUEUED_BIT_MAP 87
|
||||
#define BTCOEX_TX_COMPLETE_FIRST_DESC_STATS 88
|
||||
#define BTCOEX_UPLINK_DESC 89
|
||||
#define BTCOEX_SCO_GET_PER_FIRST_FRM_TIMESTAMP 90
|
||||
#define BTCOEX_DBG_RECV_ACK 94
|
||||
#define BTCOEX_DBG_ADDBA_INDICATION 95
|
||||
#define BTCOEX_TX_COMPLETE_EOL_FAILED 96
|
||||
#define BTCOEX_DBG_A2DP_USAGE_COMPLETE 97
|
||||
#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_HANDLER 98
|
||||
#define BTCOEX_DBG_A2DP_SYNC_INTR 99
|
||||
#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_RECEPTION 100
|
||||
#define BTCOEX_FORM_AGGR_CURR_AGGR 101
|
||||
#define BTCOEX_DBG_TOGGLE_A2DP_BURST_CNT 102
|
||||
#define BTCOEX_DBG_BT_TRAFFIC 103
|
||||
#define BTCOEX_DBG_STOMP_BT_TRAFFIC 104
|
||||
#define BTCOEX_RECV_NULL 105
|
||||
#define BTCOEX_DBG_A2DP_MASTER_BT_END 106
|
||||
#define BTCOEX_DBG_A2DP_BT_START 107
|
||||
#define BTCOEX_DBG_A2DP_SLAVE_BT_END 108
|
||||
#define BTCOEX_DBG_A2DP_STOMP_BT 109
|
||||
#define BTCOEX_DBG_GO_TO_SLEEP 110
|
||||
#define BTCOEX_DBG_A2DP_PKT 111
|
||||
#define BTCOEX_DBG_A2DP_PSPOLL_DATA_RECV 112
|
||||
#define BTCOEX_DBG_A2DP_NULL 113
|
||||
#define BTCOEX_DBG_UPLINK_DATA 114
|
||||
#define BTCOEX_DBG_A2DP_STOMP_LOW_PRIO_NULL 115
|
||||
#define BTCOEX_DBG_ADD_BA_RESP_TIMEOUT 116
|
||||
#define BTCOEX_DBG_TXQ_STATE 117
|
||||
#define BTCOEX_DBG_ALLOW_SCAN 118
|
||||
#define BTCOEX_DBG_SCAN_REQUEST 119
|
||||
#define BTCOEX_A2DP_SLEEP 127
|
||||
#define BTCOEX_DBG_DATA_ACTIV_TIMEOUT 128
|
||||
#define BTCOEX_DBG_SWITCH_TO_PSPOLL_ON_MODE 129
|
||||
#define BTCOEX_DBG_SWITCH_TO_PSPOLL_OFF_MODE 130
|
||||
#define BTCOEX_DATARECEIVE_AGGR 131
|
||||
#define BTCOEX_DBG_DATA_RECV_SLEEPING_PENDING 132
|
||||
#define BTCOEX_DBG_DATARESP_TIMEOUT 133
|
||||
#define BTCOEX_BDG_BMISS 134
|
||||
#define BTCOEX_DBG_DATA_RECV_WAKEUP_TIM 135
|
||||
#define BTCOEX_DBG_SECOND_BMISS 136
|
||||
#define BTCOEX_DBG_SET_WLAN_STATE 138
|
||||
#define BTCOEX_BDG_FIRST_BMISS 139
|
||||
#define BTCOEX_DBG_A2DP_CHAN_OP 140
|
||||
#define BTCOEX_DBG_A2DP_INTR 141
|
||||
#define BTCOEX_DBG_BT_INQUIRY 142
|
||||
#define BTCOEX_DBG_BT_INQUIRY_DATA_FETCH 143
|
||||
#define BTCOEX_DBG_POST_INQUIRY_FINISH 144
|
||||
#define BTCOEX_DBG_SCO_OPT_MODE_TIMER_HANDLER 145
|
||||
#define BTCOEX_DBG_NULL_FRAME_SLEEP 146
|
||||
#define BTCOEX_DBG_NULL_FRAME_AWAKE 147
|
||||
#define BTCOEX_DBG_SET_AGGR_SIZE 152
|
||||
#define BTCOEX_DBG_TEAR_BA_TIMEOUT 153
|
||||
#define BTCOEX_DBG_MGMT_FRAME_SEQ_NO 154
|
||||
#define BTCOEX_DBG_SCO_STOMP_HIGH_PRI 155
|
||||
#define BTCOEX_DBG_COLOCATED_BT_DEV 156
|
||||
#define BTCOEX_DBG_FE_ANT_TYPE 157
|
||||
#define BTCOEX_DBG_BT_INQUIRY_CMD 158
|
||||
#define BTCOEX_DBG_SCO_CONFIG 159
|
||||
#define BTCOEX_DBG_SCO_PSPOLL_CONFIG 160
|
||||
#define BTCOEX_DBG_SCO_OPTMODE_CONFIG 161
|
||||
#define BTCOEX_DBG_A2DP_CONFIG 162
|
||||
#define BTCOEX_DBG_A2DP_PSPOLL_CONFIG 163
|
||||
#define BTCOEX_DBG_A2DP_OPTMODE_CONFIG 164
|
||||
#define BTCOEX_DBG_ACLCOEX_CONFIG 165
|
||||
#define BTCOEX_DBG_ACLCOEX_PSPOLL_CONFIG 166
|
||||
#define BTCOEX_DBG_ACLCOEX_OPTMODE_CONFIG 167
|
||||
#define BTCOEX_DBG_DEBUG_CMD 168
|
||||
#define BTCOEX_DBG_SET_BT_OPERATING_STATUS 169
|
||||
#define BTCOEX_DBG_GET_CONFIG 170
|
||||
#define BTCOEX_DBG_GET_STATS 171
|
||||
#define BTCOEX_DBG_BT_OPERATING_STATUS 172
|
||||
#define BTCOEX_DBG_PERFORM_RECONNECT 173
|
||||
#define BTCOEX_DBG_ACL_WLAN_MED 175
|
||||
#define BTCOEX_DBG_ACL_BT_MED 176
|
||||
#define BTCOEX_DBG_WLAN_CONNECT 177
|
||||
#define BTCOEX_DBG_A2DP_DUAL_START 178
|
||||
#define BTCOEX_DBG_PMAWAKE_NOTIFY 179
|
||||
#define BTCOEX_DBG_BEACON_SCAN_ENABLE 180
|
||||
#define BTCOEX_DBG_BEACON_SCAN_DISABLE 181
|
||||
#define BTCOEX_DBG_RX_NOTIFY 182
|
||||
#define BTCOEX_SCO_GET_PER_SECOND_FRM_TIMESTAMP 183
|
||||
#define BTCOEX_DBG_TXQ_DETAILS 184
|
||||
#define BTCOEX_DBG_SCO_STOMP_LOW_PRI 185
|
||||
#define BTCOEX_DBG_A2DP_FORCE_SCAN 186
|
||||
#define BTCOEX_DBG_DTIM_STOMP_COMP 187
|
||||
#define BTCOEX_ACL_PRESENCE_TIMER 188
|
||||
#define BTCOEX_DBGID_DEFINITION_END
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DBGLOG_ID_H_ */
|
|
@ -1,75 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="discovery.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef _DISCOVERY_H_
|
||||
#define _DISCOVERY_H_
|
||||
|
||||
/*
|
||||
* DC_SCAN_PRIORITY is an 8-bit bitmap of the scan priority of a channel
|
||||
*/
|
||||
typedef enum {
|
||||
DEFAULT_SCPRI = 0x01,
|
||||
POPULAR_SCPRI = 0x02,
|
||||
SSIDS_SCPRI = 0x04,
|
||||
PROF_SCPRI = 0x08,
|
||||
} DC_SCAN_PRIORITY;
|
||||
|
||||
/* The following search type construct can be used to manipulate the behavior of the search module based on different bits set */
|
||||
typedef enum {
|
||||
SCAN_RESET = 0,
|
||||
SCAN_ALL = (DEFAULT_SCPRI | POPULAR_SCPRI | \
|
||||
SSIDS_SCPRI | PROF_SCPRI),
|
||||
|
||||
SCAN_POPULAR = (POPULAR_SCPRI | SSIDS_SCPRI | PROF_SCPRI),
|
||||
SCAN_SSIDS = (SSIDS_SCPRI | PROF_SCPRI),
|
||||
SCAN_PROF_MASK = (PROF_SCPRI),
|
||||
SCAN_MULTI_CHANNEL = 0x000100,
|
||||
SCAN_DETERMINISTIC = 0x000200,
|
||||
SCAN_PROFILE_MATCH_TERMINATED = 0x000400,
|
||||
SCAN_HOME_CHANNEL_SKIP = 0x000800,
|
||||
SCAN_CHANNEL_LIST_CONTINUE = 0x001000,
|
||||
SCAN_CURRENT_SSID_SKIP = 0x002000,
|
||||
SCAN_ACTIVE_PROBE_DISABLE = 0x004000,
|
||||
SCAN_CHANNEL_HINT_ONLY = 0x008000,
|
||||
SCAN_ACTIVE_CHANNELS_ONLY = 0x010000,
|
||||
SCAN_UNUSED1 = 0x020000, /* unused */
|
||||
SCAN_PERIODIC = 0x040000,
|
||||
SCAN_FIXED_DURATION = 0x080000,
|
||||
SCAN_AP_ASSISTED = 0x100000,
|
||||
} DC_SCAN_TYPE;
|
||||
|
||||
typedef enum {
|
||||
BSS_REPORTING_DEFAULT = 0x0,
|
||||
EXCLUDE_NON_SCAN_RESULTS = 0x1, /* Exclude results outside of scan */
|
||||
} DC_BSS_REPORTING_POLICY;
|
||||
|
||||
typedef enum {
|
||||
DC_IGNORE_WPAx_GROUP_CIPHER = 0x01,
|
||||
DC_PROFILE_MATCH_DONE = 0x02,
|
||||
DC_IGNORE_AAC_BEACON = 0x04,
|
||||
DC_CSA_FOLLOW_BSS = 0x08,
|
||||
} DC_PROFILE_FILTER;
|
||||
|
||||
#define DEFAULT_DC_PROFILE_FILTER (DC_CSA_FOLLOW_BSS)
|
||||
|
||||
#endif /* _DISCOVERY_H_ */
|
|
@ -1,111 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//
|
||||
|
||||
/* This file contains shared definitions for the host/target endpoint ping test */
|
||||
|
||||
#ifndef EPPING_TEST_H_
|
||||
#define EPPING_TEST_H_
|
||||
|
||||
/* alignment to 4-bytes */
|
||||
#define EPPING_ALIGNMENT_PAD (((sizeof(struct htc_frame_hdr) + 3) & (~0x3)) - sizeof(struct htc_frame_hdr))
|
||||
|
||||
#ifndef A_OFFSETOF
|
||||
#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
|
||||
#endif
|
||||
|
||||
#define EPPING_RSVD_FILL 0xCC
|
||||
|
||||
#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET 7
|
||||
|
||||
typedef PREPACK struct {
|
||||
u8 _HCIRsvd[8]; /* reserved for HCI packet header (GMBOX) testing */
|
||||
u8 StreamEcho_h; /* stream no. to echo this packet on (filled by host) */
|
||||
u8 StreamEchoSent_t; /* stream no. packet was echoed to (filled by target)
|
||||
When echoed: StreamEchoSent_t == StreamEcho_h */
|
||||
u8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */
|
||||
u8 StreamNo_h; /* stream number to send on (filled by host) */
|
||||
u8 Magic_h[4]; /* magic number to filter for this packet on the host*/
|
||||
u8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value
|
||||
since this packet maps to a 14-byte ethernet frame we want
|
||||
to make sure ethertype field is set to something unknown */
|
||||
|
||||
u8 _pad[2]; /* padding for alignment */
|
||||
u8 TimeStamp[8]; /* timestamp of packet (host or target) */
|
||||
u32 HostContext_h; /* 4 byte host context, target echos this back */
|
||||
u32 SeqNo; /* sequence number (set by host or target) */
|
||||
u16 Cmd_h; /* ping command (filled by host) */
|
||||
u16 CmdFlags_h; /* optional flags */
|
||||
u8 CmdBuffer_h[8]; /* buffer for command (host -> target) */
|
||||
u8 CmdBuffer_t[8]; /* buffer for command (target -> host) */
|
||||
u16 DataLength; /* length of data */
|
||||
u16 DataCRC; /* 16 bit CRC of data */
|
||||
u16 HeaderCRC; /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */
|
||||
} POSTPACK EPPING_HEADER;
|
||||
|
||||
#define EPPING_PING_MAGIC_0 0xAA
|
||||
#define EPPING_PING_MAGIC_1 0x55
|
||||
#define EPPING_PING_MAGIC_2 0xCE
|
||||
#define EPPING_PING_MAGIC_3 0xEC
|
||||
|
||||
|
||||
|
||||
#define IS_EPPING_PACKET(pPkt) (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \
|
||||
((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \
|
||||
((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \
|
||||
((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3))
|
||||
|
||||
#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \
|
||||
(pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \
|
||||
(pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \
|
||||
(pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3;}
|
||||
|
||||
#define CMD_FLAGS_DATA_CRC (1 << 0) /* DataCRC field is valid */
|
||||
#define CMD_FLAGS_DELAY_ECHO (1 << 1) /* delay the echo of the packet */
|
||||
#define CMD_FLAGS_NO_DROP (1 << 2) /* do not drop at HTC layer no matter what the stream is */
|
||||
|
||||
#define IS_EPING_PACKET_NO_DROP(pPkt) ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP)
|
||||
|
||||
#define EPPING_CMD_ECHO_PACKET 1 /* echo packet test */
|
||||
#define EPPING_CMD_RESET_RECV_CNT 2 /* reset recv count */
|
||||
#define EPPING_CMD_CAPTURE_RECV_CNT 3 /* fetch recv count, 4-byte count returned in CmdBuffer_t */
|
||||
#define EPPING_CMD_NO_ECHO 4 /* non-echo packet test (tx-only) */
|
||||
#define EPPING_CMD_CONT_RX_START 5 /* continuous RX packets, parameters are in CmdBuffer_h */
|
||||
#define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */
|
||||
|
||||
/* test command parameters may be no more than 8 bytes */
|
||||
typedef PREPACK struct {
|
||||
u16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */
|
||||
u16 PacketLength; /* length of packet to generate including header */
|
||||
u16 Flags; /* flags */
|
||||
|
||||
#define EPPING_CONT_RX_DATA_CRC (1 << 0) /* Add CRC to all data */
|
||||
#define EPPING_CONT_RX_RANDOM_DATA (1 << 1) /* randomize the data pattern */
|
||||
#define EPPING_CONT_RX_RANDOM_LEN (1 << 2) /* randomize the packet lengths */
|
||||
} POSTPACK EPPING_CONT_RX_PARAMS;
|
||||
|
||||
#define EPPING_HDR_CRC_OFFSET A_OFFSETOF(EPPING_HEADER,StreamNo_h)
|
||||
#define EPPING_HDR_BYTES_CRC (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(u16)))
|
||||
|
||||
#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we
|
||||
can use this to distinguish packets */
|
||||
|
||||
#endif /*EPPING_TEST_H_*/
|
|
@ -1,70 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef __GMBOXIF_H__
|
||||
#define __GMBOXIF_H__
|
||||
|
||||
/* GMBOX interface definitions */
|
||||
|
||||
#define AR6K_GMBOX_CREDIT_COUNTER 1 /* we use credit counter 1 to track credits */
|
||||
#define AR6K_GMBOX_CREDIT_SIZE_COUNTER 2 /* credit counter 2 is used to pass the size of each credit */
|
||||
|
||||
|
||||
/* HCI UART transport definitions when used over GMBOX interface */
|
||||
#define HCI_UART_COMMAND_PKT 0x01
|
||||
#define HCI_UART_ACL_PKT 0x02
|
||||
#define HCI_UART_SCO_PKT 0x03
|
||||
#define HCI_UART_EVENT_PKT 0x04
|
||||
|
||||
/* definitions for BT HCI packets */
|
||||
typedef PREPACK struct {
|
||||
u16 Flags_ConnHandle;
|
||||
u16 Length;
|
||||
} POSTPACK BT_HCI_ACL_HEADER;
|
||||
|
||||
typedef PREPACK struct {
|
||||
u16 Flags_ConnHandle;
|
||||
u8 Length;
|
||||
} POSTPACK BT_HCI_SCO_HEADER;
|
||||
|
||||
typedef PREPACK struct {
|
||||
u16 OpCode;
|
||||
u8 ParamLength;
|
||||
} POSTPACK BT_HCI_COMMAND_HEADER;
|
||||
|
||||
typedef PREPACK struct {
|
||||
u8 EventCode;
|
||||
u8 ParamLength;
|
||||
} POSTPACK BT_HCI_EVENT_HEADER;
|
||||
|
||||
/* MBOX host interrupt signal assignments */
|
||||
|
||||
#define MBOX_SIG_HCI_BRIDGE_MAX 8
|
||||
#define MBOX_SIG_HCI_BRIDGE_BT_ON 0
|
||||
#define MBOX_SIG_HCI_BRIDGE_BT_OFF 1
|
||||
#define MBOX_SIG_HCI_BRIDGE_BAUD_SET 2
|
||||
#define MBOX_SIG_HCI_BRIDGE_PWR_SAV_ON 3
|
||||
#define MBOX_SIG_HCI_BRIDGE_PWR_SAV_OFF 4
|
||||
|
||||
|
||||
#endif /* __GMBOXIF_H__ */
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
#ifndef _GPIO_REG_REG_H_
|
||||
#define _GPIO_REG_REG_H_
|
||||
|
||||
#define GPIO_PIN10_ADDRESS 0x00000050
|
||||
#define GPIO_PIN11_ADDRESS 0x00000054
|
||||
#define GPIO_PIN12_ADDRESS 0x00000058
|
||||
#define GPIO_PIN13_ADDRESS 0x0000005c
|
||||
|
||||
#endif /* _GPIO_REG_H_ */
|
|
@ -1,227 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="htc.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef __HTC_H__
|
||||
#define __HTC_H__
|
||||
|
||||
#define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field))
|
||||
|
||||
#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
|
||||
(((u16)(((u8 *)(p))[(highbyte)])) << 8 | (u16)(((u8 *)(p))[(lowbyte)]))
|
||||
|
||||
/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a
|
||||
* structure using only the type and field name.
|
||||
* Use these macros if there is the potential for unaligned buffer accesses. */
|
||||
#define A_GET_UINT16_FIELD(p,type,field) \
|
||||
ASSEMBLE_UNALIGNED_UINT16(p,\
|
||||
A_OFFSETOF(type,field) + 1, \
|
||||
A_OFFSETOF(type,field))
|
||||
|
||||
#define A_SET_UINT16_FIELD(p,type,field,value) \
|
||||
{ \
|
||||
((u8 *)(p))[A_OFFSETOF(type,field)] = (u8)(value); \
|
||||
((u8 *)(p))[A_OFFSETOF(type,field) + 1] = (u8)((value) >> 8); \
|
||||
}
|
||||
|
||||
#define A_GET_UINT8_FIELD(p,type,field) \
|
||||
((u8 *)(p))[A_OFFSETOF(type,field)]
|
||||
|
||||
#define A_SET_UINT8_FIELD(p,type,field,value) \
|
||||
((u8 *)(p))[A_OFFSETOF(type,field)] = (value)
|
||||
|
||||
/****** DANGER DANGER ***************
|
||||
*
|
||||
* The frame header length and message formats defined herein were
|
||||
* selected to accommodate optimal alignment for target processing. This reduces code
|
||||
* size and improves performance.
|
||||
*
|
||||
* Any changes to the header length may alter the alignment and cause exceptions
|
||||
* on the target. When adding to the message structures insure that fields are
|
||||
* properly aligned.
|
||||
*
|
||||
*/
|
||||
|
||||
/* HTC frame header */
|
||||
PREPACK struct htc_frame_hdr {
|
||||
/* do not remove or re-arrange these fields, these are minimally required
|
||||
* to take advantage of 4-byte lookaheads in some hardware implementations */
|
||||
u8 EndpointID;
|
||||
u8 Flags;
|
||||
u16 PayloadLen; /* length of data (including trailer) that follows the header */
|
||||
|
||||
/***** end of 4-byte lookahead ****/
|
||||
|
||||
u8 ControlBytes[2];
|
||||
|
||||
/* message payload starts after the header */
|
||||
|
||||
} POSTPACK;
|
||||
|
||||
/* frame header flags */
|
||||
|
||||
/* send direction */
|
||||
#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
|
||||
#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */
|
||||
/* receive direction */
|
||||
#define HTC_FLAGS_RECV_UNUSED_0 (1 << 0) /* bit 0 unused */
|
||||
#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */
|
||||
#define HTC_FLAGS_RECV_UNUSED_2 (1 << 0) /* bit 2 unused */
|
||||
#define HTC_FLAGS_RECV_UNUSED_3 (1 << 0) /* bit 3 unused */
|
||||
#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xF0) /* bits 7..4 */
|
||||
#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 4
|
||||
|
||||
#define HTC_HDR_LENGTH (sizeof(struct htc_frame_hdr))
|
||||
#define HTC_MAX_TRAILER_LENGTH 255
|
||||
#define HTC_MAX_PAYLOAD_LENGTH (4096 - sizeof(struct htc_frame_hdr))
|
||||
|
||||
/* HTC control message IDs */
|
||||
|
||||
#define HTC_MSG_READY_ID 1
|
||||
#define HTC_MSG_CONNECT_SERVICE_ID 2
|
||||
#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3
|
||||
#define HTC_MSG_SETUP_COMPLETE_ID 4
|
||||
#define HTC_MSG_SETUP_COMPLETE_EX_ID 5
|
||||
|
||||
#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256
|
||||
|
||||
/* base message ID header */
|
||||
typedef PREPACK struct {
|
||||
u16 MessageID;
|
||||
} POSTPACK HTC_UNKNOWN_MSG;
|
||||
|
||||
/* HTC ready message
|
||||
* direction : target-to-host */
|
||||
typedef PREPACK struct {
|
||||
u16 MessageID; /* ID */
|
||||
u16 CreditCount; /* number of credits the target can offer */
|
||||
u16 CreditSize; /* size of each credit */
|
||||
u8 MaxEndpoints; /* maximum number of endpoints the target has resources for */
|
||||
u8 _Pad1;
|
||||
} POSTPACK HTC_READY_MSG;
|
||||
|
||||
/* extended HTC ready message */
|
||||
typedef PREPACK struct {
|
||||
HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */
|
||||
/* extended information */
|
||||
u8 HTCVersion;
|
||||
u8 MaxMsgsPerHTCBundle;
|
||||
} POSTPACK HTC_READY_EX_MSG;
|
||||
|
||||
#define HTC_VERSION_2P0 0x00
|
||||
#define HTC_VERSION_2P1 0x01 /* HTC 2.1 */
|
||||
|
||||
#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
|
||||
|
||||
/* connect service
|
||||
* direction : host-to-target */
|
||||
typedef PREPACK struct {
|
||||
u16 MessageID;
|
||||
u16 ServiceID; /* service ID of the service to connect to */
|
||||
u16 ConnectionFlags; /* connection flags */
|
||||
|
||||
#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when
|
||||
the host needs credits */
|
||||
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3)
|
||||
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0
|
||||
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1
|
||||
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2
|
||||
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3
|
||||
|
||||
u8 ServiceMetaLength; /* length of meta data that follows */
|
||||
u8 _Pad1;
|
||||
|
||||
/* service-specific meta data starts after the header */
|
||||
|
||||
} POSTPACK HTC_CONNECT_SERVICE_MSG;
|
||||
|
||||
/* connect response
|
||||
* direction : target-to-host */
|
||||
typedef PREPACK struct {
|
||||
u16 MessageID;
|
||||
u16 ServiceID; /* service ID that the connection request was made */
|
||||
u8 Status; /* service connection status */
|
||||
u8 EndpointID; /* assigned endpoint ID */
|
||||
u16 MaxMsgSize; /* maximum expected message size on this endpoint */
|
||||
u8 ServiceMetaLength; /* length of meta data that follows */
|
||||
u8 _Pad1;
|
||||
|
||||
/* service-specific meta data starts after the header */
|
||||
|
||||
} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
|
||||
|
||||
typedef PREPACK struct {
|
||||
u16 MessageID;
|
||||
/* currently, no other fields */
|
||||
} POSTPACK HTC_SETUP_COMPLETE_MSG;
|
||||
|
||||
/* extended setup completion message */
|
||||
typedef PREPACK struct {
|
||||
u16 MessageID;
|
||||
u32 SetupFlags;
|
||||
u8 MaxMsgsPerBundledRecv;
|
||||
u8 Rsvd[3];
|
||||
} POSTPACK HTC_SETUP_COMPLETE_EX_MSG;
|
||||
|
||||
#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0)
|
||||
|
||||
/* connect response status codes */
|
||||
#define HTC_SERVICE_SUCCESS 0 /* success */
|
||||
#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */
|
||||
#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */
|
||||
#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */
|
||||
#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more
|
||||
endpoints */
|
||||
|
||||
/* report record IDs */
|
||||
|
||||
#define HTC_RECORD_NULL 0
|
||||
#define HTC_RECORD_CREDITS 1
|
||||
#define HTC_RECORD_LOOKAHEAD 2
|
||||
#define HTC_RECORD_LOOKAHEAD_BUNDLE 3
|
||||
|
||||
typedef PREPACK struct {
|
||||
u8 RecordID; /* Record ID */
|
||||
u8 Length; /* Length of record */
|
||||
} POSTPACK HTC_RECORD_HDR;
|
||||
|
||||
typedef PREPACK struct {
|
||||
u8 EndpointID; /* Endpoint that owns these credits */
|
||||
u8 Credits; /* credits to report since last report */
|
||||
} POSTPACK HTC_CREDIT_REPORT;
|
||||
|
||||
typedef PREPACK struct {
|
||||
u8 PreValid; /* pre valid guard */
|
||||
u8 LookAhead[4]; /* 4 byte lookahead */
|
||||
u8 PostValid; /* post valid guard */
|
||||
|
||||
/* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
|
||||
* The PreValid bytes must equal the inverse of the PostValid byte */
|
||||
|
||||
} POSTPACK HTC_LOOKAHEAD_REPORT;
|
||||
|
||||
typedef PREPACK struct {
|
||||
u8 LookAhead[4]; /* 4 byte lookahead */
|
||||
} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
|
||||
|
||||
#endif /* __HTC_H__ */
|
||||
|
|
@ -1,52 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="htc_services.h" company="Atheros">
|
||||
// Copyright (c) 2007 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef __HTC_SERVICES_H__
|
||||
#define __HTC_SERVICES_H__
|
||||
|
||||
/* Current service IDs */
|
||||
|
||||
typedef enum {
|
||||
RSVD_SERVICE_GROUP = 0,
|
||||
WMI_SERVICE_GROUP = 1,
|
||||
|
||||
HTC_TEST_GROUP = 254,
|
||||
HTC_SERVICE_GROUP_LAST = 255
|
||||
}HTC_SERVICE_GROUP_IDS;
|
||||
|
||||
#define MAKE_SERVICE_ID(group,index) \
|
||||
(int)(((int)group << 8) | (int)(index))
|
||||
|
||||
/* NOTE: service ID of 0x0000 is reserved and should never be used */
|
||||
#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
|
||||
#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
|
||||
#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
|
||||
#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
|
||||
#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
|
||||
#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
|
||||
#define WMI_MAX_SERVICES 5
|
||||
|
||||
/* raw stream service (i.e. flash, tcmd, calibration apps) */
|
||||
#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
|
||||
|
||||
#endif /*HTC_SERVICES_H_*/
|
|
@ -1,45 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef __PKT_LOG_H__
|
||||
#define __PKT_LOG_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Pkt log info */
|
||||
typedef PREPACK struct pkt_log_t {
|
||||
struct info_t {
|
||||
u16 st;
|
||||
u16 end;
|
||||
u16 cur;
|
||||
}info[4096];
|
||||
u16 last_idx;
|
||||
}POSTPACK PACKET_LOG;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __PKT_LOG_H__ */
|
|
@ -1,41 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="roaming.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef _ROAMING_H_
|
||||
#define _ROAMING_H_
|
||||
|
||||
/*
|
||||
* The signal quality could be in terms of either snr or rssi. We should
|
||||
* have an enum for both of them. For the time being, we are going to move
|
||||
* it to wmi.h that is shared by both host and the target, since we are
|
||||
* repartitioning the code to the host
|
||||
*/
|
||||
#define SIGNAL_QUALITY_NOISE_FLOOR -96
|
||||
#define SIGNAL_QUALITY_METRICS_NUM_MAX 2
|
||||
typedef enum {
|
||||
SIGNAL_QUALITY_METRICS_SNR = 0,
|
||||
SIGNAL_QUALITY_METRICS_RSSI,
|
||||
SIGNAL_QUALITY_METRICS_ALL,
|
||||
} SIGNAL_QUALITY_METRICS_TYPE;
|
||||
|
||||
#endif /* _ROAMING_H_ */
|
|
@ -1,395 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __TARGADDRS_H__
|
||||
#define __TARGADDRS_H__
|
||||
|
||||
#if defined(AR6002)
|
||||
#include "AR6002/addrs.h"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* AR6K option bits, to enable/disable various features.
|
||||
* By default, all option bits are 0.
|
||||
* These bits can be set in LOCAL_SCRATCH register 0.
|
||||
*/
|
||||
#define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */
|
||||
#define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */
|
||||
#define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */
|
||||
#define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */
|
||||
#define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */
|
||||
#define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */
|
||||
#define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */
|
||||
#define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */
|
||||
|
||||
/*
|
||||
* xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
|
||||
* host_interest structure. It must match the address of the _host_interest
|
||||
* symbol (see linker script).
|
||||
*
|
||||
* Host Interest is shared between Host and Target in order to coordinate
|
||||
* between the two, and is intended to remain constant (with additions only
|
||||
* at the end) across software releases.
|
||||
*
|
||||
* All addresses are available here so that it's possible to
|
||||
* write a single binary that works with all Target Types.
|
||||
* May be used in assembler code as well as C.
|
||||
*/
|
||||
#define AR6002_HOST_INTEREST_ADDRESS 0x00500400
|
||||
#define AR6003_HOST_INTEREST_ADDRESS 0x00540600
|
||||
|
||||
|
||||
#define HOST_INTEREST_MAX_SIZE 0x100
|
||||
|
||||
#if !defined(__ASSEMBLER__)
|
||||
struct register_dump_s;
|
||||
struct dbglog_hdr_s;
|
||||
|
||||
/*
|
||||
* These are items that the Host may need to access
|
||||
* via BMI or via the Diagnostic Window. The position
|
||||
* of items in this structure must remain constant
|
||||
* across firmware revisions!
|
||||
*
|
||||
* Types for each item must be fixed size across
|
||||
* target and host platforms.
|
||||
*
|
||||
* More items may be added at the end.
|
||||
*/
|
||||
PREPACK struct host_interest_s {
|
||||
/*
|
||||
* Pointer to application-defined area, if any.
|
||||
* Set by Target application during startup.
|
||||
*/
|
||||
u32 hi_app_host_interest; /* 0x00 */
|
||||
|
||||
/* Pointer to register dump area, valid after Target crash. */
|
||||
u32 hi_failure_state; /* 0x04 */
|
||||
|
||||
/* Pointer to debug logging header */
|
||||
u32 hi_dbglog_hdr; /* 0x08 */
|
||||
|
||||
u32 hi_unused1; /* 0x0c */
|
||||
|
||||
/*
|
||||
* General-purpose flag bits, similar to AR6000_OPTION_* flags.
|
||||
* Can be used by application rather than by OS.
|
||||
*/
|
||||
u32 hi_option_flag; /* 0x10 */
|
||||
|
||||
/*
|
||||
* Boolean that determines whether or not to
|
||||
* display messages on the serial port.
|
||||
*/
|
||||
u32 hi_serial_enable; /* 0x14 */
|
||||
|
||||
/* Start address of DataSet index, if any */
|
||||
u32 hi_dset_list_head; /* 0x18 */
|
||||
|
||||
/* Override Target application start address */
|
||||
u32 hi_app_start; /* 0x1c */
|
||||
|
||||
/* Clock and voltage tuning */
|
||||
u32 hi_skip_clock_init; /* 0x20 */
|
||||
u32 hi_core_clock_setting; /* 0x24 */
|
||||
u32 hi_cpu_clock_setting; /* 0x28 */
|
||||
u32 hi_system_sleep_setting; /* 0x2c */
|
||||
u32 hi_xtal_control_setting; /* 0x30 */
|
||||
u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
|
||||
u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
|
||||
u32 hi_ref_voltage_trim_setting; /* 0x3c */
|
||||
u32 hi_clock_info; /* 0x40 */
|
||||
|
||||
/*
|
||||
* Flash configuration overrides, used only
|
||||
* when firmware is not executing from flash.
|
||||
* (When using flash, modify the global variables
|
||||
* with equivalent names.)
|
||||
*/
|
||||
u32 hi_bank0_addr_value; /* 0x44 */
|
||||
u32 hi_bank0_read_value; /* 0x48 */
|
||||
u32 hi_bank0_write_value; /* 0x4c */
|
||||
u32 hi_bank0_config_value; /* 0x50 */
|
||||
|
||||
/* Pointer to Board Data */
|
||||
u32 hi_board_data; /* 0x54 */
|
||||
u32 hi_board_data_initialized; /* 0x58 */
|
||||
|
||||
u32 hi_dset_RAM_index_table; /* 0x5c */
|
||||
|
||||
u32 hi_desired_baud_rate; /* 0x60 */
|
||||
u32 hi_dbglog_config; /* 0x64 */
|
||||
u32 hi_end_RAM_reserve_sz; /* 0x68 */
|
||||
u32 hi_mbox_io_block_sz; /* 0x6c */
|
||||
|
||||
u32 hi_num_bpatch_streams; /* 0x70 -- unused */
|
||||
u32 hi_mbox_isr_yield_limit; /* 0x74 */
|
||||
|
||||
u32 hi_refclk_hz; /* 0x78 */
|
||||
u32 hi_ext_clk_detected; /* 0x7c */
|
||||
u32 hi_dbg_uart_txpin; /* 0x80 */
|
||||
u32 hi_dbg_uart_rxpin; /* 0x84 */
|
||||
u32 hi_hci_uart_baud; /* 0x88 */
|
||||
u32 hi_hci_uart_pin_assignments; /* 0x8C */
|
||||
/* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
|
||||
u32 hi_hci_uart_baud_scale_val; /* 0x90 */
|
||||
u32 hi_hci_uart_baud_step_val; /* 0x94 */
|
||||
|
||||
u32 hi_allocram_start; /* 0x98 */
|
||||
u32 hi_allocram_sz; /* 0x9c */
|
||||
u32 hi_hci_bridge_flags; /* 0xa0 */
|
||||
u32 hi_hci_uart_support_pins; /* 0xa4 */
|
||||
/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
|
||||
u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
|
||||
/*
|
||||
* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
|
||||
* [31:16]: wakeup timeout in ms
|
||||
*/
|
||||
|
||||
/* Pointer to extended board data */
|
||||
u32 hi_board_ext_data; /* 0xac */
|
||||
u32 hi_board_ext_data_config; /* 0xb0 */
|
||||
|
||||
/*
|
||||
* Bit [0] : valid
|
||||
* Bit[31:16: size
|
||||
*/
|
||||
/*
|
||||
* hi_reset_flag is used to do some stuff when target reset.
|
||||
* such as restore app_start after warm reset or
|
||||
* preserve host Interest area, or preserve ROM data, literals etc.
|
||||
*/
|
||||
u32 hi_reset_flag; /* 0xb4 */
|
||||
/* indicate hi_reset_flag is valid */
|
||||
u32 hi_reset_flag_valid; /* 0xb8 */
|
||||
u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
|
||||
/*
|
||||
* 0xbc - [31:0]: idle timeout in ms
|
||||
*/
|
||||
/* ACS flags */
|
||||
u32 hi_acs_flags; /* 0xc0 */
|
||||
u32 hi_console_flags; /* 0xc4 */
|
||||
u32 hi_nvram_state; /* 0xc8 */
|
||||
u32 hi_option_flag2; /* 0xcc */
|
||||
|
||||
/* If non-zero, override values sent to Host in WMI_READY event. */
|
||||
u32 hi_sw_version_override; /* 0xd0 */
|
||||
u32 hi_abi_version_override; /* 0xd4 */
|
||||
|
||||
/*
|
||||
* Percentage of high priority RX traffic to total expected RX traffic -
|
||||
* applicable only to ar6004
|
||||
*/
|
||||
u32 hi_hp_rx_traffic_ratio; /* 0xd8 */
|
||||
|
||||
/* test applications flags */
|
||||
u32 hi_test_apps_related ; /* 0xdc */
|
||||
/* location of test script */
|
||||
u32 hi_ota_testscript; /* 0xe0 */
|
||||
/* location of CAL data */
|
||||
u32 hi_cal_data; /* 0xe4 */
|
||||
/* Number of packet log buffers */
|
||||
u32 hi_pktlog_num_buffers; /* 0xe8 */
|
||||
|
||||
} POSTPACK;
|
||||
|
||||
/* Bits defined in hi_option_flag */
|
||||
#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
|
||||
#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
|
||||
#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
|
||||
/* MAC addr method 0-locally administred 1-globally unique addrs */
|
||||
#define HI_OPTION_MAC_ADDR_METHOD 0x08
|
||||
#define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */
|
||||
#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
|
||||
#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
|
||||
#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
|
||||
#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
|
||||
#define HI_OPTION_NUM_DEV_LSB 0x200
|
||||
#define HI_OPTION_NUM_DEV_MSB 0x800
|
||||
#define HI_OPTION_DEV_MODE_LSB 0x1000
|
||||
#define HI_OPTION_DEV_MODE_MSB 0x8000000
|
||||
/* Disable LowFreq Timer Stabilization */
|
||||
#define HI_OPTION_NO_LFT_STBL 0x10000000
|
||||
#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */
|
||||
/* Do regulatory scan during init beforesending WMI ready event to host */
|
||||
#define HI_OPTION_INIT_REG_SCAN 0x40000000
|
||||
#define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory
|
||||
map */
|
||||
|
||||
/* hi_option_flag2 options */
|
||||
#define HI_OPTION_OFFLOAD_AMSDU 0x01
|
||||
#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
|
||||
|
||||
#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
|
||||
|
||||
/* 2 bits of hi_option_flag are used to represent 3 modes */
|
||||
#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
|
||||
#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
|
||||
#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
|
||||
|
||||
/* 2 bits of hi_option flag are usedto represent 4 submodes */
|
||||
#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
|
||||
#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
|
||||
#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
|
||||
#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
|
||||
|
||||
/* Num dev Mask */
|
||||
#define HI_OPTION_NUM_DEV_MASK 0x7
|
||||
#define HI_OPTION_NUM_DEV_SHIFT 0x9
|
||||
|
||||
/* firmware bridging */
|
||||
#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
|
||||
|
||||
/* Fw Mode/SubMode Mask
|
||||
|------------------------------------------------------------------------------|
|
||||
| SUB | SUB | SUB | SUB | | | |
|
||||
| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0|
|
||||
| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2)
|
||||
|------------------------------------------------------------------------------|
|
||||
*/
|
||||
#define HI_OPTION_FW_MODE_BITS 0x2
|
||||
#define HI_OPTION_FW_MODE_MASK 0x3
|
||||
#define HI_OPTION_FW_MODE_SHIFT 0xC
|
||||
#define HI_OPTION_ALL_FW_MODE_MASK 0xFF
|
||||
|
||||
#define HI_OPTION_FW_SUBMODE_BITS 0x2
|
||||
#define HI_OPTION_FW_SUBMODE_MASK 0x3
|
||||
#define HI_OPTION_FW_SUBMODE_SHIFT 0x14
|
||||
#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
|
||||
#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
|
||||
|
||||
/* hi_reset_flag */
|
||||
|
||||
/* preserve App Start address */
|
||||
#define HI_RESET_FLAG_PRESERVE_APP_START 0x01
|
||||
/* preserve host interest */
|
||||
#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02
|
||||
#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */
|
||||
#define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08
|
||||
#define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10
|
||||
|
||||
#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is
|
||||
valid */
|
||||
|
||||
#define ON_RESET_FLAGS_VALID() \
|
||||
(HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
|
||||
|
||||
#define RESET_FLAGS_VALIDATE() \
|
||||
(HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
|
||||
|
||||
#define RESET_FLAGS_INVALIDATE() \
|
||||
(HOST_INTEREST->hi_reset_flag_valid = 0)
|
||||
|
||||
#define ON_RESET_PRESERVE_APP_START() \
|
||||
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
|
||||
|
||||
#define ON_RESET_PRESERVE_NVRAM_STATE() \
|
||||
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
|
||||
|
||||
#define ON_RESET_PRESERVE_HOST_INTEREST() \
|
||||
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
|
||||
|
||||
#define ON_RESET_PRESERVE_ROMDATA() \
|
||||
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
|
||||
|
||||
#define ON_RESET_PRESERVE_BOOT_INFO() \
|
||||
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO)
|
||||
|
||||
#define HI_ACS_FLAGS_ENABLED (1 << 0) /* ACS is enabled */
|
||||
#define HI_ACS_FLAGS_USE_WWAN (1 << 1) /* Use physical WWAN device */
|
||||
#define HI_ACS_FLAGS_TEST_VAP (1 << 2) /* Use test VAP */
|
||||
|
||||
/* CONSOLE FLAGS
|
||||
*
|
||||
* Bit Range Meaning
|
||||
* --------- --------------------------------
|
||||
* 2..0 UART ID (0 = Default)
|
||||
* 3 Baud Select (0 = 9600, 1 = 115200)
|
||||
* 30..4 Reserved
|
||||
* 31 Enable Console
|
||||
*
|
||||
*/
|
||||
|
||||
#define HI_CONSOLE_FLAGS_ENABLE (1 << 31)
|
||||
#define HI_CONSOLE_FLAGS_UART_MASK (0x7)
|
||||
#define HI_CONSOLE_FLAGS_UART_SHIFT 0
|
||||
#define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3)
|
||||
|
||||
/*
|
||||
* Intended for use by Host software, this macro returns the Target RAM
|
||||
* address of any item in the host_interest structure.
|
||||
* Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
|
||||
*/
|
||||
#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
|
||||
(u32)((unsigned long)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
|
||||
|
||||
#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
|
||||
(u32)((unsigned long)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
|
||||
|
||||
#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \
|
||||
((u32)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item)))
|
||||
|
||||
|
||||
#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
|
||||
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
|
||||
|
||||
#define HOST_INTEREST_PKTLOG_IS_ENABLED() \
|
||||
((HOST_INTEREST->hi_pktlog_num_buffers))
|
||||
|
||||
|
||||
#define HOST_INTEREST_PROFILE_IS_ENABLED() \
|
||||
(HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
|
||||
|
||||
#define LF_TIMER_STABILIZATION_IS_ENABLED() \
|
||||
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
|
||||
|
||||
#define IS_AMSDU_OFFLAOD_ENABLED() \
|
||||
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
|
||||
|
||||
#define HOST_INTEREST_DFS_IS_ENABLED() \
|
||||
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT))
|
||||
|
||||
/* Convert a Target virtual address into a Target physical address */
|
||||
#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
|
||||
#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
|
||||
#define TARG_VTOP(TargetType, vaddr) \
|
||||
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr))
|
||||
|
||||
#define AR6003_REV2_APP_START_OVERRIDE 0x944C00
|
||||
#define AR6003_REV2_APP_LOAD_ADDRESS 0x543180
|
||||
#define AR6003_REV2_BOARD_EXT_DATA_ADDRESS 0x57E500
|
||||
#define AR6003_REV2_DATASET_PATCH_ADDRESS 0x57e884
|
||||
#define AR6003_REV2_RAM_RESERVE_SIZE 6912
|
||||
|
||||
#define AR6003_REV3_APP_START_OVERRIDE 0x945d00
|
||||
#define AR6003_REV3_APP_LOAD_ADDRESS 0x545000
|
||||
#define AR6003_REV3_BOARD_EXT_DATA_ADDRESS 0x542330
|
||||
#define AR6003_REV3_DATASET_PATCH_ADDRESS 0x57FF74
|
||||
#define AR6003_REV3_RAM_RESERVE_SIZE 512
|
||||
|
||||
#define AR6003_BOARD_EXT_DATA_ADDRESS 0x57E600
|
||||
|
||||
/* # of u32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
|
||||
#define AR6003_FETCH_TARG_REGS_COUNT 64
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
#endif /* __TARGADDRS_H__ */
|
|
@ -1,185 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="testcmd.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef TESTCMD_H_
|
||||
#define TESTCMD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef AR6002_REV2
|
||||
#define TCMD_MAX_RATES 12
|
||||
#else
|
||||
#define TCMD_MAX_RATES 28
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
ZEROES_PATTERN = 0,
|
||||
ONES_PATTERN,
|
||||
REPEATING_10,
|
||||
PN7_PATTERN,
|
||||
PN9_PATTERN,
|
||||
PN15_PATTERN
|
||||
}TX_DATA_PATTERN;
|
||||
|
||||
/* Continuous tx
|
||||
mode : TCMD_CONT_TX_OFF - Disabling continuous tx
|
||||
TCMD_CONT_TX_SINE - Enable continuous unmodulated tx
|
||||
TCMD_CONT_TX_FRAME- Enable continuous modulated tx
|
||||
freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g)
|
||||
dataRate: 0 - 1 Mbps
|
||||
1 - 2 Mbps
|
||||
2 - 5.5 Mbps
|
||||
3 - 11 Mbps
|
||||
4 - 6 Mbps
|
||||
5 - 9 Mbps
|
||||
6 - 12 Mbps
|
||||
7 - 18 Mbps
|
||||
8 - 24 Mbps
|
||||
9 - 36 Mbps
|
||||
10 - 28 Mbps
|
||||
11 - 54 Mbps
|
||||
txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx
|
||||
antenna: 1 - one antenna
|
||||
2 - two antenna
|
||||
Note : Enable/disable continuous tx test cmd works only when target is awake.
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
TCMD_CONT_TX_OFF = 0,
|
||||
TCMD_CONT_TX_SINE,
|
||||
TCMD_CONT_TX_FRAME,
|
||||
TCMD_CONT_TX_TX99,
|
||||
TCMD_CONT_TX_TX100
|
||||
} TCMD_CONT_TX_MODE;
|
||||
|
||||
typedef enum {
|
||||
TCMD_WLAN_MODE_NOHT = 0,
|
||||
TCMD_WLAN_MODE_HT20 = 1,
|
||||
TCMD_WLAN_MODE_HT40PLUS = 2,
|
||||
TCMD_WLAN_MODE_HT40MINUS = 3,
|
||||
} TCMD_WLAN_MODE;
|
||||
|
||||
typedef PREPACK struct {
|
||||
u32 testCmdId;
|
||||
u32 mode;
|
||||
u32 freq;
|
||||
u32 dataRate;
|
||||
s32 txPwr;
|
||||
u32 antenna;
|
||||
u32 enANI;
|
||||
u32 scramblerOff;
|
||||
u32 aifsn;
|
||||
u16 pktSz;
|
||||
u16 txPattern;
|
||||
u32 shortGuard;
|
||||
u32 numPackets;
|
||||
u32 wlanMode;
|
||||
} POSTPACK TCMD_CONT_TX;
|
||||
|
||||
#define TCMD_TXPATTERN_ZERONE 0x1
|
||||
#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE 0x2
|
||||
|
||||
/* Continuous Rx
|
||||
act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames)
|
||||
TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest
|
||||
address equal specified
|
||||
mac address (set via act =3)
|
||||
TCMD_CONT_RX_REPORT off mode (disable cont rx mode and get the
|
||||
report from the last cont
|
||||
Rx test)
|
||||
|
||||
TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the
|
||||
target. This Overrides
|
||||
the default MAC address.)
|
||||
|
||||
*/
|
||||
typedef enum {
|
||||
TCMD_CONT_RX_PROMIS =0,
|
||||
TCMD_CONT_RX_FILTER,
|
||||
TCMD_CONT_RX_REPORT,
|
||||
TCMD_CONT_RX_SETMAC,
|
||||
TCMD_CONT_RX_SET_ANT_SWITCH_TABLE
|
||||
} TCMD_CONT_RX_ACT;
|
||||
|
||||
typedef PREPACK struct {
|
||||
u32 testCmdId;
|
||||
u32 act;
|
||||
u32 enANI;
|
||||
PREPACK union {
|
||||
struct PREPACK TCMD_CONT_RX_PARA {
|
||||
u32 freq;
|
||||
u32 antenna;
|
||||
u32 wlanMode;
|
||||
} POSTPACK para;
|
||||
struct PREPACK TCMD_CONT_RX_REPORT {
|
||||
u32 totalPkt;
|
||||
s32 rssiInDBm;
|
||||
u32 crcErrPkt;
|
||||
u32 secErrPkt;
|
||||
u16 rateCnt[TCMD_MAX_RATES];
|
||||
u16 rateCntShortGuard[TCMD_MAX_RATES];
|
||||
} POSTPACK report;
|
||||
struct PREPACK TCMD_CONT_RX_MAC {
|
||||
u8 addr[ATH_MAC_LEN];
|
||||
} POSTPACK mac;
|
||||
struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE {
|
||||
u32 antswitch1;
|
||||
u32 antswitch2;
|
||||
}POSTPACK antswitchtable;
|
||||
} POSTPACK u;
|
||||
} POSTPACK TCMD_CONT_RX;
|
||||
|
||||
/* Force sleep/wake test cmd
|
||||
mode: TCMD_PM_WAKEUP - Wakeup the target
|
||||
TCMD_PM_SLEEP - Force the target to sleep.
|
||||
*/
|
||||
typedef enum {
|
||||
TCMD_PM_WAKEUP = 1, /* be consistent with target */
|
||||
TCMD_PM_SLEEP,
|
||||
TCMD_PM_DEEPSLEEP
|
||||
} TCMD_PM_MODE;
|
||||
|
||||
typedef PREPACK struct {
|
||||
u32 testCmdId;
|
||||
u32 mode;
|
||||
} POSTPACK TCMD_PM;
|
||||
|
||||
typedef enum {
|
||||
TCMD_CONT_TX_ID,
|
||||
TCMD_CONT_RX_ID,
|
||||
TCMD_PM_ID
|
||||
} TCMD_ID;
|
||||
|
||||
typedef PREPACK union {
|
||||
TCMD_CONT_TX contTx;
|
||||
TCMD_CONT_RX contRx;
|
||||
TCMD_PM pm;
|
||||
} POSTPACK TEST_CMD;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* TESTCMD_H_ */
|
|
@ -1,38 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#ifndef __TLPM_H__
|
||||
#define __TLPM_H__
|
||||
|
||||
/* idle timeout in 16-bit value as in HOST_INTEREST hi_hci_uart_pwr_mgmt_params */
|
||||
#define TLPM_DEFAULT_IDLE_TIMEOUT_MS 1000
|
||||
/* hex in LSB and MSB for HCI command */
|
||||
#define TLPM_DEFAULT_IDLE_TIMEOUT_LSB 0xE8
|
||||
#define TLPM_DEFAULT_IDLE_TIMEOUT_MSB 0x3
|
||||
|
||||
/* wakeup timeout in 8-bit value as in HOST_INTEREST hi_hci_uart_pwr_mgmt_params */
|
||||
#define TLPM_DEFAULT_WAKEUP_TIMEOUT_MS 10
|
||||
|
||||
/* default UART FC polarity is low */
|
||||
#define TLPM_DEFAULT_UART_FC_POLARITY 0
|
||||
|
||||
#endif
|
|
@ -1,79 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="wlan_defs.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef __WLAN_DEFS_H__
|
||||
#define __WLAN_DEFS_H__
|
||||
|
||||
/*
|
||||
* This file contains WLAN definitions that may be used across both
|
||||
* Host and Target software.
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
MODE_11A = 0, /* 11a Mode */
|
||||
MODE_11G = 1, /* 11b/g Mode */
|
||||
MODE_11B = 2, /* 11b Mode */
|
||||
MODE_11GONLY = 3, /* 11g only Mode */
|
||||
#ifdef SUPPORT_11N
|
||||
MODE_11NA_HT20 = 4, /* 11a HT20 mode */
|
||||
MODE_11NG_HT20 = 5, /* 11g HT20 mode */
|
||||
MODE_11NA_HT40 = 6, /* 11a HT40 mode */
|
||||
MODE_11NG_HT40 = 7, /* 11g HT40 mode */
|
||||
MODE_UNKNOWN = 8,
|
||||
MODE_MAX = 8
|
||||
#else
|
||||
MODE_UNKNOWN = 4,
|
||||
MODE_MAX = 4
|
||||
#endif
|
||||
} WLAN_PHY_MODE;
|
||||
|
||||
typedef enum {
|
||||
WLAN_11A_CAPABILITY = 1,
|
||||
WLAN_11G_CAPABILITY = 2,
|
||||
WLAN_11AG_CAPABILITY = 3,
|
||||
}WLAN_CAPABILITY;
|
||||
|
||||
#ifdef SUPPORT_11N
|
||||
typedef unsigned long A_RATEMASK;
|
||||
#else
|
||||
typedef unsigned short A_RATEMASK;
|
||||
#endif
|
||||
|
||||
#ifdef SUPPORT_11N
|
||||
#define IS_MODE_11A(mode) (((mode) == MODE_11A) || \
|
||||
((mode) == MODE_11NA_HT20) || \
|
||||
((mode) == MODE_11NA_HT40))
|
||||
#define IS_MODE_11B(mode) ((mode) == MODE_11B)
|
||||
#define IS_MODE_11G(mode) (((mode) == MODE_11G) || \
|
||||
((mode) == MODE_11GONLY) || \
|
||||
((mode) == MODE_11NG_HT20) || \
|
||||
((mode) == MODE_11NG_HT40))
|
||||
#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY)
|
||||
#else
|
||||
#define IS_MODE_11A(mode) ((mode) == MODE_11A)
|
||||
#define IS_MODE_11B(mode) ((mode) == MODE_11B)
|
||||
#define IS_MODE_11G(mode) (((mode) == MODE_11G) || \
|
||||
((mode) == MODE_11GONLY))
|
||||
#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY)
|
||||
#endif /* SUPPORT_11N */
|
||||
|
||||
#endif /* __WLANDEFS_H__ */
|
File diff suppressed because it is too large
Load diff
|
@ -1,271 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="wmix.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
/*
|
||||
* This file contains extensions of the WMI protocol specified in the
|
||||
* Wireless Module Interface (WMI). It includes definitions of all
|
||||
* extended commands and events. Extensions include useful commands
|
||||
* that are not directly related to wireless activities. They may
|
||||
* be hardware-specific, and they might not be supported on all
|
||||
* implementations.
|
||||
*
|
||||
* Extended WMIX commands are encapsulated in a WMI message with
|
||||
* cmd=WMI_EXTENSION_CMD.
|
||||
*/
|
||||
|
||||
#ifndef _WMIX_H_
|
||||
#define _WMIX_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "dbglog.h"
|
||||
|
||||
/*
|
||||
* Extended WMI commands are those that are needed during wireless
|
||||
* operation, but which are not really wireless commands. This allows,
|
||||
* for instance, platform-specific commands. Extended WMI commands are
|
||||
* embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID.
|
||||
* Extended WMI events are similarly embedded in a WMI event message with
|
||||
* WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
|
||||
*/
|
||||
typedef PREPACK struct {
|
||||
u32 commandId;
|
||||
} POSTPACK WMIX_CMD_HDR;
|
||||
|
||||
typedef enum {
|
||||
WMIX_DSETOPEN_REPLY_CMDID = 0x2001,
|
||||
WMIX_DSETDATA_REPLY_CMDID,
|
||||
WMIX_GPIO_OUTPUT_SET_CMDID,
|
||||
WMIX_GPIO_INPUT_GET_CMDID,
|
||||
WMIX_GPIO_REGISTER_SET_CMDID,
|
||||
WMIX_GPIO_REGISTER_GET_CMDID,
|
||||
WMIX_GPIO_INTR_ACK_CMDID,
|
||||
WMIX_HB_CHALLENGE_RESP_CMDID,
|
||||
WMIX_DBGLOG_CFG_MODULE_CMDID,
|
||||
WMIX_PROF_CFG_CMDID, /* 0x200a */
|
||||
WMIX_PROF_ADDR_SET_CMDID,
|
||||
WMIX_PROF_START_CMDID,
|
||||
WMIX_PROF_STOP_CMDID,
|
||||
WMIX_PROF_COUNT_GET_CMDID,
|
||||
} WMIX_COMMAND_ID;
|
||||
|
||||
typedef enum {
|
||||
WMIX_DSETOPENREQ_EVENTID = 0x3001,
|
||||
WMIX_DSETCLOSE_EVENTID,
|
||||
WMIX_DSETDATAREQ_EVENTID,
|
||||
WMIX_GPIO_INTR_EVENTID,
|
||||
WMIX_GPIO_DATA_EVENTID,
|
||||
WMIX_GPIO_ACK_EVENTID,
|
||||
WMIX_HB_CHALLENGE_RESP_EVENTID,
|
||||
WMIX_DBGLOG_EVENTID,
|
||||
WMIX_PROF_COUNT_EVENTID,
|
||||
} WMIX_EVENT_ID;
|
||||
|
||||
/*
|
||||
* =============DataSet support=================
|
||||
*/
|
||||
|
||||
/*
|
||||
* WMIX_DSETOPENREQ_EVENTID
|
||||
* DataSet Open Request Event
|
||||
*/
|
||||
typedef PREPACK struct {
|
||||
u32 dset_id;
|
||||
u32 targ_dset_handle; /* echo'ed, not used by Host, */
|
||||
u32 targ_reply_fn; /* echo'ed, not used by Host, */
|
||||
u32 targ_reply_arg; /* echo'ed, not used by Host, */
|
||||
} POSTPACK WMIX_DSETOPENREQ_EVENT;
|
||||
|
||||
/*
|
||||
* WMIX_DSETCLOSE_EVENTID
|
||||
* DataSet Close Event
|
||||
*/
|
||||
typedef PREPACK struct {
|
||||
u32 access_cookie;
|
||||
} POSTPACK WMIX_DSETCLOSE_EVENT;
|
||||
|
||||
/*
|
||||
* WMIX_DSETDATAREQ_EVENTID
|
||||
* DataSet Data Request Event
|
||||
*/
|
||||
typedef PREPACK struct {
|
||||
u32 access_cookie;
|
||||
u32 offset;
|
||||
u32 length;
|
||||
u32 targ_buf; /* echo'ed, not used by Host, */
|
||||
u32 targ_reply_fn; /* echo'ed, not used by Host, */
|
||||
u32 targ_reply_arg; /* echo'ed, not used by Host, */
|
||||
} POSTPACK WMIX_DSETDATAREQ_EVENT;
|
||||
|
||||
typedef PREPACK struct {
|
||||
u32 status;
|
||||
u32 targ_dset_handle;
|
||||
u32 targ_reply_fn;
|
||||
u32 targ_reply_arg;
|
||||
u32 access_cookie;
|
||||
u32 size;
|
||||
u32 version;
|
||||
} POSTPACK WMIX_DSETOPEN_REPLY_CMD;
|
||||
|
||||
typedef PREPACK struct {
|
||||
u32 status;
|
||||
u32 targ_buf;
|
||||
u32 targ_reply_fn;
|
||||
u32 targ_reply_arg;
|
||||
u32 length;
|
||||
u8 buf[1];
|
||||
} POSTPACK WMIX_DSETDATA_REPLY_CMD;
|
||||
|
||||
|
||||
/*
|
||||
* =============GPIO support=================
|
||||
* All masks are 18-bit masks with bit N operating on GPIO pin N.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Set GPIO pin output state.
|
||||
* In order for output to be driven, a pin must be enabled for output.
|
||||
* This can be done during initialization through the GPIO Configuration
|
||||
* DataSet, or during operation with the enable_mask.
|
||||
*
|
||||
* If a request is made to simultaneously set/clear or set/disable or
|
||||
* clear/disable or disable/enable, results are undefined.
|
||||
*/
|
||||
typedef PREPACK struct {
|
||||
u32 set_mask; /* pins to set */
|
||||
u32 clear_mask; /* pins to clear */
|
||||
u32 enable_mask; /* pins to enable for output */
|
||||
u32 disable_mask; /* pins to disable/tristate */
|
||||
} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD;
|
||||
|
||||
/*
|
||||
* Set a GPIO register. For debug/exceptional cases.
|
||||
* Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a
|
||||
* platform-dependent header.
|
||||
*/
|
||||
typedef PREPACK struct {
|
||||
u32 gpioreg_id; /* GPIO register ID */
|
||||
u32 value; /* value to write */
|
||||
} POSTPACK WMIX_GPIO_REGISTER_SET_CMD;
|
||||
|
||||
/* Get a GPIO register. For debug/exceptional cases. */
|
||||
typedef PREPACK struct {
|
||||
u32 gpioreg_id; /* GPIO register to read */
|
||||
} POSTPACK WMIX_GPIO_REGISTER_GET_CMD;
|
||||
|
||||
/*
|
||||
* Host acknowledges and re-arms GPIO interrupts. A single
|
||||
* message should be used to acknowledge all interrupts that
|
||||
* were delivered in an earlier WMIX_GPIO_INTR_EVENT message.
|
||||
*/
|
||||
typedef PREPACK struct {
|
||||
u32 ack_mask; /* interrupts to acknowledge */
|
||||
} POSTPACK WMIX_GPIO_INTR_ACK_CMD;
|
||||
|
||||
/*
|
||||
* Target informs Host of GPIO interrupts that have occurred since the
|
||||
* last WMIX_GIPO_INTR_ACK_CMD was received. Additional information --
|
||||
* the current GPIO input values is provided -- in order to support
|
||||
* use of a GPIO interrupt as a Data Valid signal for other GPIO pins.
|
||||
*/
|
||||
typedef PREPACK struct {
|
||||
u32 intr_mask; /* pending GPIO interrupts */
|
||||
u32 input_values; /* recent GPIO input values */
|
||||
} POSTPACK WMIX_GPIO_INTR_EVENT;
|
||||
|
||||
/*
|
||||
* Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request
|
||||
* using a GPIO_DATA_EVENT with
|
||||
* value set to the mask of GPIO pin inputs and
|
||||
* reg_id set to GPIO_ID_NONE
|
||||
*
|
||||
*
|
||||
* Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request
|
||||
* using a GPIO_DATA_EVENT with
|
||||
* value set to the value of the requested register and
|
||||
* reg_id identifying the register (reflects the original request)
|
||||
* NB: reg_id supports the future possibility of unsolicited
|
||||
* WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may
|
||||
* simplify Host GPIO support.
|
||||
*/
|
||||
typedef PREPACK struct {
|
||||
u32 value;
|
||||
u32 reg_id;
|
||||
} POSTPACK WMIX_GPIO_DATA_EVENT;
|
||||
|
||||
/*
|
||||
* =============Error Detection support=================
|
||||
*/
|
||||
|
||||
/*
|
||||
* WMIX_HB_CHALLENGE_RESP_CMDID
|
||||
* Heartbeat Challenge Response command
|
||||
*/
|
||||
typedef PREPACK struct {
|
||||
u32 cookie;
|
||||
u32 source;
|
||||
} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD;
|
||||
|
||||
/*
|
||||
* WMIX_HB_CHALLENGE_RESP_EVENTID
|
||||
* Heartbeat Challenge Response Event
|
||||
*/
|
||||
#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD
|
||||
|
||||
typedef PREPACK struct {
|
||||
struct dbglog_config_s config;
|
||||
} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD;
|
||||
|
||||
/*
|
||||
* =============Target Profiling support=================
|
||||
*/
|
||||
|
||||
typedef PREPACK struct {
|
||||
u32 period; /* Time (in 30.5us ticks) between samples */
|
||||
u32 nbins;
|
||||
} POSTPACK WMIX_PROF_CFG_CMD;
|
||||
|
||||
typedef PREPACK struct {
|
||||
u32 addr;
|
||||
} POSTPACK WMIX_PROF_ADDR_SET_CMD;
|
||||
|
||||
/*
|
||||
* Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request
|
||||
* using a WMIX_PROF_COUNT_EVENT with
|
||||
* addr set to the next address
|
||||
* count set to the corresponding count
|
||||
*/
|
||||
typedef PREPACK struct {
|
||||
u32 addr;
|
||||
u32 count;
|
||||
} POSTPACK WMIX_PROF_COUNT_EVENT;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _WMIX_H_ */
|
|
@ -1,104 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef COMMON_DRV_H_
|
||||
#define COMMON_DRV_H_
|
||||
|
||||
#include "hif.h"
|
||||
#include "htc_packet.h"
|
||||
#include "htc_api.h"
|
||||
|
||||
/* structure that is the state information for the default credit distribution callback
|
||||
* drivers should instantiate (zero-init as well) this structure in their driver instance
|
||||
* and pass it as a context to the HTC credit distribution functions */
|
||||
struct common_credit_state_info {
|
||||
int TotalAvailableCredits; /* total credits in the system at startup */
|
||||
int CurrentFreeCredits; /* credits available in the pool that have not been
|
||||
given out to endpoints */
|
||||
struct htc_endpoint_credit_dist *pLowestPriEpDist; /* pointer to the lowest priority endpoint dist struct */
|
||||
};
|
||||
|
||||
struct hci_transport_callbacks {
|
||||
s32 (*setupTransport)(void *ar);
|
||||
void (*cleanupTransport)(void *ar);
|
||||
};
|
||||
|
||||
struct hci_transport_misc_handles {
|
||||
void *netDevice;
|
||||
void *hifDevice;
|
||||
void *htcHandle;
|
||||
};
|
||||
|
||||
/* HTC TX packet tagging definitions */
|
||||
#define AR6K_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED
|
||||
#define AR6K_DATA_PKT_TAG (AR6K_CONTROL_PKT_TAG + 1)
|
||||
|
||||
#define AR6002_VERSION_REV1 0x20000086
|
||||
#define AR6002_VERSION_REV2 0x20000188
|
||||
#define AR6003_VERSION_REV1 0x300002ba
|
||||
#define AR6003_VERSION_REV2 0x30000384
|
||||
|
||||
#define AR6002_CUST_DATA_SIZE 112
|
||||
#define AR6003_CUST_DATA_SIZE 16
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* OS-independent APIs */
|
||||
int ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, struct common_credit_state_info *pCredInfo);
|
||||
|
||||
int ar6000_ReadRegDiag(struct hif_device *hifDevice, u32 *address, u32 *data);
|
||||
|
||||
int ar6000_WriteRegDiag(struct hif_device *hifDevice, u32 *address, u32 *data);
|
||||
|
||||
int ar6000_ReadDataDiag(struct hif_device *hifDevice, u32 address, u8 *data, u32 length);
|
||||
|
||||
int ar6000_reset_device(struct hif_device *hifDevice, u32 TargetType, bool waitForCompletion, bool coldReset);
|
||||
|
||||
void ar6000_dump_target_assert_info(struct hif_device *hifDevice, u32 TargetType);
|
||||
|
||||
int ar6000_set_htc_params(struct hif_device *hifDevice,
|
||||
u32 TargetType,
|
||||
u32 MboxIsrYieldValue,
|
||||
u8 HtcControlBuffers);
|
||||
|
||||
int ar6000_set_hci_bridge_flags(struct hif_device *hifDevice,
|
||||
u32 TargetType,
|
||||
u32 Flags);
|
||||
|
||||
void ar6000_copy_cust_data_from_target(struct hif_device *hifDevice, u32 TargetType);
|
||||
|
||||
u8 *ar6000_get_cust_data_buffer(u32 TargetType);
|
||||
|
||||
int ar6000_setBTState(void *context, u8 *pInBuf, u32 InBufSize);
|
||||
|
||||
int ar6000_setDevicePowerState(void *context, u8 *pInBuf, u32 InBufSize);
|
||||
|
||||
int ar6000_setWowMode(void *context, u8 *pInBuf, u32 InBufSize);
|
||||
|
||||
int ar6000_setHostMode(void *context, u8 *pInBuf, u32 InBufSize);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*COMMON_DRV_H_*/
|
|
@ -1,52 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="dbglog_api.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// This file contains host side debug primitives.
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _DBGLOG_API_H_
|
||||
#define _DBGLOG_API_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "dbglog.h"
|
||||
|
||||
#define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE
|
||||
|
||||
#define DBGLOG_GET_DBGID(arg) \
|
||||
((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
|
||||
|
||||
#define DBGLOG_GET_MODULEID(arg) \
|
||||
((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
|
||||
|
||||
#define DBGLOG_GET_NUMARGS(arg) \
|
||||
((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
|
||||
|
||||
#define DBGLOG_GET_TIMESTAMP(arg) \
|
||||
((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DBGLOG_API_H_ */
|
|
@ -1,153 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="dl_list.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Double-link list definitions (adapted from Atheros SDIO stack)
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef __DL_LIST_H___
|
||||
#define __DL_LIST_H___
|
||||
|
||||
#include "a_osapi.h"
|
||||
|
||||
#define A_CONTAINING_STRUCT(address, struct_type, field_name)\
|
||||
((struct_type *)((unsigned long)(address) - (unsigned long)(&((struct_type *)0)->field_name)))
|
||||
|
||||
/* list functions */
|
||||
/* pointers for the list */
|
||||
struct dl_list {
|
||||
struct dl_list *pPrev;
|
||||
struct dl_list *pNext;
|
||||
};
|
||||
/*
|
||||
* DL_LIST_INIT , initialize doubly linked list
|
||||
*/
|
||||
#define DL_LIST_INIT(pList)\
|
||||
{(pList)->pPrev = pList; (pList)->pNext = pList;}
|
||||
|
||||
/* faster macro to init list and add a single item */
|
||||
#define DL_LIST_INIT_AND_ADD(pList,pItem) \
|
||||
{ (pList)->pPrev = (pItem); \
|
||||
(pList)->pNext = (pItem); \
|
||||
(pItem)->pNext = (pList); \
|
||||
(pItem)->pPrev = (pList); \
|
||||
}
|
||||
|
||||
#define DL_LIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList)))
|
||||
#define DL_LIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext
|
||||
#define DL_LIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev
|
||||
/*
|
||||
* ITERATE_OVER_LIST pStart is the list, pTemp is a temp list member
|
||||
* NOT: do not use this function if the items in the list are deleted inside the
|
||||
* iteration loop
|
||||
*/
|
||||
#define ITERATE_OVER_LIST(pStart, pTemp) \
|
||||
for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext)
|
||||
|
||||
|
||||
/* safe iterate macro that allows the item to be removed from the list
|
||||
* the iteration continues to the next item in the list
|
||||
*/
|
||||
#define ITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset) \
|
||||
{ \
|
||||
struct dl_list * pTemp; \
|
||||
pTemp = (pStart)->pNext; \
|
||||
while (pTemp != (pStart)) { \
|
||||
(pItem) = A_CONTAINING_STRUCT(pTemp,st,offset); \
|
||||
pTemp = pTemp->pNext; \
|
||||
|
||||
#define ITERATE_END }}
|
||||
|
||||
/*
|
||||
* DL_ListInsertTail - insert pAdd to the end of the list
|
||||
*/
|
||||
static INLINE struct dl_list *DL_ListInsertTail(struct dl_list *pList, struct dl_list *pAdd) {
|
||||
/* insert at tail */
|
||||
pAdd->pPrev = pList->pPrev;
|
||||
pAdd->pNext = pList;
|
||||
pList->pPrev->pNext = pAdd;
|
||||
pList->pPrev = pAdd;
|
||||
return pAdd;
|
||||
}
|
||||
|
||||
/*
|
||||
* DL_ListInsertHead - insert pAdd into the head of the list
|
||||
*/
|
||||
static INLINE struct dl_list * DL_ListInsertHead(struct dl_list * pList, struct dl_list * pAdd) {
|
||||
/* insert at head */
|
||||
pAdd->pPrev = pList;
|
||||
pAdd->pNext = pList->pNext;
|
||||
pList->pNext->pPrev = pAdd;
|
||||
pList->pNext = pAdd;
|
||||
return pAdd;
|
||||
}
|
||||
|
||||
#define DL_ListAdd(pList,pItem) DL_ListInsertHead((pList),(pItem))
|
||||
/*
|
||||
* DL_ListRemove - remove pDel from list
|
||||
*/
|
||||
static INLINE struct dl_list * DL_ListRemove(struct dl_list * pDel) {
|
||||
pDel->pNext->pPrev = pDel->pPrev;
|
||||
pDel->pPrev->pNext = pDel->pNext;
|
||||
/* point back to itself just to be safe, incase remove is called again */
|
||||
pDel->pNext = pDel;
|
||||
pDel->pPrev = pDel;
|
||||
return pDel;
|
||||
}
|
||||
|
||||
/*
|
||||
* DL_ListRemoveItemFromHead - get a list item from the head
|
||||
*/
|
||||
static INLINE struct dl_list * DL_ListRemoveItemFromHead(struct dl_list * pList) {
|
||||
struct dl_list * pItem = NULL;
|
||||
if (pList->pNext != pList) {
|
||||
pItem = pList->pNext;
|
||||
/* remove the first item from head */
|
||||
DL_ListRemove(pItem);
|
||||
}
|
||||
return pItem;
|
||||
}
|
||||
|
||||
static INLINE struct dl_list * DL_ListRemoveItemFromTail(struct dl_list * pList) {
|
||||
struct dl_list * pItem = NULL;
|
||||
if (pList->pPrev != pList) {
|
||||
pItem = pList->pPrev;
|
||||
/* remove the item from tail */
|
||||
DL_ListRemove(pItem);
|
||||
}
|
||||
return pItem;
|
||||
}
|
||||
|
||||
/* transfer src list items to the tail of the destination list */
|
||||
static INLINE void DL_ListTransferItemsToTail(struct dl_list * pDest, struct dl_list * pSrc) {
|
||||
/* only concatenate if src is not empty */
|
||||
if (!DL_LIST_IS_EMPTY(pSrc)) {
|
||||
/* cut out circular list in src and re-attach to end of dest */
|
||||
pSrc->pPrev->pNext = pDest;
|
||||
pSrc->pNext->pPrev = pDest->pPrev;
|
||||
pDest->pPrev->pNext = pSrc->pNext;
|
||||
pDest->pPrev = pSrc->pPrev;
|
||||
/* terminate src list, it is now empty */
|
||||
pSrc->pPrev = pSrc;
|
||||
pSrc->pNext = pSrc;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __DL_LIST_H___ */
|
|
@ -1,65 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="dset_api.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Host-side DataSet API.
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _DSET_API_H_
|
||||
#define _DSET_API_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*
|
||||
* Host-side DataSet support is optional, and is not
|
||||
* currently required for correct operation. To disable
|
||||
* Host-side DataSet support, set this to 0.
|
||||
*/
|
||||
#ifndef CONFIG_HOST_DSET_SUPPORT
|
||||
#define CONFIG_HOST_DSET_SUPPORT 1
|
||||
#endif
|
||||
|
||||
/* Called to send a DataSet Open Reply back to the Target. */
|
||||
int wmi_dset_open_reply(struct wmi_t *wmip,
|
||||
u32 status,
|
||||
u32 access_cookie,
|
||||
u32 size,
|
||||
u32 version,
|
||||
u32 targ_handle,
|
||||
u32 targ_reply_fn,
|
||||
u32 targ_reply_arg);
|
||||
|
||||
/* Called to send a DataSet Data Reply back to the Target. */
|
||||
int wmi_dset_data_reply(struct wmi_t *wmip,
|
||||
u32 status,
|
||||
u8 *host_buf,
|
||||
u32 length,
|
||||
u32 targ_buf,
|
||||
u32 targ_reply_fn,
|
||||
u32 targ_reply_arg);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
#endif /* _DSET_API_H_ */
|
|
@ -1,259 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _HCI_TRANSPORT_API_H_
|
||||
#define _HCI_TRANSPORT_API_H_
|
||||
|
||||
/* Bluetooth HCI packets are stored in HTC packet containers */
|
||||
#include "htc_packet.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
typedef void *HCI_TRANSPORT_HANDLE;
|
||||
|
||||
typedef HTC_ENDPOINT_ID HCI_TRANSPORT_PACKET_TYPE;
|
||||
|
||||
/* we map each HCI packet class to a static Endpoint ID */
|
||||
#define HCI_COMMAND_TYPE ENDPOINT_1
|
||||
#define HCI_EVENT_TYPE ENDPOINT_2
|
||||
#define HCI_ACL_TYPE ENDPOINT_3
|
||||
#define HCI_PACKET_INVALID ENDPOINT_MAX
|
||||
|
||||
#define HCI_GET_PACKET_TYPE(pP) (pP)->Endpoint
|
||||
#define HCI_SET_PACKET_TYPE(pP,s) (pP)->Endpoint = (s)
|
||||
|
||||
/* callback when an HCI packet was completely sent */
|
||||
typedef void (*HCI_TRANSPORT_SEND_PKT_COMPLETE)(void *, struct htc_packet *);
|
||||
/* callback when an HCI packet is received */
|
||||
typedef void (*HCI_TRANSPORT_RECV_PKT)(void *, struct htc_packet *);
|
||||
/* Optional receive buffer re-fill callback,
|
||||
* On some OSes (like Linux) packets are allocated from a global pool and indicated up
|
||||
* to the network stack. The driver never gets the packets back from the OS. For these OSes
|
||||
* a refill callback can be used to allocate and re-queue buffers into HTC.
|
||||
* A refill callback is used for the reception of ACL and EVENT packets. The caller must
|
||||
* set the watermark trigger point to cause a refill.
|
||||
*/
|
||||
typedef void (*HCI_TRANSPORT_RECV_REFILL)(void *, HCI_TRANSPORT_PACKET_TYPE Type, int BuffersAvailable);
|
||||
/* Optional receive packet refill
|
||||
* On some systems packet buffers are an extremely limited resource. Rather than
|
||||
* queue largest-possible-sized buffers to the HCI bridge, some systems would rather
|
||||
* allocate a specific size as the packet is received. The trade off is
|
||||
* slightly more processing (callback invoked for each RX packet)
|
||||
* for the benefit of committing fewer buffer resources into the bridge.
|
||||
*
|
||||
* The callback is provided the length of the pending packet to fetch. This includes the
|
||||
* full transport header, HCI header, plus the length of payload. The callback can return a pointer to
|
||||
* the allocated HTC packet for immediate use.
|
||||
*
|
||||
* NOTE*** This callback is mutually exclusive with the the refill callback above.
|
||||
*
|
||||
* */
|
||||
typedef struct htc_packet *(*HCI_TRANSPORT_RECV_ALLOC)(void *, HCI_TRANSPORT_PACKET_TYPE Type, int Length);
|
||||
|
||||
typedef enum _HCI_SEND_FULL_ACTION {
|
||||
HCI_SEND_FULL_KEEP = 0, /* packet that overflowed should be kept in the queue */
|
||||
HCI_SEND_FULL_DROP = 1, /* packet that overflowed should be dropped */
|
||||
} HCI_SEND_FULL_ACTION;
|
||||
|
||||
/* callback when an HCI send queue exceeds the caller's MaxSendQueueDepth threshold,
|
||||
* the callback must return the send full action to take (either DROP or KEEP) */
|
||||
typedef HCI_SEND_FULL_ACTION (*HCI_TRANSPORT_SEND_FULL)(void *, struct htc_packet *);
|
||||
|
||||
struct hci_transport_properties {
|
||||
int HeadRoom; /* number of bytes in front of HCI packet for header space */
|
||||
int TailRoom; /* number of bytes at the end of the HCI packet for tail space */
|
||||
int IOBlockPad; /* I/O block padding required (always a power of 2) */
|
||||
};
|
||||
|
||||
struct hci_transport_config_info {
|
||||
int ACLRecvBufferWaterMark; /* low watermark to trigger recv refill */
|
||||
int EventRecvBufferWaterMark; /* low watermark to trigger recv refill */
|
||||
int MaxSendQueueDepth; /* max number of packets in the single send queue */
|
||||
void *pContext; /* context for all callbacks */
|
||||
void (*TransportFailure)(void *pContext, int Status); /* transport failure callback */
|
||||
int (*TransportReady)(HCI_TRANSPORT_HANDLE, struct hci_transport_properties *,void *pContext); /* transport is ready */
|
||||
void (*TransportRemoved)(void *pContext); /* transport was removed */
|
||||
/* packet processing callbacks */
|
||||
HCI_TRANSPORT_SEND_PKT_COMPLETE pHCISendComplete;
|
||||
HCI_TRANSPORT_RECV_PKT pHCIPktRecv;
|
||||
HCI_TRANSPORT_RECV_REFILL pHCIPktRecvRefill;
|
||||
HCI_TRANSPORT_RECV_ALLOC pHCIPktRecvAlloc;
|
||||
HCI_TRANSPORT_SEND_FULL pHCISendFull;
|
||||
};
|
||||
|
||||
/* ------ Function Prototypes ------ */
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Attach to the HCI transport module
|
||||
@function name: HCI_TransportAttach
|
||||
@input: HTCHandle - HTC handle (see HTC apis)
|
||||
pInfo - initialization information
|
||||
@output:
|
||||
@return: HCI_TRANSPORT_HANDLE on success, NULL on failure
|
||||
@notes: The HTC module provides HCI transport services.
|
||||
@example:
|
||||
@see also: HCI_TransportDetach
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
HCI_TRANSPORT_HANDLE HCI_TransportAttach(void *HTCHandle, struct hci_transport_config_info *pInfo);
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Detach from the HCI transport module
|
||||
@function name: HCI_TransportDetach
|
||||
@input: HciTrans - HCI transport handle
|
||||
pInfo - initialization information
|
||||
@output:
|
||||
@return:
|
||||
@notes:
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
void HCI_TransportDetach(HCI_TRANSPORT_HANDLE HciTrans);
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Add receive packets to the HCI transport
|
||||
@function name: HCI_TransportAddReceivePkts
|
||||
@input: HciTrans - HCI transport handle
|
||||
pQueue - a queue holding one or more packets
|
||||
@output:
|
||||
@return: 0 on success
|
||||
@notes: user must supply HTC packets for capturing incomming HCI packets. The caller
|
||||
must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
|
||||
macro. Each packet in the queue must be of the same type and length
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HCI_TransportAddReceivePkts(HCI_TRANSPORT_HANDLE HciTrans, struct htc_packet_queue *pQueue);
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Send an HCI packet packet
|
||||
@function name: HCI_TransportSendPkt
|
||||
@input: HciTrans - HCI transport handle
|
||||
pPacket - packet to send
|
||||
Synchronous - send the packet synchronously (blocking)
|
||||
@output:
|
||||
@return: 0
|
||||
@notes: Caller must initialize packet using SET_HTC_PACKET_INFO_TX() and
|
||||
HCI_SET_PACKET_TYPE() macros to prepare the packet.
|
||||
If Synchronous is set to false the call is fully asynchronous. On error or completion,
|
||||
the registered send complete callback will be called.
|
||||
If Synchronous is set to true, the call will block until the packet is sent, if the
|
||||
interface cannot send the packet within a 2 second timeout, the function will return
|
||||
the failure code : A_EBUSY.
|
||||
|
||||
Synchronous Mode should only be used at start-up to initialize the HCI device using
|
||||
custom HCI commands. It should NOT be mixed with Asynchronous operations. Mixed synchronous
|
||||
and asynchronous operation behavior is undefined.
|
||||
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HCI_TransportSendPkt(HCI_TRANSPORT_HANDLE HciTrans, struct htc_packet *pPacket, bool Synchronous);
|
||||
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Stop HCI transport
|
||||
@function name: HCI_TransportStop
|
||||
@input: HciTrans - hci transport handle
|
||||
@output:
|
||||
@return:
|
||||
@notes: HCI transport communication will be halted. All receive and pending TX packets will
|
||||
be flushed.
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
void HCI_TransportStop(HCI_TRANSPORT_HANDLE HciTrans);
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Start the HCI transport
|
||||
@function name: HCI_TransportStart
|
||||
@input: HciTrans - hci transport handle
|
||||
@output:
|
||||
@return: 0 on success
|
||||
@notes: HCI transport communication will begin, the caller can expect the arrival
|
||||
of HCI recv packets as soon as this call returns.
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HCI_TransportStart(HCI_TRANSPORT_HANDLE HciTrans);
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Enable or Disable Asynchronous Recv
|
||||
@function name: HCI_TransportEnableDisableAsyncRecv
|
||||
@input: HciTrans - hci transport handle
|
||||
Enable - enable or disable asynchronous recv
|
||||
@output:
|
||||
@return: 0 on success
|
||||
@notes: This API must be called when HCI recv is handled synchronously
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HCI_TransportEnableDisableAsyncRecv(HCI_TRANSPORT_HANDLE HciTrans, bool Enable);
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Receive an event packet from the HCI transport synchronously using polling
|
||||
@function name: HCI_TransportRecvHCIEventSync
|
||||
@input: HciTrans - hci transport handle
|
||||
pPacket - HTC packet to hold the recv data
|
||||
MaxPollMS - maximum polling duration in Milliseconds;
|
||||
@output:
|
||||
@return: 0 on success
|
||||
@notes: This API should be used only during HCI device initialization, the caller must call
|
||||
HCI_TransportEnableDisableAsyncRecv with Enable=false prior to using this API.
|
||||
This API will only capture HCI Event packets.
|
||||
@example:
|
||||
@see also: HCI_TransportEnableDisableAsyncRecv
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HCI_TransportRecvHCIEventSync(HCI_TRANSPORT_HANDLE HciTrans,
|
||||
struct htc_packet *pPacket,
|
||||
int MaxPollMS);
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Set the desired baud rate for the underlying transport layer
|
||||
@function name: HCI_TransportSetBaudRate
|
||||
@input: HciTrans - hci transport handle
|
||||
Baud - baud rate in bps
|
||||
@output:
|
||||
@return: 0 on success
|
||||
@notes: This API should be used only after HCI device initialization
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HCI_TransportSetBaudRate(HCI_TRANSPORT_HANDLE HciTrans, u32 Baud);
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Enable/Disable HCI Transport Power Management
|
||||
@function name: HCI_TransportEnablePowerMgmt
|
||||
@input: HciTrans - hci transport handle
|
||||
Enable - 1 = Enable, 0 = Disable
|
||||
@output:
|
||||
@return: 0 on success
|
||||
@notes:
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HCI_TransportEnablePowerMgmt(HCI_TRANSPORT_HANDLE HciTrans, bool Enable);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HCI_TRANSPORT_API_H_ */
|
|
@ -1,456 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="hif.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// HIF specific declarations and prototypes
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _HIF_H_
|
||||
#define _HIF_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Header files */
|
||||
#include "a_config.h"
|
||||
#include "athdefs.h"
|
||||
#include "a_osapi.h"
|
||||
#include "dl_list.h"
|
||||
|
||||
|
||||
typedef struct htc_callbacks HTC_CALLBACKS;
|
||||
struct hif_device;
|
||||
|
||||
/*
|
||||
* direction - Direction of transfer (HIF_READ/HIF_WRITE).
|
||||
*/
|
||||
#define HIF_READ 0x00000001
|
||||
#define HIF_WRITE 0x00000002
|
||||
#define HIF_DIR_MASK (HIF_READ | HIF_WRITE)
|
||||
|
||||
/*
|
||||
* type - An interface may support different kind of read/write commands.
|
||||
* For example: SDIO supports CMD52/CMD53s. In case of MSIO it
|
||||
* translates to using different kinds of TPCs. The command type
|
||||
* is thus divided into a basic and an extended command and can
|
||||
* be specified using HIF_BASIC_IO/HIF_EXTENDED_IO.
|
||||
*/
|
||||
#define HIF_BASIC_IO 0x00000004
|
||||
#define HIF_EXTENDED_IO 0x00000008
|
||||
#define HIF_TYPE_MASK (HIF_BASIC_IO | HIF_EXTENDED_IO)
|
||||
|
||||
/*
|
||||
* emode - This indicates the whether the command is to be executed in a
|
||||
* blocking or non-blocking fashion (HIF_SYNCHRONOUS/
|
||||
* HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
|
||||
* implemented using the asynchronous mode allowing the the bus
|
||||
* driver to indicate the completion of operation through the
|
||||
* registered callback routine. The requirement primarily comes
|
||||
* from the contexts these operations get called from (a driver's
|
||||
* transmit context or the ISR context in case of receive).
|
||||
* Support for both of these modes is essential.
|
||||
*/
|
||||
#define HIF_SYNCHRONOUS 0x00000010
|
||||
#define HIF_ASYNCHRONOUS 0x00000020
|
||||
#define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
|
||||
|
||||
/*
|
||||
* dmode - An interface may support different kinds of commands based on
|
||||
* the tradeoff between the amount of data it can carry and the
|
||||
* setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
|
||||
* HIF_BLOCK_BASIS). In case of latter, the data is rounded off
|
||||
* to the nearest block size by padding. The size of the block is
|
||||
* configurable at compile time using the HIF_BLOCK_SIZE and is
|
||||
* negotiated with the target during initialization after the
|
||||
* AR6000 interrupts are enabled.
|
||||
*/
|
||||
#define HIF_BYTE_BASIS 0x00000040
|
||||
#define HIF_BLOCK_BASIS 0x00000080
|
||||
#define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
|
||||
|
||||
/*
|
||||
* amode - This indicates if the address has to be incremented on AR6000
|
||||
* after every read/write operation (HIF?FIXED_ADDRESS/
|
||||
* HIF_INCREMENTAL_ADDRESS).
|
||||
*/
|
||||
#define HIF_FIXED_ADDRESS 0x00000100
|
||||
#define HIF_INCREMENTAL_ADDRESS 0x00000200
|
||||
#define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)
|
||||
|
||||
#define HIF_WR_ASYNC_BYTE_FIX \
|
||||
(HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
|
||||
#define HIF_WR_ASYNC_BYTE_INC \
|
||||
(HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
|
||||
#define HIF_WR_ASYNC_BLOCK_INC \
|
||||
(HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
|
||||
#define HIF_WR_SYNC_BYTE_FIX \
|
||||
(HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
|
||||
#define HIF_WR_SYNC_BYTE_INC \
|
||||
(HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
|
||||
#define HIF_WR_SYNC_BLOCK_INC \
|
||||
(HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
|
||||
#define HIF_WR_ASYNC_BLOCK_FIX \
|
||||
(HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
|
||||
#define HIF_WR_SYNC_BLOCK_FIX \
|
||||
(HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
|
||||
#define HIF_RD_SYNC_BYTE_INC \
|
||||
(HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
|
||||
#define HIF_RD_SYNC_BYTE_FIX \
|
||||
(HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
|
||||
#define HIF_RD_ASYNC_BYTE_FIX \
|
||||
(HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
|
||||
#define HIF_RD_ASYNC_BLOCK_FIX \
|
||||
(HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
|
||||
#define HIF_RD_ASYNC_BYTE_INC \
|
||||
(HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
|
||||
#define HIF_RD_ASYNC_BLOCK_INC \
|
||||
(HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
|
||||
#define HIF_RD_SYNC_BLOCK_INC \
|
||||
(HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
|
||||
#define HIF_RD_SYNC_BLOCK_FIX \
|
||||
(HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
|
||||
|
||||
typedef enum {
|
||||
HIF_DEVICE_POWER_STATE = 0,
|
||||
HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
|
||||
HIF_DEVICE_GET_MBOX_ADDR,
|
||||
HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
|
||||
HIF_DEVICE_GET_IRQ_PROC_MODE,
|
||||
HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
|
||||
HIF_DEVICE_POWER_STATE_CHANGE,
|
||||
HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
|
||||
HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
|
||||
HIF_DEVICE_GET_OS_DEVICE,
|
||||
HIF_DEVICE_DEBUG_BUS_STATE,
|
||||
} HIF_DEVICE_CONFIG_OPCODE;
|
||||
|
||||
/*
|
||||
* HIF CONFIGURE definitions:
|
||||
*
|
||||
* HIF_DEVICE_GET_MBOX_BLOCK_SIZE
|
||||
* input : none
|
||||
* output : array of 4 u32s
|
||||
* notes: block size is returned for each mailbox (4)
|
||||
*
|
||||
* HIF_DEVICE_GET_MBOX_ADDR
|
||||
* input : none
|
||||
* output : struct hif_device_mbox_info
|
||||
* notes:
|
||||
*
|
||||
* HIF_DEVICE_GET_PENDING_EVENTS_FUNC
|
||||
* input : none
|
||||
* output: HIF_PENDING_EVENTS_FUNC function pointer
|
||||
* notes: this is optional for the HIF layer, if the request is
|
||||
* not handled then it indicates that the upper layer can use
|
||||
* the standard device methods to get pending events (IRQs, mailbox messages etc..)
|
||||
* otherwise it can call the function pointer to check pending events.
|
||||
*
|
||||
* HIF_DEVICE_GET_IRQ_PROC_MODE
|
||||
* input : none
|
||||
* output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode)
|
||||
* note: the hif layer interfaces with the underlying OS-specific bus driver. The HIF
|
||||
* layer can report whether IRQ processing is requires synchronous behavior or
|
||||
* can be processed using asynchronous bus requests (typically faster).
|
||||
*
|
||||
* HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC
|
||||
* input :
|
||||
* output : HIF_MASK_UNMASK_RECV_EVENT function pointer
|
||||
* notes: this is optional for the HIF layer. The HIF layer may require a special mechanism
|
||||
* to mask receive message events. The upper layer can call this pointer when it needs
|
||||
* to mask/unmask receive events (in case it runs out of buffers).
|
||||
*
|
||||
* HIF_DEVICE_POWER_STATE_CHANGE
|
||||
*
|
||||
* input : HIF_DEVICE_POWER_CHANGE_TYPE
|
||||
* output : none
|
||||
* note: this is optional for the HIF layer. The HIF layer can handle power on/off state change
|
||||
* requests in an interconnect specific way. This is highly OS and bus driver dependent.
|
||||
* The caller must guarantee that no HIF read/write requests will be made after the device
|
||||
* is powered down.
|
||||
*
|
||||
* HIF_DEVICE_GET_IRQ_YIELD_PARAMS
|
||||
*
|
||||
* input : none
|
||||
* output : struct hif_device_irq_yield_params
|
||||
* note: This query checks if the HIF layer wishes to impose a processing yield count for the DSR handler.
|
||||
* The DSR callback handler will exit after a fixed number of RX packets or events are processed.
|
||||
* This query is only made if the device reports an IRQ processing mode of HIF_DEVICE_IRQ_SYNC_ONLY.
|
||||
* The HIF implementation can ignore this command if it does not desire the DSR callback to yield.
|
||||
* The HIF layer can indicate the maximum number of IRQ processing units (RX packets) before the
|
||||
* DSR handler callback must yield and return control back to the HIF layer. When a yield limit is
|
||||
* used the DSR callback will not call HIFAckInterrupts() as it would normally do before returning.
|
||||
* The HIF implementation that requires a yield count must call HIFAckInterrupt() when it is prepared
|
||||
* to process interrupts again.
|
||||
*
|
||||
* HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT
|
||||
* input : none
|
||||
* output : struct hif_device_scatter_support_info
|
||||
* note: This query checks if the HIF layer implements the SCATTER request interface. Scatter requests
|
||||
* allows upper layers to submit mailbox I/O operations using a list of buffers. This is useful for
|
||||
* multi-message transfers that can better utilize the bus interconnect.
|
||||
*
|
||||
*
|
||||
* HIF_DEVICE_GET_OS_DEVICE
|
||||
* intput : none
|
||||
* output : struct hif_device_os_device_info;
|
||||
* note: On some operating systems, the HIF layer has a parent device object for the bus. This object
|
||||
* may be required to register certain types of logical devices.
|
||||
*
|
||||
* HIF_DEVICE_DEBUG_BUS_STATE
|
||||
* input : none
|
||||
* output : none
|
||||
* note: This configure option triggers the HIF interface to dump as much bus interface state. This
|
||||
* configuration request is optional (No-OP on some HIF implementations)
|
||||
*
|
||||
*/
|
||||
|
||||
struct hif_mbox_properties {
|
||||
u32 ExtendedAddress; /* extended address for larger writes */
|
||||
u32 ExtendedSize;
|
||||
};
|
||||
|
||||
#define HIF_MBOX_FLAG_NO_BUNDLING (1 << 0) /* do not allow bundling over the mailbox */
|
||||
|
||||
typedef enum _MBOX_BUF_IF_TYPE {
|
||||
MBOX_BUS_IF_SDIO = 0,
|
||||
MBOX_BUS_IF_SPI = 1,
|
||||
} MBOX_BUF_IF_TYPE;
|
||||
|
||||
struct hif_device_mbox_info {
|
||||
u32 MboxAddresses[4]; /* must be first element for legacy HIFs that return the address in
|
||||
and ARRAY of 32-bit words */
|
||||
|
||||
/* the following describe extended mailbox properties */
|
||||
struct hif_mbox_properties MboxProp[4];
|
||||
/* if the HIF supports the GMbox extended address region it can report it
|
||||
* here, some interfaces cannot support the GMBOX address range and not set this */
|
||||
u32 GMboxAddress;
|
||||
u32 GMboxSize;
|
||||
u32 Flags; /* flags to describe mbox behavior or usage */
|
||||
MBOX_BUF_IF_TYPE MboxBusIFType; /* mailbox bus interface type */
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
HIF_DEVICE_IRQ_SYNC_ONLY, /* for HIF implementations that require the DSR to process all
|
||||
interrupts before returning */
|
||||
HIF_DEVICE_IRQ_ASYNC_SYNC, /* for HIF implementations that allow DSR to process interrupts
|
||||
using ASYNC I/O (that is HIFAckInterrupt can be called at a
|
||||
later time */
|
||||
} HIF_DEVICE_IRQ_PROCESSING_MODE;
|
||||
|
||||
typedef enum {
|
||||
HIF_DEVICE_POWER_UP, /* HIF layer should power up interface and/or module */
|
||||
HIF_DEVICE_POWER_DOWN, /* HIF layer should initiate bus-specific measures to minimize power */
|
||||
HIF_DEVICE_POWER_CUT /* HIF layer should initiate bus-specific AND/OR platform-specific measures
|
||||
to completely power-off the module and associated hardware (i.e. cut power supplies)
|
||||
*/
|
||||
} HIF_DEVICE_POWER_CHANGE_TYPE;
|
||||
|
||||
struct hif_device_irq_yield_params {
|
||||
int RecvPacketYieldCount; /* max number of packets to force DSR to return */
|
||||
};
|
||||
|
||||
|
||||
struct hif_scatter_item {
|
||||
u8 *pBuffer; /* CPU accessible address of buffer */
|
||||
int Length; /* length of transfer to/from this buffer */
|
||||
void *pCallerContexts[2]; /* space for caller to insert a context associated with this item */
|
||||
};
|
||||
|
||||
struct hif_scatter_req;
|
||||
typedef void ( *HIF_SCATTER_COMP_CB)(struct hif_scatter_req *);
|
||||
|
||||
typedef enum _HIF_SCATTER_METHOD {
|
||||
HIF_SCATTER_NONE = 0,
|
||||
HIF_SCATTER_DMA_REAL, /* Real SG support no restrictions */
|
||||
HIF_SCATTER_DMA_BOUNCE, /* Uses SG DMA but HIF layer uses an internal bounce buffer */
|
||||
} HIF_SCATTER_METHOD;
|
||||
|
||||
struct hif_scatter_req {
|
||||
struct dl_list ListLink; /* link management */
|
||||
u32 Address; /* address for the read/write operation */
|
||||
u32 Request; /* request flags */
|
||||
u32 TotalLength; /* total length of entire transfer */
|
||||
u32 CallerFlags; /* caller specific flags can be stored here */
|
||||
HIF_SCATTER_COMP_CB CompletionRoutine; /* completion routine set by caller */
|
||||
int CompletionStatus; /* status of completion */
|
||||
void *Context; /* caller context for this request */
|
||||
int ValidScatterEntries; /* number of valid entries set by caller */
|
||||
HIF_SCATTER_METHOD ScatterMethod; /* scatter method handled by HIF */
|
||||
void *HIFPrivate[4]; /* HIF private area */
|
||||
u8 *pScatterBounceBuffer; /* bounce buffer for upper layers to copy to/from */
|
||||
struct hif_scatter_item ScatterList[1]; /* start of scatter list */
|
||||
};
|
||||
|
||||
typedef struct hif_scatter_req * ( *HIF_ALLOCATE_SCATTER_REQUEST)(struct hif_device *device);
|
||||
typedef void ( *HIF_FREE_SCATTER_REQUEST)(struct hif_device *device, struct hif_scatter_req *request);
|
||||
typedef int ( *HIF_READWRITE_SCATTER)(struct hif_device *device, struct hif_scatter_req *request);
|
||||
|
||||
struct hif_device_scatter_support_info {
|
||||
/* information returned from HIF layer */
|
||||
HIF_ALLOCATE_SCATTER_REQUEST pAllocateReqFunc;
|
||||
HIF_FREE_SCATTER_REQUEST pFreeReqFunc;
|
||||
HIF_READWRITE_SCATTER pReadWriteScatterFunc;
|
||||
int MaxScatterEntries;
|
||||
int MaxTransferSizePerScatterReq;
|
||||
};
|
||||
|
||||
struct hif_device_os_device_info {
|
||||
void *pOSDevice;
|
||||
};
|
||||
|
||||
#define HIF_MAX_DEVICES 1
|
||||
|
||||
struct htc_callbacks {
|
||||
void *context; /* context to pass to the dsrhandler
|
||||
note : rwCompletionHandler is provided the context passed to HIFReadWrite */
|
||||
int (* rwCompletionHandler)(void *rwContext, int status);
|
||||
int (* dsrHandler)(void *context);
|
||||
};
|
||||
|
||||
typedef struct osdrv_callbacks {
|
||||
void *context; /* context to pass for all callbacks except deviceRemovedHandler
|
||||
the deviceRemovedHandler is only called if the device is claimed */
|
||||
int (* deviceInsertedHandler)(void *context, void *hif_handle);
|
||||
int (* deviceRemovedHandler)(void *claimedContext, void *hif_handle);
|
||||
int (* deviceSuspendHandler)(void *context);
|
||||
int (* deviceResumeHandler)(void *context);
|
||||
int (* deviceWakeupHandler)(void *context);
|
||||
int (* devicePowerChangeHandler)(void *context, HIF_DEVICE_POWER_CHANGE_TYPE config);
|
||||
} OSDRV_CALLBACKS;
|
||||
|
||||
#define HIF_OTHER_EVENTS (1 << 0) /* other interrupts (non-Recv) are pending, host
|
||||
needs to read the register table to figure out what */
|
||||
#define HIF_RECV_MSG_AVAIL (1 << 1) /* pending recv packet */
|
||||
|
||||
struct hif_pending_events_info {
|
||||
u32 Events;
|
||||
u32 LookAhead;
|
||||
u32 AvailableRecvBytes;
|
||||
#ifdef THREAD_X
|
||||
u32 Polling;
|
||||
u32 INT_CAUSE_REG;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* function to get pending events , some HIF modules use special mechanisms
|
||||
* to detect packet available and other interrupts */
|
||||
typedef int ( *HIF_PENDING_EVENTS_FUNC)(struct hif_device *device,
|
||||
struct hif_pending_events_info *pEvents,
|
||||
void *AsyncContext);
|
||||
|
||||
#define HIF_MASK_RECV true
|
||||
#define HIF_UNMASK_RECV false
|
||||
/* function to mask recv events */
|
||||
typedef int ( *HIF_MASK_UNMASK_RECV_EVENT)(struct hif_device *device,
|
||||
bool Mask,
|
||||
void *AsyncContext);
|
||||
|
||||
|
||||
/*
|
||||
* This API is used to perform any global initialization of the HIF layer
|
||||
* and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer
|
||||
*
|
||||
*/
|
||||
int HIFInit(OSDRV_CALLBACKS *callbacks);
|
||||
|
||||
/* This API claims the HIF device and provides a context for handling removal.
|
||||
* The device removal callback is only called when the OSDRV layer claims
|
||||
* a device. The claimed context must be non-NULL */
|
||||
void HIFClaimDevice(struct hif_device *device, void *claimedContext);
|
||||
/* release the claimed device */
|
||||
void HIFReleaseDevice(struct hif_device *device);
|
||||
|
||||
/* This API allows the HTC layer to attach to the HIF device */
|
||||
int HIFAttachHTC(struct hif_device *device, HTC_CALLBACKS *callbacks);
|
||||
/* This API detaches the HTC layer from the HIF device */
|
||||
void HIFDetachHTC(struct hif_device *device);
|
||||
|
||||
/*
|
||||
* This API is used to provide the read/write interface over the specific bus
|
||||
* interface.
|
||||
* address - Starting address in the AR6000's address space. For mailbox
|
||||
* writes, it refers to the start of the mbox boundary. It should
|
||||
* be ensured that the last byte falls on the mailbox's EOM. For
|
||||
* mailbox reads, it refers to the end of the mbox boundary.
|
||||
* buffer - Pointer to the buffer containg the data to be transmitted or
|
||||
* received.
|
||||
* length - Amount of data to be transmitted or received.
|
||||
* request - Characterizes the attributes of the command.
|
||||
*/
|
||||
int
|
||||
HIFReadWrite(struct hif_device *device,
|
||||
u32 address,
|
||||
u8 *buffer,
|
||||
u32 length,
|
||||
u32 request,
|
||||
void *context);
|
||||
|
||||
/*
|
||||
* This can be initiated from the unload driver context when the OSDRV layer has no more use for
|
||||
* the device.
|
||||
*/
|
||||
void HIFShutDownDevice(struct hif_device *device);
|
||||
|
||||
/*
|
||||
* This should translate to an acknowledgment to the bus driver indicating that
|
||||
* the previous interrupt request has been serviced and the all the relevant
|
||||
* sources have been cleared. HTC is ready to process more interrupts.
|
||||
* This should prevent the bus driver from raising an interrupt unless the
|
||||
* previous one has been serviced and acknowledged using the previous API.
|
||||
*/
|
||||
void HIFAckInterrupt(struct hif_device *device);
|
||||
|
||||
void HIFMaskInterrupt(struct hif_device *device);
|
||||
|
||||
void HIFUnMaskInterrupt(struct hif_device *device);
|
||||
|
||||
#ifdef THREAD_X
|
||||
/*
|
||||
* This set of functions are to be used by the bus driver to notify
|
||||
* the HIF module about various events.
|
||||
* These are not implemented if the bus driver provides an alternative
|
||||
* way for this notification though callbacks for instance.
|
||||
*/
|
||||
int HIFInsertEventNotify(void);
|
||||
|
||||
int HIFRemoveEventNotify(void);
|
||||
|
||||
int HIFIRQEventNotify(void);
|
||||
|
||||
int HIFRWCompleteEventNotify(void);
|
||||
#endif
|
||||
|
||||
int
|
||||
HIFConfigureDevice(struct hif_device *device, HIF_DEVICE_CONFIG_OPCODE opcode,
|
||||
void *config, u32 configLen);
|
||||
|
||||
/*
|
||||
* This API wait for the remaining MBOX messages to be drained
|
||||
* This should be moved to HTC AR6K layer
|
||||
*/
|
||||
int hifWaitForPendingRecv(struct hif_device *device);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HIF_H_ */
|
|
@ -1,52 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="host_version.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// This file contains version information for the sample host driver for the
|
||||
// AR6000 chip
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _HOST_VERSION_H_
|
||||
#define _HOST_VERSION_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <AR6002/AR6K_version.h>
|
||||
|
||||
/*
|
||||
* The version number is made up of major, minor, patch and build
|
||||
* numbers. These are 16 bit numbers. The build and release script will
|
||||
* set the build number using a Perforce counter. Here the build number is
|
||||
* set to 9999 so that builds done without the build-release script are easily
|
||||
* identifiable.
|
||||
*/
|
||||
|
||||
#define ATH_SW_VER_MAJOR __VER_MAJOR_
|
||||
#define ATH_SW_VER_MINOR __VER_MINOR_
|
||||
#define ATH_SW_VER_PATCH __VER_PATCH_
|
||||
#define ATH_SW_VER_BUILD __BUILD_NUMBER_
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HOST_VERSION_H_ */
|
|
@ -1,575 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="htc_api.h" company="Atheros">
|
||||
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _HTC_API_H_
|
||||
#define _HTC_API_H_
|
||||
|
||||
#include "htc_packet.h"
|
||||
#include <htc.h>
|
||||
#include <htc_services.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* TODO.. for BMI */
|
||||
#define ENDPOINT1 0
|
||||
// TODO -remove me, but we have to fix BMI first
|
||||
#define HTC_MAILBOX_NUM_MAX 4
|
||||
|
||||
/* this is the amount of header room required by users of HTC */
|
||||
#define HTC_HEADER_LEN HTC_HDR_LENGTH
|
||||
|
||||
typedef void *HTC_HANDLE;
|
||||
|
||||
typedef u16 HTC_SERVICE_ID;
|
||||
|
||||
struct htc_init_info {
|
||||
void *pContext; /* context for target failure notification */
|
||||
void (*TargetFailure)(void *Instance, int Status);
|
||||
};
|
||||
|
||||
/* per service connection send completion */
|
||||
typedef void (*HTC_EP_SEND_PKT_COMPLETE)(void *,struct htc_packet *);
|
||||
/* per service connection callback when a plurality of packets have been sent
|
||||
* The struct htc_packet_queue is a temporary queue object (e.g. freed on return from the callback)
|
||||
* to hold a list of completed send packets.
|
||||
* If the handler cannot fully traverse the packet queue before returning, it should
|
||||
* transfer the items of the queue into the caller's private queue using:
|
||||
* HTC_PACKET_ENQUEUE() */
|
||||
typedef void (*HTC_EP_SEND_PKT_COMP_MULTIPLE)(void *,struct htc_packet_queue *);
|
||||
/* per service connection pkt received */
|
||||
typedef void (*HTC_EP_RECV_PKT)(void *,struct htc_packet *);
|
||||
/* per service connection callback when a plurality of packets are received
|
||||
* The struct htc_packet_queue is a temporary queue object (e.g. freed on return from the callback)
|
||||
* to hold a list of recv packets.
|
||||
* If the handler cannot fully traverse the packet queue before returning, it should
|
||||
* transfer the items of the queue into the caller's private queue using:
|
||||
* HTC_PACKET_ENQUEUE() */
|
||||
typedef void (*HTC_EP_RECV_PKT_MULTIPLE)(void *,struct htc_packet_queue *);
|
||||
|
||||
/* Optional per service connection receive buffer re-fill callback,
|
||||
* On some OSes (like Linux) packets are allocated from a global pool and indicated up
|
||||
* to the network stack. The driver never gets the packets back from the OS. For these OSes
|
||||
* a refill callback can be used to allocate and re-queue buffers into HTC.
|
||||
*
|
||||
* On other OSes, the network stack can call into the driver's OS-specifc "return_packet" handler and
|
||||
* the driver can re-queue these buffers into HTC. In this regard a refill callback is
|
||||
* unnecessary */
|
||||
typedef void (*HTC_EP_RECV_REFILL)(void *, HTC_ENDPOINT_ID Endpoint);
|
||||
|
||||
/* Optional per service connection receive buffer allocation callback.
|
||||
* On some systems packet buffers are an extremely limited resource. Rather than
|
||||
* queue largest-possible-sized buffers to HTC, some systems would rather
|
||||
* allocate a specific size as the packet is received. The trade off is
|
||||
* slightly more processing (callback invoked for each RX packet)
|
||||
* for the benefit of committing fewer buffer resources into HTC.
|
||||
*
|
||||
* The callback is provided the length of the pending packet to fetch. This includes the
|
||||
* HTC header length plus the length of payload. The callback can return a pointer to
|
||||
* the allocated HTC packet for immediate use.
|
||||
*
|
||||
* Alternatively a variant of this handler can be used to allocate large receive packets as needed.
|
||||
* For example an application can use the refill mechanism for normal packets and the recv-alloc mechanism to
|
||||
* handle the case where a large packet buffer is required. This can significantly reduce the
|
||||
* amount of "committed" memory used to receive packets.
|
||||
*
|
||||
* */
|
||||
typedef struct htc_packet *(*HTC_EP_RECV_ALLOC)(void *, HTC_ENDPOINT_ID Endpoint, int Length);
|
||||
|
||||
typedef enum _HTC_SEND_FULL_ACTION {
|
||||
HTC_SEND_FULL_KEEP = 0, /* packet that overflowed should be kept in the queue */
|
||||
HTC_SEND_FULL_DROP = 1, /* packet that overflowed should be dropped */
|
||||
} HTC_SEND_FULL_ACTION;
|
||||
|
||||
/* Optional per service connection callback when a send queue is full. This can occur if the
|
||||
* host continues queueing up TX packets faster than credits can arrive
|
||||
* To prevent the host (on some Oses like Linux) from continuously queueing packets
|
||||
* and consuming resources, this callback is provided so that that the host
|
||||
* can disable TX in the subsystem (i.e. network stack).
|
||||
* This callback is invoked for each packet that "overflows" the HTC queue. The callback can
|
||||
* determine whether the new packet that overflowed the queue can be kept (HTC_SEND_FULL_KEEP) or
|
||||
* dropped (HTC_SEND_FULL_DROP). If a packet is dropped, the EpTxComplete handler will be called
|
||||
* and the packet's status field will be set to A_NO_RESOURCE.
|
||||
* Other OSes require a "per-packet" indication for each completed TX packet, this
|
||||
* closed loop mechanism will prevent the network stack from overunning the NIC
|
||||
* The packet to keep or drop is passed for inspection to the registered handler the handler
|
||||
* must ONLY inspect the packet, it may not free or reclaim the packet. */
|
||||
typedef HTC_SEND_FULL_ACTION (*HTC_EP_SEND_QUEUE_FULL)(void *, struct htc_packet *pPacket);
|
||||
|
||||
struct htc_ep_callbacks {
|
||||
void *pContext; /* context for each callback */
|
||||
HTC_EP_SEND_PKT_COMPLETE EpTxComplete; /* tx completion callback for connected endpoint */
|
||||
HTC_EP_RECV_PKT EpRecv; /* receive callback for connected endpoint */
|
||||
HTC_EP_RECV_REFILL EpRecvRefill; /* OPTIONAL receive re-fill callback for connected endpoint */
|
||||
HTC_EP_SEND_QUEUE_FULL EpSendFull; /* OPTIONAL send full callback */
|
||||
HTC_EP_RECV_ALLOC EpRecvAlloc; /* OPTIONAL recv allocation callback */
|
||||
HTC_EP_RECV_ALLOC EpRecvAllocThresh; /* OPTIONAL recv allocation callback based on a threshold */
|
||||
HTC_EP_SEND_PKT_COMP_MULTIPLE EpTxCompleteMultiple; /* OPTIONAL completion handler for multiple complete
|
||||
indications (EpTxComplete must be NULL) */
|
||||
HTC_EP_RECV_PKT_MULTIPLE EpRecvPktMultiple; /* OPTIONAL completion handler for multiple
|
||||
recv packet indications (EpRecv must be NULL) */
|
||||
int RecvAllocThreshold; /* if EpRecvAllocThresh is non-NULL, HTC will compare the
|
||||
threshold value to the current recv packet length and invoke
|
||||
the EpRecvAllocThresh callback to acquire a packet buffer */
|
||||
int RecvRefillWaterMark; /* if a EpRecvRefill handler is provided, this value
|
||||
can be used to set a trigger refill callback
|
||||
when the recv queue drops below this value
|
||||
if set to 0, the refill is only called when packets
|
||||
are empty */
|
||||
};
|
||||
|
||||
/* service connection information */
|
||||
struct htc_service_connect_req {
|
||||
HTC_SERVICE_ID ServiceID; /* service ID to connect to */
|
||||
u16 ConnectionFlags; /* connection flags, see htc protocol definition */
|
||||
u8 *pMetaData; /* ptr to optional service-specific meta-data */
|
||||
u8 MetaDataLength; /* optional meta data length */
|
||||
struct htc_ep_callbacks EpCallbacks; /* endpoint callbacks */
|
||||
int MaxSendQueueDepth; /* maximum depth of any send queue */
|
||||
u32 LocalConnectionFlags; /* HTC flags for the host-side (local) connection */
|
||||
unsigned int MaxSendMsgSize; /* override max message size in send direction */
|
||||
};
|
||||
|
||||
#define HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING (1 << 0) /* enable send bundle padding for this endpoint */
|
||||
|
||||
/* service connection response information */
|
||||
struct htc_service_connect_resp {
|
||||
u8 *pMetaData; /* caller supplied buffer to optional meta-data */
|
||||
u8 BufferLength; /* length of caller supplied buffer */
|
||||
u8 ActualLength; /* actual length of meta data */
|
||||
HTC_ENDPOINT_ID Endpoint; /* endpoint to communicate over */
|
||||
unsigned int MaxMsgLength; /* max length of all messages over this endpoint */
|
||||
u8 ConnectRespCode; /* connect response code from target */
|
||||
};
|
||||
|
||||
/* endpoint distribution structure */
|
||||
struct htc_endpoint_credit_dist {
|
||||
struct htc_endpoint_credit_dist *pNext;
|
||||
struct htc_endpoint_credit_dist *pPrev;
|
||||
HTC_SERVICE_ID ServiceID; /* Service ID (set by HTC) */
|
||||
HTC_ENDPOINT_ID Endpoint; /* endpoint for this distribution struct (set by HTC) */
|
||||
u32 DistFlags; /* distribution flags, distribution function can
|
||||
set default activity using SET_EP_ACTIVE() macro */
|
||||
int TxCreditsNorm; /* credits for normal operation, anything above this
|
||||
indicates the endpoint is over-subscribed, this field
|
||||
is only relevant to the credit distribution function */
|
||||
int TxCreditsMin; /* floor for credit distribution, this field is
|
||||
only relevant to the credit distribution function */
|
||||
int TxCreditsAssigned; /* number of credits assigned to this EP, this field
|
||||
is only relevant to the credit dist function */
|
||||
int TxCredits; /* current credits available, this field is used by
|
||||
HTC to determine whether a message can be sent or
|
||||
must be queued */
|
||||
int TxCreditsToDist; /* pending credits to distribute on this endpoint, this
|
||||
is set by HTC when credit reports arrive.
|
||||
The credit distribution functions sets this to zero
|
||||
when it distributes the credits */
|
||||
int TxCreditsSeek; /* this is the number of credits that the current pending TX
|
||||
packet needs to transmit. This is set by HTC when
|
||||
and endpoint needs credits in order to transmit */
|
||||
int TxCreditSize; /* size in bytes of each credit (set by HTC) */
|
||||
int TxCreditsPerMaxMsg; /* credits required for a maximum sized messages (set by HTC) */
|
||||
void *pHTCReserved; /* reserved for HTC use */
|
||||
int TxQueueDepth; /* current depth of TX queue , i.e. messages waiting for credits
|
||||
This field is valid only when HTC_CREDIT_DIST_ACTIVITY_CHANGE
|
||||
or HTC_CREDIT_DIST_SEND_COMPLETE is indicated on an endpoint
|
||||
that has non-zero credits to recover
|
||||
*/
|
||||
};
|
||||
|
||||
#define HTC_EP_ACTIVE ((u32) (1u << 31))
|
||||
|
||||
/* macro to check if an endpoint has gone active, useful for credit
|
||||
* distributions */
|
||||
#define IS_EP_ACTIVE(epDist) ((epDist)->DistFlags & HTC_EP_ACTIVE)
|
||||
#define SET_EP_ACTIVE(epDist) (epDist)->DistFlags |= HTC_EP_ACTIVE
|
||||
|
||||
/* credit distibution code that is passed into the distrbution function,
|
||||
* there are mandatory and optional codes that must be handled */
|
||||
typedef enum _HTC_CREDIT_DIST_REASON {
|
||||
HTC_CREDIT_DIST_SEND_COMPLETE = 0, /* credits available as a result of completed
|
||||
send operations (MANDATORY) resulting in credit reports */
|
||||
HTC_CREDIT_DIST_ACTIVITY_CHANGE = 1, /* a change in endpoint activity occurred (OPTIONAL) */
|
||||
HTC_CREDIT_DIST_SEEK_CREDITS, /* an endpoint needs to "seek" credits (OPTIONAL) */
|
||||
HTC_DUMP_CREDIT_STATE /* for debugging, dump any state information that is kept by
|
||||
the distribution function */
|
||||
} HTC_CREDIT_DIST_REASON;
|
||||
|
||||
typedef void (*HTC_CREDIT_DIST_CALLBACK)(void *Context,
|
||||
struct htc_endpoint_credit_dist *pEPList,
|
||||
HTC_CREDIT_DIST_REASON Reason);
|
||||
|
||||
typedef void (*HTC_CREDIT_INIT_CALLBACK)(void *Context,
|
||||
struct htc_endpoint_credit_dist *pEPList,
|
||||
int TotalCredits);
|
||||
|
||||
/* endpoint statistics action */
|
||||
typedef enum _HTC_ENDPOINT_STAT_ACTION {
|
||||
HTC_EP_STAT_SAMPLE = 0, /* only read statistics */
|
||||
HTC_EP_STAT_SAMPLE_AND_CLEAR = 1, /* sample and immediately clear statistics */
|
||||
HTC_EP_STAT_CLEAR /* clear only */
|
||||
} HTC_ENDPOINT_STAT_ACTION;
|
||||
|
||||
/* endpoint statistics */
|
||||
struct htc_endpoint_stats {
|
||||
u32 TxCreditLowIndications; /* number of times the host set the credit-low flag in a send message on
|
||||
this endpoint */
|
||||
u32 TxIssued; /* running count of total TX packets issued */
|
||||
u32 TxPacketsBundled; /* running count of TX packets that were issued in bundles */
|
||||
u32 TxBundles; /* running count of TX bundles that were issued */
|
||||
u32 TxDropped; /* tx packets that were dropped */
|
||||
u32 TxCreditRpts; /* running count of total credit reports received for this endpoint */
|
||||
u32 TxCreditRptsFromRx; /* credit reports received from this endpoint's RX packets */
|
||||
u32 TxCreditRptsFromOther; /* credit reports received from RX packets of other endpoints */
|
||||
u32 TxCreditRptsFromEp0; /* credit reports received from endpoint 0 RX packets */
|
||||
u32 TxCreditsFromRx; /* count of credits received via Rx packets on this endpoint */
|
||||
u32 TxCreditsFromOther; /* count of credits received via another endpoint */
|
||||
u32 TxCreditsFromEp0; /* count of credits received via another endpoint */
|
||||
u32 TxCreditsConsummed; /* count of consummed credits */
|
||||
u32 TxCreditsReturned; /* count of credits returned */
|
||||
u32 RxReceived; /* count of RX packets received */
|
||||
u32 RxLookAheads; /* count of lookahead records
|
||||
found in messages received on this endpoint */
|
||||
u32 RxPacketsBundled; /* count of recv packets received in a bundle */
|
||||
u32 RxBundleLookAheads; /* count of number of bundled lookaheads */
|
||||
u32 RxBundleIndFromHdr; /* count of the number of bundle indications from the HTC header */
|
||||
u32 RxAllocThreshHit; /* count of the number of times the recv allocation threshold was hit */
|
||||
u32 RxAllocThreshBytes; /* total number of bytes */
|
||||
};
|
||||
|
||||
/* ------ Function Prototypes ------ */
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Create an instance of HTC over the underlying HIF device
|
||||
@function name: HTCCreate
|
||||
@input: HifDevice - hif device handle,
|
||||
pInfo - initialization information
|
||||
@output:
|
||||
@return: HTC_HANDLE on success, NULL on failure
|
||||
@notes:
|
||||
@example:
|
||||
@see also: HTCDestroy
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
HTC_HANDLE HTCCreate(void *HifDevice, struct htc_init_info *pInfo);
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Get the underlying HIF device handle
|
||||
@function name: HTCGetHifDevice
|
||||
@input: HTCHandle - handle passed into the AddInstance callback
|
||||
@output:
|
||||
@return: opaque HIF device handle usable in HIF API calls.
|
||||
@notes:
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
void *HTCGetHifDevice(HTC_HANDLE HTCHandle);
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Set credit distribution parameters
|
||||
@function name: HTCSetCreditDistribution
|
||||
@input: HTCHandle - HTC handle
|
||||
pCreditDistCont - caller supplied context to pass into distribution functions
|
||||
CreditDistFunc - Distribution function callback
|
||||
CreditDistInit - Credit Distribution initialization callback
|
||||
ServicePriorityOrder - Array containing list of service IDs, lowest index is highest
|
||||
priority
|
||||
ListLength - number of elements in ServicePriorityOrder
|
||||
@output:
|
||||
@return:
|
||||
@notes: The user can set a custom credit distribution function to handle special requirements
|
||||
for each endpoint. A default credit distribution routine can be used by setting
|
||||
CreditInitFunc to NULL. The default credit distribution is only provided for simple
|
||||
"fair" credit distribution without regard to any prioritization.
|
||||
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
void HTCSetCreditDistribution(HTC_HANDLE HTCHandle,
|
||||
void *pCreditDistContext,
|
||||
HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
|
||||
HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
|
||||
HTC_SERVICE_ID ServicePriorityOrder[],
|
||||
int ListLength);
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Wait for the target to indicate the HTC layer is ready
|
||||
@function name: HTCWaitTarget
|
||||
@input: HTCHandle - HTC handle
|
||||
@output:
|
||||
@return:
|
||||
@notes: This API blocks until the target responds with an HTC ready message.
|
||||
The caller should not connect services until the target has indicated it is
|
||||
ready.
|
||||
@example:
|
||||
@see also: HTCConnectService
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HTCWaitTarget(HTC_HANDLE HTCHandle);
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Start target service communications
|
||||
@function name: HTCStart
|
||||
@input: HTCHandle - HTC handle
|
||||
@output:
|
||||
@return:
|
||||
@notes: This API indicates to the target that the service connection phase is complete
|
||||
and the target can freely start all connected services. This API should only be
|
||||
called AFTER all service connections have been made. TCStart will issue a
|
||||
SETUP_COMPLETE message to the target to indicate that all service connections
|
||||
have been made and the target can start communicating over the endpoints.
|
||||
@example:
|
||||
@see also: HTCConnectService
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HTCStart(HTC_HANDLE HTCHandle);
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Add receive packet to HTC
|
||||
@function name: HTCAddReceivePkt
|
||||
@input: HTCHandle - HTC handle
|
||||
pPacket - HTC receive packet to add
|
||||
@output:
|
||||
@return: 0 on success
|
||||
@notes: user must supply HTC packets for capturing incomming HTC frames. The caller
|
||||
must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
|
||||
macro.
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HTCAddReceivePkt(HTC_HANDLE HTCHandle, struct htc_packet *pPacket);
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Connect to an HTC service
|
||||
@function name: HTCConnectService
|
||||
@input: HTCHandle - HTC handle
|
||||
pReq - connection details
|
||||
@output: pResp - connection response
|
||||
@return:
|
||||
@notes: Service connections must be performed before HTCStart. User provides callback handlers
|
||||
for various endpoint events.
|
||||
@example:
|
||||
@see also: HTCStart
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HTCConnectService(HTC_HANDLE HTCHandle,
|
||||
struct htc_service_connect_req *pReq,
|
||||
struct htc_service_connect_resp *pResp);
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Send an HTC packet
|
||||
@function name: HTCSendPkt
|
||||
@input: HTCHandle - HTC handle
|
||||
pPacket - packet to send
|
||||
@output:
|
||||
@return: 0
|
||||
@notes: Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro.
|
||||
This interface is fully asynchronous. On error, HTC SendPkt will
|
||||
call the registered Endpoint callback to cleanup the packet.
|
||||
@example:
|
||||
@see also: HTCFlushEndpoint
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HTCSendPkt(HTC_HANDLE HTCHandle, struct htc_packet *pPacket);
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Stop HTC service communications
|
||||
@function name: HTCStop
|
||||
@input: HTCHandle - HTC handle
|
||||
@output:
|
||||
@return:
|
||||
@notes: HTC communications is halted. All receive and pending TX packets will
|
||||
be flushed.
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
void HTCStop(HTC_HANDLE HTCHandle);
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Destroy HTC service
|
||||
@function name: HTCDestroy
|
||||
@input: HTCHandle
|
||||
@output:
|
||||
@return:
|
||||
@notes: This cleans up all resources allocated by HTCCreate().
|
||||
@example:
|
||||
@see also: HTCCreate
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
void HTCDestroy(HTC_HANDLE HTCHandle);
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Flush pending TX packets
|
||||
@function name: HTCFlushEndpoint
|
||||
@input: HTCHandle - HTC handle
|
||||
Endpoint - Endpoint to flush
|
||||
Tag - flush tag
|
||||
@output:
|
||||
@return:
|
||||
@notes: The Tag parameter is used to selectively flush packets with matching tags.
|
||||
The value of 0 forces all packets to be flush regardless of tag.
|
||||
@example:
|
||||
@see also: HTCSendPkt
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag);
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Dump credit distribution state
|
||||
@function name: HTCDumpCreditStates
|
||||
@input: HTCHandle - HTC handle
|
||||
@output:
|
||||
@return:
|
||||
@notes: This dumps all credit distribution information to the debugger
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
void HTCDumpCreditStates(HTC_HANDLE HTCHandle);
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Indicate a traffic activity change on an endpoint
|
||||
@function name: HTCIndicateActivityChange
|
||||
@input: HTCHandle - HTC handle
|
||||
Endpoint - endpoint in which activity has changed
|
||||
Active - true if active, false if it has become inactive
|
||||
@output:
|
||||
@return:
|
||||
@notes: This triggers the registered credit distribution function to
|
||||
re-adjust credits for active/inactive endpoints.
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
void HTCIndicateActivityChange(HTC_HANDLE HTCHandle,
|
||||
HTC_ENDPOINT_ID Endpoint,
|
||||
bool Active);
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Get endpoint statistics
|
||||
@function name: HTCGetEndpointStatistics
|
||||
@input: HTCHandle - HTC handle
|
||||
Endpoint - Endpoint identifier
|
||||
Action - action to take with statistics
|
||||
@output:
|
||||
pStats - statistics that were sampled (can be NULL if Action is HTC_EP_STAT_CLEAR)
|
||||
|
||||
@return: true if statistics profiling is enabled, otherwise false.
|
||||
|
||||
@notes: Statistics is a compile-time option and this function may return false
|
||||
if HTC is not compiled with profiling.
|
||||
|
||||
The caller can specify the statistic "action" to take when sampling
|
||||
the statistics. This includes:
|
||||
|
||||
HTC_EP_STAT_SAMPLE: The pStats structure is filled with the current values.
|
||||
HTC_EP_STAT_SAMPLE_AND_CLEAR: The structure is filled and the current statistics
|
||||
are cleared.
|
||||
HTC_EP_STAT_CLEA : the statistics are cleared, the called can pass a NULL value for
|
||||
pStats
|
||||
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
bool HTCGetEndpointStatistics(HTC_HANDLE HTCHandle,
|
||||
HTC_ENDPOINT_ID Endpoint,
|
||||
HTC_ENDPOINT_STAT_ACTION Action,
|
||||
struct htc_endpoint_stats *pStats);
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Unblock HTC message reception
|
||||
@function name: HTCUnblockRecv
|
||||
@input: HTCHandle - HTC handle
|
||||
@output:
|
||||
@return:
|
||||
@notes:
|
||||
HTC will block the receiver if the EpRecvAlloc callback fails to provide a packet.
|
||||
The caller can use this API to indicate to HTC when resources (buffers) are available
|
||||
such that the receiver can be unblocked and HTC may re-attempt fetching the pending message.
|
||||
|
||||
This API is not required if the user uses the EpRecvRefill callback or uses the HTCAddReceivePacket()
|
||||
API to recycle or provide receive packets to HTC.
|
||||
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
void HTCUnblockRecv(HTC_HANDLE HTCHandle);
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: send a series of HTC packets
|
||||
@function name: HTCSendPktsMultiple
|
||||
@input: HTCHandle - HTC handle
|
||||
pPktQueue - local queue holding packets to send
|
||||
@output:
|
||||
@return: 0
|
||||
@notes: Caller must initialize each packet using SET_HTC_PACKET_INFO_TX() macro.
|
||||
The queue must only contain packets directed at the same endpoint.
|
||||
Caller supplies a pointer to an struct htc_packet_queue structure holding the TX packets in FIFO order.
|
||||
This API will remove the packets from the pkt queue and place them into the HTC Tx Queue
|
||||
and bundle messages where possible.
|
||||
The caller may allocate the pkt queue on the stack to hold the packets.
|
||||
This interface is fully asynchronous. On error, HTCSendPkts will
|
||||
call the registered Endpoint callback to cleanup the packet.
|
||||
@example:
|
||||
@see also: HTCFlushEndpoint
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HTCSendPktsMultiple(HTC_HANDLE HTCHandle, struct htc_packet_queue *pPktQueue);
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Add multiple receive packets to HTC
|
||||
@function name: HTCAddReceivePktMultiple
|
||||
@input: HTCHandle - HTC handle
|
||||
pPktQueue - HTC receive packet queue holding packets to add
|
||||
@output:
|
||||
@return: 0 on success
|
||||
@notes: user must supply HTC packets for capturing incomming HTC frames. The caller
|
||||
must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
|
||||
macro. The queue must only contain recv packets for the same endpoint.
|
||||
Caller supplies a pointer to an struct htc_packet_queue structure holding the recv packet.
|
||||
This API will remove the packets from the pkt queue and place them into internal
|
||||
recv packet list.
|
||||
The caller may allocate the pkt queue on the stack to hold the packets.
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HTCAddReceivePktMultiple(HTC_HANDLE HTCHandle, struct htc_packet_queue *pPktQueue);
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Check if an endpoint is marked active
|
||||
@function name: HTCIsEndpointActive
|
||||
@input: HTCHandle - HTC handle
|
||||
Endpoint - endpoint to check for active state
|
||||
@output:
|
||||
@return: returns true if Endpoint is Active
|
||||
@notes:
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
bool HTCIsEndpointActive(HTC_HANDLE HTCHandle,
|
||||
HTC_ENDPOINT_ID Endpoint);
|
||||
|
||||
|
||||
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
@desc: Get the number of recv buffers currently queued into an HTC endpoint
|
||||
@function name: HTCGetNumRecvBuffers
|
||||
@input: HTCHandle - HTC handle
|
||||
Endpoint - endpoint to check
|
||||
@output:
|
||||
@return: returns number of buffers in queue
|
||||
@notes:
|
||||
@example:
|
||||
@see also:
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
|
||||
int HTCGetNumRecvBuffers(HTC_HANDLE HTCHandle,
|
||||
HTC_ENDPOINT_ID Endpoint);
|
||||
|
||||
/* internally used functions for testing... */
|
||||
void HTCEnableRecv(HTC_HANDLE HTCHandle);
|
||||
void HTCDisableRecv(HTC_HANDLE HTCHandle);
|
||||
int HTCWaitForPendingRecv(HTC_HANDLE HTCHandle,
|
||||
u32 TimeoutInMs,
|
||||
bool *pbIsRecvPending);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HTC_API_H_ */
|
|
@ -1,227 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="htc_packet.h" company="Atheros">
|
||||
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef HTC_PACKET_H_
|
||||
#define HTC_PACKET_H_
|
||||
|
||||
|
||||
#include "dl_list.h"
|
||||
|
||||
/* ------ Endpoint IDS ------ */
|
||||
typedef enum
|
||||
{
|
||||
ENDPOINT_UNUSED = -1,
|
||||
ENDPOINT_0 = 0,
|
||||
ENDPOINT_1 = 1,
|
||||
ENDPOINT_2 = 2,
|
||||
ENDPOINT_3,
|
||||
ENDPOINT_4,
|
||||
ENDPOINT_5,
|
||||
ENDPOINT_6,
|
||||
ENDPOINT_7,
|
||||
ENDPOINT_8,
|
||||
ENDPOINT_MAX,
|
||||
} HTC_ENDPOINT_ID;
|
||||
|
||||
struct htc_packet;
|
||||
|
||||
typedef void (* HTC_PACKET_COMPLETION)(void *,struct htc_packet *);
|
||||
|
||||
typedef u16 HTC_TX_TAG;
|
||||
|
||||
struct htc_tx_packet_info {
|
||||
HTC_TX_TAG Tag; /* tag used to selective flush packets */
|
||||
int CreditsUsed; /* number of credits used for this TX packet (HTC internal) */
|
||||
u8 SendFlags; /* send flags (HTC internal) */
|
||||
int SeqNo; /* internal seq no for debugging (HTC internal) */
|
||||
};
|
||||
|
||||
#define HTC_TX_PACKET_TAG_ALL 0 /* a tag of zero is reserved and used to flush ALL packets */
|
||||
#define HTC_TX_PACKET_TAG_INTERNAL 1 /* internal tags start here */
|
||||
#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9) /* user-defined tags start here */
|
||||
|
||||
struct htc_rx_packet_info {
|
||||
u32 ExpectedHdr; /* HTC internal use */
|
||||
u32 HTCRxFlags; /* HTC internal use */
|
||||
u32 IndicationFlags; /* indication flags set on each RX packet indication */
|
||||
};
|
||||
|
||||
#define HTC_RX_FLAGS_INDICATE_MORE_PKTS (1 << 0) /* more packets on this endpoint are being fetched */
|
||||
|
||||
/* wrapper around endpoint-specific packets */
|
||||
struct htc_packet {
|
||||
struct dl_list ListLink; /* double link */
|
||||
void *pPktContext; /* caller's per packet specific context */
|
||||
|
||||
u8 *pBufferStart; /* the true buffer start , the caller can
|
||||
store the real buffer start here. In
|
||||
receive callbacks, the HTC layer sets pBuffer
|
||||
to the start of the payload past the header. This
|
||||
field allows the caller to reset pBuffer when it
|
||||
recycles receive packets back to HTC */
|
||||
/*
|
||||
* Pointer to the start of the buffer. In the transmit
|
||||
* direction this points to the start of the payload. In the
|
||||
* receive direction, however, the buffer when queued up
|
||||
* points to the start of the HTC header but when returned
|
||||
* to the caller points to the start of the payload
|
||||
*/
|
||||
u8 *pBuffer; /* payload start (RX/TX) */
|
||||
u32 BufferLength; /* length of buffer */
|
||||
u32 ActualLength; /* actual length of payload */
|
||||
HTC_ENDPOINT_ID Endpoint; /* endpoint that this packet was sent/recv'd from */
|
||||
int Status; /* completion status */
|
||||
union {
|
||||
struct htc_tx_packet_info AsTx; /* Tx Packet specific info */
|
||||
struct htc_rx_packet_info AsRx; /* Rx Packet specific info */
|
||||
} PktInfo;
|
||||
|
||||
/* the following fields are for internal HTC use */
|
||||
HTC_PACKET_COMPLETION Completion; /* completion */
|
||||
void *pContext; /* HTC private completion context */
|
||||
};
|
||||
|
||||
|
||||
|
||||
#define COMPLETE_HTC_PACKET(p,status) \
|
||||
{ \
|
||||
(p)->Status = (status); \
|
||||
(p)->Completion((p)->pContext,(p)); \
|
||||
}
|
||||
|
||||
#define INIT_HTC_PACKET_INFO(p,b,len) \
|
||||
{ \
|
||||
(p)->pBufferStart = (b); \
|
||||
(p)->BufferLength = (len); \
|
||||
}
|
||||
|
||||
/* macro to set an initial RX packet for refilling HTC */
|
||||
#define SET_HTC_PACKET_INFO_RX_REFILL(p,c,b,len,ep) \
|
||||
{ \
|
||||
(p)->pPktContext = (c); \
|
||||
(p)->pBuffer = (b); \
|
||||
(p)->pBufferStart = (b); \
|
||||
(p)->BufferLength = (len); \
|
||||
(p)->Endpoint = (ep); \
|
||||
}
|
||||
|
||||
/* fast macro to recycle an RX packet that will be re-queued to HTC */
|
||||
#define HTC_PACKET_RESET_RX(p) \
|
||||
{ (p)->pBuffer = (p)->pBufferStart; (p)->ActualLength = 0; }
|
||||
|
||||
/* macro to set packet parameters for TX */
|
||||
#define SET_HTC_PACKET_INFO_TX(p,c,b,len,ep,tag) \
|
||||
{ \
|
||||
(p)->pPktContext = (c); \
|
||||
(p)->pBuffer = (b); \
|
||||
(p)->ActualLength = (len); \
|
||||
(p)->Endpoint = (ep); \
|
||||
(p)->PktInfo.AsTx.Tag = (tag); \
|
||||
}
|
||||
|
||||
/* HTC Packet Queueing Macros */
|
||||
struct htc_packet_queue {
|
||||
struct dl_list QueueHead;
|
||||
int Depth;
|
||||
};
|
||||
|
||||
/* initialize queue */
|
||||
#define INIT_HTC_PACKET_QUEUE(pQ) \
|
||||
{ \
|
||||
DL_LIST_INIT(&(pQ)->QueueHead); \
|
||||
(pQ)->Depth = 0; \
|
||||
}
|
||||
|
||||
/* enqueue HTC packet to the tail of the queue */
|
||||
#define HTC_PACKET_ENQUEUE(pQ,p) \
|
||||
{ DL_ListInsertTail(&(pQ)->QueueHead,&(p)->ListLink); \
|
||||
(pQ)->Depth++; \
|
||||
}
|
||||
|
||||
/* enqueue HTC packet to the tail of the queue */
|
||||
#define HTC_PACKET_ENQUEUE_TO_HEAD(pQ,p) \
|
||||
{ DL_ListInsertHead(&(pQ)->QueueHead,&(p)->ListLink); \
|
||||
(pQ)->Depth++; \
|
||||
}
|
||||
/* test if a queue is empty */
|
||||
#define HTC_QUEUE_EMPTY(pQ) ((pQ)->Depth == 0)
|
||||
/* get packet at head without removing it */
|
||||
static INLINE struct htc_packet *HTC_GET_PKT_AT_HEAD(struct htc_packet_queue *queue) {
|
||||
if (queue->Depth == 0) {
|
||||
return NULL;
|
||||
}
|
||||
return A_CONTAINING_STRUCT((DL_LIST_GET_ITEM_AT_HEAD(&queue->QueueHead)),struct htc_packet,ListLink);
|
||||
}
|
||||
/* remove a packet from a queue, where-ever it is in the queue */
|
||||
#define HTC_PACKET_REMOVE(pQ,p) \
|
||||
{ \
|
||||
DL_ListRemove(&(p)->ListLink); \
|
||||
(pQ)->Depth--; \
|
||||
}
|
||||
|
||||
/* dequeue an HTC packet from the head of the queue */
|
||||
static INLINE struct htc_packet *HTC_PACKET_DEQUEUE(struct htc_packet_queue *queue) {
|
||||
struct dl_list *pItem = DL_ListRemoveItemFromHead(&queue->QueueHead);
|
||||
if (pItem != NULL) {
|
||||
queue->Depth--;
|
||||
return A_CONTAINING_STRUCT(pItem, struct htc_packet, ListLink);
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* dequeue an HTC packet from the tail of the queue */
|
||||
static INLINE struct htc_packet *HTC_PACKET_DEQUEUE_TAIL(struct htc_packet_queue *queue) {
|
||||
struct dl_list *pItem = DL_ListRemoveItemFromTail(&queue->QueueHead);
|
||||
if (pItem != NULL) {
|
||||
queue->Depth--;
|
||||
return A_CONTAINING_STRUCT(pItem, struct htc_packet, ListLink);
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#define HTC_PACKET_QUEUE_DEPTH(pQ) (pQ)->Depth
|
||||
|
||||
|
||||
#define HTC_GET_ENDPOINT_FROM_PKT(p) (p)->Endpoint
|
||||
#define HTC_GET_TAG_FROM_PKT(p) (p)->PktInfo.AsTx.Tag
|
||||
|
||||
/* transfer the packets from one queue to the tail of another queue */
|
||||
#define HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(pQDest,pQSrc) \
|
||||
{ \
|
||||
DL_ListTransferItemsToTail(&(pQDest)->QueueHead,&(pQSrc)->QueueHead); \
|
||||
(pQDest)->Depth += (pQSrc)->Depth; \
|
||||
(pQSrc)->Depth = 0; \
|
||||
}
|
||||
|
||||
/* fast version to init and add a single packet to a queue */
|
||||
#define INIT_HTC_PACKET_QUEUE_AND_ADD(pQ,pP) \
|
||||
{ \
|
||||
DL_LIST_INIT_AND_ADD(&(pQ)->QueueHead,&(pP)->ListLink) \
|
||||
(pQ)->Depth = 1; \
|
||||
}
|
||||
|
||||
#define HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pQ, pPTemp) \
|
||||
ITERATE_OVER_LIST_ALLOW_REMOVE(&(pQ)->QueueHead,(pPTemp), struct htc_packet, ListLink)
|
||||
|
||||
#define HTC_PACKET_QUEUE_ITERATE_END ITERATE_END
|
||||
|
||||
#endif /*HTC_PACKET_H_*/
|
|
@ -1,128 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// This file contains the API for the host wlan module
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _HOST_WLAN_API_H_
|
||||
#define _HOST_WLAN_API_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <a_osapi.h>
|
||||
|
||||
struct ieee80211_node_table;
|
||||
struct ieee80211_frame;
|
||||
|
||||
struct ieee80211_common_ie {
|
||||
u16 ie_chan;
|
||||
u8 *ie_tstamp;
|
||||
u8 *ie_ssid;
|
||||
u8 *ie_rates;
|
||||
u8 *ie_xrates;
|
||||
u8 *ie_country;
|
||||
u8 *ie_wpa;
|
||||
u8 *ie_rsn;
|
||||
u8 *ie_wmm;
|
||||
u8 *ie_ath;
|
||||
u16 ie_capInfo;
|
||||
u16 ie_beaconInt;
|
||||
u8 *ie_tim;
|
||||
u8 *ie_chswitch;
|
||||
u8 ie_erp;
|
||||
u8 *ie_wsc;
|
||||
u8 *ie_htcap;
|
||||
u8 *ie_htop;
|
||||
#ifdef WAPI_ENABLE
|
||||
u8 *ie_wapi;
|
||||
#endif
|
||||
};
|
||||
|
||||
typedef struct bss {
|
||||
u8 ni_macaddr[6];
|
||||
u8 ni_snr;
|
||||
s16 ni_rssi;
|
||||
struct bss *ni_list_next;
|
||||
struct bss *ni_list_prev;
|
||||
struct bss *ni_hash_next;
|
||||
struct bss *ni_hash_prev;
|
||||
struct ieee80211_common_ie ni_cie;
|
||||
u8 *ni_buf;
|
||||
u16 ni_framelen;
|
||||
struct ieee80211_node_table *ni_table;
|
||||
u32 ni_refcnt;
|
||||
int ni_scangen;
|
||||
|
||||
u32 ni_tstamp;
|
||||
u32 ni_actcnt;
|
||||
#ifdef OS_ROAM_MANAGEMENT
|
||||
u32 ni_si_gen;
|
||||
#endif
|
||||
} bss_t;
|
||||
|
||||
typedef void wlan_node_iter_func(void *arg, bss_t *);
|
||||
|
||||
bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size);
|
||||
void wlan_node_free(bss_t *ni);
|
||||
void wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
|
||||
const u8 *macaddr);
|
||||
bss_t *wlan_find_node(struct ieee80211_node_table *nt, const u8 *macaddr);
|
||||
void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni);
|
||||
void wlan_free_allnodes(struct ieee80211_node_table *nt);
|
||||
void wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
|
||||
void *arg);
|
||||
|
||||
void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt);
|
||||
void wlan_node_table_reset(struct ieee80211_node_table *nt);
|
||||
void wlan_node_table_cleanup(struct ieee80211_node_table *nt);
|
||||
|
||||
int wlan_parse_beacon(u8 *buf, int framelen,
|
||||
struct ieee80211_common_ie *cie);
|
||||
|
||||
u16 wlan_ieee2freq(int chan);
|
||||
u32 wlan_freq2ieee(u16 freq);
|
||||
|
||||
void wlan_set_nodeage(struct ieee80211_node_table *nt, u32 nodeAge);
|
||||
|
||||
void
|
||||
wlan_refresh_inactive_nodes (struct ieee80211_node_table *nt);
|
||||
|
||||
bss_t *
|
||||
wlan_find_Ssidnode (struct ieee80211_node_table *nt, u8 *pSsid,
|
||||
u32 ssidLength, bool bIsWPA2, bool bMatchSSID);
|
||||
|
||||
void
|
||||
wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni);
|
||||
|
||||
bss_t *wlan_node_remove(struct ieee80211_node_table *nt, u8 *bssid);
|
||||
|
||||
bss_t *
|
||||
wlan_find_matching_Ssidnode (struct ieee80211_node_table *nt, u8 *pSsid,
|
||||
u32 ssidLength, u32 dot11AuthMode, u32 authMode,
|
||||
u32 pairwiseCryptoType, u32 grpwiseCryptoTyp);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HOST_WLAN_API_H_ */
|
|
@ -1,441 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="wmi_api.h" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// This file contains the definitions for the Wireless Module Interface (WMI).
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
#ifndef _WMI_API_H_
|
||||
#define _WMI_API_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* WMI converts a dix frame with an ethernet payload (up to 1500 bytes)
|
||||
* to an 802.3 frame (adds SNAP header) and adds on a WMI data header */
|
||||
#define WMI_MAX_TX_DATA_FRAME_LENGTH (1500 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR))
|
||||
|
||||
/* A normal WMI data frame */
|
||||
#define WMI_MAX_NORMAL_RX_DATA_FRAME_LENGTH (1500 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR))
|
||||
|
||||
/* An AMSDU frame */ /* The MAX AMSDU length of AR6003 is 3839 */
|
||||
#define WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH (3840 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR))
|
||||
|
||||
/*
|
||||
* IP QoS Field definitions according to 802.1p
|
||||
*/
|
||||
#define BEST_EFFORT_PRI 0
|
||||
#define BACKGROUND_PRI 1
|
||||
#define EXCELLENT_EFFORT_PRI 3
|
||||
#define CONTROLLED_LOAD_PRI 4
|
||||
#define VIDEO_PRI 5
|
||||
#define VOICE_PRI 6
|
||||
#define NETWORK_CONTROL_PRI 7
|
||||
#define MAX_NUM_PRI 8
|
||||
|
||||
#define UNDEFINED_PRI (0xff)
|
||||
|
||||
#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */
|
||||
|
||||
#define A_ROUND_UP(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
|
||||
|
||||
typedef enum {
|
||||
ATHEROS_COMPLIANCE = 0x1,
|
||||
}TSPEC_PARAM_COMPLIANCE;
|
||||
|
||||
struct wmi_t;
|
||||
|
||||
void *wmi_init(void *devt);
|
||||
|
||||
void wmi_qos_state_init(struct wmi_t *wmip);
|
||||
void wmi_shutdown(struct wmi_t *wmip);
|
||||
HTC_ENDPOINT_ID wmi_get_control_ep(struct wmi_t * wmip);
|
||||
void wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid);
|
||||
u16 wmi_get_mapped_qos_queue(struct wmi_t *, u8 );
|
||||
int wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf);
|
||||
int wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, u8 msgType, bool bMoreData, WMI_DATA_HDR_DATA_TYPE data_type,u8 metaVersion, void *pTxMetaS);
|
||||
int wmi_dot3_2_dix(void *osbuf);
|
||||
|
||||
int wmi_dot11_hdr_remove (struct wmi_t *wmip, void *osbuf);
|
||||
int wmi_dot11_hdr_add(struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode);
|
||||
|
||||
int wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf);
|
||||
int wmi_syncpoint(struct wmi_t *wmip);
|
||||
int wmi_syncpoint_reset(struct wmi_t *wmip);
|
||||
u8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, u32 layer2Priority, bool wmmEnabled);
|
||||
|
||||
u8 wmi_determine_userPriority (u8 *pkt, u32 layer2Pri);
|
||||
|
||||
int wmi_control_rx(struct wmi_t *wmip, void *osbuf);
|
||||
void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg);
|
||||
void wmi_free_allnodes(struct wmi_t *wmip);
|
||||
bss_t *wmi_find_node(struct wmi_t *wmip, const u8 *macaddr);
|
||||
void wmi_free_node(struct wmi_t *wmip, const u8 *macaddr);
|
||||
|
||||
|
||||
typedef enum {
|
||||
NO_SYNC_WMIFLAG = 0,
|
||||
SYNC_BEFORE_WMIFLAG, /* transmit all queued data before cmd */
|
||||
SYNC_AFTER_WMIFLAG, /* any new data waits until cmd execs */
|
||||
SYNC_BOTH_WMIFLAG,
|
||||
END_WMIFLAG /* end marker */
|
||||
} WMI_SYNC_FLAG;
|
||||
|
||||
int wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
|
||||
WMI_SYNC_FLAG flag);
|
||||
|
||||
int wmi_connect_cmd(struct wmi_t *wmip,
|
||||
NETWORK_TYPE netType,
|
||||
DOT11_AUTH_MODE dot11AuthMode,
|
||||
AUTH_MODE authMode,
|
||||
CRYPTO_TYPE pairwiseCrypto,
|
||||
u8 pairwiseCryptoLen,
|
||||
CRYPTO_TYPE groupCrypto,
|
||||
u8 groupCryptoLen,
|
||||
int ssidLength,
|
||||
u8 *ssid,
|
||||
u8 *bssid,
|
||||
u16 channel,
|
||||
u32 ctrl_flags);
|
||||
|
||||
int wmi_reconnect_cmd(struct wmi_t *wmip,
|
||||
u8 *bssid,
|
||||
u16 channel);
|
||||
int wmi_disconnect_cmd(struct wmi_t *wmip);
|
||||
int wmi_getrev_cmd(struct wmi_t *wmip);
|
||||
int wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
|
||||
u32 forceFgScan, u32 isLegacy,
|
||||
u32 homeDwellTime, u32 forceScanInterval,
|
||||
s8 numChan, u16 *channelList);
|
||||
int wmi_scanparams_cmd(struct wmi_t *wmip, u16 fg_start_sec,
|
||||
u16 fg_end_sec, u16 bg_sec,
|
||||
u16 minact_chdw_msec,
|
||||
u16 maxact_chdw_msec, u16 pas_chdw_msec,
|
||||
u8 shScanRatio, u8 scanCtrlFlags,
|
||||
u32 max_dfsch_act_time,
|
||||
u16 maxact_scan_per_ssid);
|
||||
int wmi_bssfilter_cmd(struct wmi_t *wmip, u8 filter, u32 ieMask);
|
||||
int wmi_probedSsid_cmd(struct wmi_t *wmip, u8 index, u8 flag,
|
||||
u8 ssidLength, u8 *ssid);
|
||||
int wmi_listeninterval_cmd(struct wmi_t *wmip, u16 listenInterval, u16 listenBeacons);
|
||||
int wmi_bmisstime_cmd(struct wmi_t *wmip, u16 bmisstime, u16 bmissbeacons);
|
||||
int wmi_associnfo_cmd(struct wmi_t *wmip, u8 ieType,
|
||||
u8 ieLen, u8 *ieInfo);
|
||||
int wmi_powermode_cmd(struct wmi_t *wmip, u8 powerMode);
|
||||
int wmi_ibsspmcaps_cmd(struct wmi_t *wmip, u8 pmEnable, u8 ttl,
|
||||
u16 atim_windows, u16 timeout_value);
|
||||
int wmi_apps_cmd(struct wmi_t *wmip, u8 psType, u32 idle_time,
|
||||
u32 ps_period, u8 sleep_period);
|
||||
int wmi_pmparams_cmd(struct wmi_t *wmip, u16 idlePeriod,
|
||||
u16 psPollNum, u16 dtimPolicy,
|
||||
u16 wakup_tx_policy, u16 num_tx_to_wakeup,
|
||||
u16 ps_fail_event_policy);
|
||||
int wmi_disctimeout_cmd(struct wmi_t *wmip, u8 timeout);
|
||||
int wmi_sync_cmd(struct wmi_t *wmip, u8 syncNumber);
|
||||
int wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *pstream);
|
||||
int wmi_delete_pstream_cmd(struct wmi_t *wmip, u8 trafficClass, u8 streamID);
|
||||
int wmi_set_framerate_cmd(struct wmi_t *wmip, u8 bEnable, u8 type, u8 subType, u16 rateMask);
|
||||
int wmi_set_bitrate_cmd(struct wmi_t *wmip, s32 dataRate, s32 mgmtRate, s32 ctlRate);
|
||||
int wmi_get_bitrate_cmd(struct wmi_t *wmip);
|
||||
s8 wmi_validate_bitrate(struct wmi_t *wmip, s32 rate, s8 *rate_idx);
|
||||
int wmi_get_regDomain_cmd(struct wmi_t *wmip);
|
||||
int wmi_get_channelList_cmd(struct wmi_t *wmip);
|
||||
int wmi_set_channelParams_cmd(struct wmi_t *wmip, u8 scanParam,
|
||||
WMI_PHY_MODE mode, s8 numChan,
|
||||
u16 *channelList);
|
||||
|
||||
int wmi_set_snr_threshold_params(struct wmi_t *wmip,
|
||||
WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd);
|
||||
int wmi_set_rssi_threshold_params(struct wmi_t *wmip,
|
||||
WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd);
|
||||
int wmi_clr_rssi_snr(struct wmi_t *wmip);
|
||||
int wmi_set_lq_threshold_params(struct wmi_t *wmip,
|
||||
WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd);
|
||||
int wmi_set_rts_cmd(struct wmi_t *wmip, u16 threshold);
|
||||
int wmi_set_lpreamble_cmd(struct wmi_t *wmip, u8 status, u8 preamblePolicy);
|
||||
|
||||
int wmi_set_error_report_bitmask(struct wmi_t *wmip, u32 bitmask);
|
||||
|
||||
int wmi_get_challenge_resp_cmd(struct wmi_t *wmip, u32 cookie,
|
||||
u32 source);
|
||||
|
||||
int wmi_config_debug_module_cmd(struct wmi_t *wmip, u16 mmask,
|
||||
u16 tsr, bool rep, u16 size,
|
||||
u32 valid);
|
||||
|
||||
int wmi_get_stats_cmd(struct wmi_t *wmip);
|
||||
|
||||
int wmi_addKey_cmd(struct wmi_t *wmip, u8 keyIndex,
|
||||
CRYPTO_TYPE keyType, u8 keyUsage,
|
||||
u8 keyLength,u8 *keyRSC,
|
||||
u8 *keyMaterial, u8 key_op_ctrl, u8 *mac,
|
||||
WMI_SYNC_FLAG sync_flag);
|
||||
int wmi_add_krk_cmd(struct wmi_t *wmip, u8 *krk);
|
||||
int wmi_delete_krk_cmd(struct wmi_t *wmip);
|
||||
int wmi_deleteKey_cmd(struct wmi_t *wmip, u8 keyIndex);
|
||||
int wmi_set_akmp_params_cmd(struct wmi_t *wmip,
|
||||
WMI_SET_AKMP_PARAMS_CMD *akmpParams);
|
||||
int wmi_get_pmkid_list_cmd(struct wmi_t *wmip);
|
||||
int wmi_set_pmkid_list_cmd(struct wmi_t *wmip,
|
||||
WMI_SET_PMKID_LIST_CMD *pmkInfo);
|
||||
int wmi_abort_scan_cmd(struct wmi_t *wmip);
|
||||
int wmi_set_txPwr_cmd(struct wmi_t *wmip, u8 dbM);
|
||||
int wmi_get_txPwr_cmd(struct wmi_t *wmip);
|
||||
int wmi_addBadAp_cmd(struct wmi_t *wmip, u8 apIndex, u8 *bssid);
|
||||
int wmi_deleteBadAp_cmd(struct wmi_t *wmip, u8 apIndex);
|
||||
int wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, bool en);
|
||||
int wmi_setPmkid_cmd(struct wmi_t *wmip, u8 *bssid, u8 *pmkId,
|
||||
bool set);
|
||||
int wmi_set_access_params_cmd(struct wmi_t *wmip, u8 ac, u16 txop,
|
||||
u8 eCWmin, u8 eCWmax,
|
||||
u8 aifsn);
|
||||
int wmi_set_retry_limits_cmd(struct wmi_t *wmip, u8 frameType,
|
||||
u8 trafficClass, u8 maxRetries,
|
||||
u8 enableNotify);
|
||||
|
||||
void wmi_get_current_bssid(struct wmi_t *wmip, u8 *bssid);
|
||||
|
||||
int wmi_get_roam_tbl_cmd(struct wmi_t *wmip);
|
||||
int wmi_get_roam_data_cmd(struct wmi_t *wmip, u8 roamDataType);
|
||||
int wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
|
||||
u8 size);
|
||||
int wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
|
||||
WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd,
|
||||
u8 size);
|
||||
|
||||
int wmi_set_opt_mode_cmd(struct wmi_t *wmip, u8 optMode);
|
||||
int wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
|
||||
u8 frmType,
|
||||
u8 *dstMacAddr,
|
||||
u8 *bssid,
|
||||
u16 optIEDataLen,
|
||||
u8 *optIEData);
|
||||
|
||||
int wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, u16 intvl);
|
||||
int wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, u16 voicePktSize);
|
||||
int wmi_set_max_sp_len_cmd(struct wmi_t *wmip, u8 maxSpLen);
|
||||
u8 convert_userPriority_to_trafficClass(u8 userPriority);
|
||||
u8 wmi_get_power_mode_cmd(struct wmi_t *wmip);
|
||||
int wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, int tspecCompliance);
|
||||
|
||||
#ifdef CONFIG_HOST_TCMD_SUPPORT
|
||||
int wmi_test_cmd(struct wmi_t *wmip, u8 *buf, u32 len);
|
||||
#endif
|
||||
|
||||
int wmi_set_bt_status_cmd(struct wmi_t *wmip, u8 streamType, u8 status);
|
||||
int wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd);
|
||||
|
||||
int wmi_set_btcoex_fe_ant_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_FE_ANT_CMD * cmd);
|
||||
|
||||
int wmi_set_btcoex_colocated_bt_dev_cmd(struct wmi_t *wmip,
|
||||
WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD * cmd);
|
||||
|
||||
int wmi_set_btcoex_btinquiry_page_config_cmd(struct wmi_t *wmip,
|
||||
WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD *cmd);
|
||||
|
||||
int wmi_set_btcoex_sco_config_cmd(struct wmi_t *wmip,
|
||||
WMI_SET_BTCOEX_SCO_CONFIG_CMD * cmd);
|
||||
|
||||
int wmi_set_btcoex_a2dp_config_cmd(struct wmi_t *wmip,
|
||||
WMI_SET_BTCOEX_A2DP_CONFIG_CMD* cmd);
|
||||
|
||||
|
||||
int wmi_set_btcoex_aclcoex_config_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD* cmd);
|
||||
|
||||
int wmi_set_btcoex_debug_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_DEBUG_CMD * cmd);
|
||||
|
||||
int wmi_set_btcoex_bt_operating_status_cmd(struct wmi_t * wmip,
|
||||
WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD * cmd);
|
||||
|
||||
int wmi_get_btcoex_config_cmd(struct wmi_t * wmip, WMI_GET_BTCOEX_CONFIG_CMD * cmd);
|
||||
|
||||
int wmi_get_btcoex_stats_cmd(struct wmi_t * wmip);
|
||||
|
||||
int wmi_SGI_cmd(struct wmi_t *wmip, u32 sgiMask, u8 sgiPERThreshold);
|
||||
|
||||
/*
|
||||
* This function is used to configure the fix rates mask to the target.
|
||||
*/
|
||||
int wmi_set_fixrates_cmd(struct wmi_t *wmip, u32 fixRatesMask);
|
||||
int wmi_get_ratemask_cmd(struct wmi_t *wmip);
|
||||
|
||||
int wmi_set_authmode_cmd(struct wmi_t *wmip, u8 mode);
|
||||
|
||||
int wmi_set_reassocmode_cmd(struct wmi_t *wmip, u8 mode);
|
||||
|
||||
int wmi_set_qos_supp_cmd(struct wmi_t *wmip,u8 status);
|
||||
int wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status);
|
||||
int wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG txEnable);
|
||||
int wmi_set_country(struct wmi_t *wmip, u8 *countryCode);
|
||||
|
||||
int wmi_get_keepalive_configured(struct wmi_t *wmip);
|
||||
u8 wmi_get_keepalive_cmd(struct wmi_t *wmip);
|
||||
int wmi_set_keepalive_cmd(struct wmi_t *wmip, u8 keepaliveInterval);
|
||||
|
||||
int wmi_set_appie_cmd(struct wmi_t *wmip, u8 mgmtFrmType,
|
||||
u8 ieLen,u8 *ieInfo);
|
||||
|
||||
int wmi_set_halparam_cmd(struct wmi_t *wmip, u8 *cmd, u16 dataLen);
|
||||
|
||||
s32 wmi_get_rate(s8 rateindex);
|
||||
|
||||
int wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *cmd);
|
||||
|
||||
/*Wake on Wireless WMI commands*/
|
||||
int wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, WMI_SET_HOST_SLEEP_MODE_CMD *cmd);
|
||||
int wmi_set_wow_mode_cmd(struct wmi_t *wmip, WMI_SET_WOW_MODE_CMD *cmd);
|
||||
int wmi_get_wow_list_cmd(struct wmi_t *wmip, WMI_GET_WOW_LIST_CMD *cmd);
|
||||
int wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
|
||||
WMI_ADD_WOW_PATTERN_CMD *cmd, u8 *pattern, u8 *mask, u8 pattern_size);
|
||||
int wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
|
||||
WMI_DEL_WOW_PATTERN_CMD *cmd);
|
||||
int wmi_set_wsc_status_cmd(struct wmi_t *wmip, u32 status);
|
||||
|
||||
int
|
||||
wmi_set_params_cmd(struct wmi_t *wmip, u32 opcode, u32 length, char *buffer);
|
||||
|
||||
int
|
||||
wmi_set_mcast_filter_cmd(struct wmi_t *wmip, u8 dot1, u8 dot2, u8 dot3, u8 dot4);
|
||||
|
||||
int
|
||||
wmi_del_mcast_filter_cmd(struct wmi_t *wmip, u8 dot1, u8 dot2, u8 dot3, u8 dot4);
|
||||
|
||||
int
|
||||
wmi_mcast_filter_cmd(struct wmi_t *wmip, u8 enable);
|
||||
|
||||
bss_t *
|
||||
wmi_find_Ssidnode (struct wmi_t *wmip, u8 *pSsid,
|
||||
u32 ssidLength, bool bIsWPA2, bool bMatchSSID);
|
||||
|
||||
|
||||
void
|
||||
wmi_node_return (struct wmi_t *wmip, bss_t *bss);
|
||||
|
||||
void
|
||||
wmi_set_nodeage(struct wmi_t *wmip, u32 nodeAge);
|
||||
|
||||
#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
|
||||
int wmi_prof_cfg_cmd(struct wmi_t *wmip, u32 period, u32 nbins);
|
||||
int wmi_prof_addr_set_cmd(struct wmi_t *wmip, u32 addr);
|
||||
int wmi_prof_start_cmd(struct wmi_t *wmip);
|
||||
int wmi_prof_stop_cmd(struct wmi_t *wmip);
|
||||
int wmi_prof_count_get_cmd(struct wmi_t *wmip);
|
||||
#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
|
||||
#ifdef OS_ROAM_MANAGEMENT
|
||||
void wmi_scan_indication (struct wmi_t *wmip);
|
||||
#endif
|
||||
|
||||
int
|
||||
wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd);
|
||||
|
||||
bss_t *wmi_rm_current_bss (struct wmi_t *wmip, u8 *id);
|
||||
int wmi_add_current_bss (struct wmi_t *wmip, u8 *id, bss_t *bss);
|
||||
|
||||
|
||||
/*
|
||||
* AP mode
|
||||
*/
|
||||
int
|
||||
wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p);
|
||||
|
||||
int
|
||||
wmi_ap_set_hidden_ssid(struct wmi_t *wmip, u8 hidden_ssid);
|
||||
|
||||
int
|
||||
wmi_ap_set_num_sta(struct wmi_t *wmip, u8 num_sta);
|
||||
|
||||
int
|
||||
wmi_ap_set_acl_policy(struct wmi_t *wmip, u8 policy);
|
||||
|
||||
int
|
||||
wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *a);
|
||||
|
||||
u8 acl_add_del_mac(WMI_AP_ACL *a, WMI_AP_ACL_MAC_CMD *acl);
|
||||
|
||||
int
|
||||
wmi_ap_set_mlme(struct wmi_t *wmip, u8 cmd, u8 *mac, u16 reason);
|
||||
|
||||
int
|
||||
wmi_set_pvb_cmd(struct wmi_t *wmip, u16 aid, bool flag);
|
||||
|
||||
int
|
||||
wmi_ap_conn_inact_time(struct wmi_t *wmip, u32 period);
|
||||
|
||||
int
|
||||
wmi_ap_bgscan_time(struct wmi_t *wmip, u32 period, u32 dwell);
|
||||
|
||||
int
|
||||
wmi_ap_set_dtim(struct wmi_t *wmip, u8 dtim);
|
||||
|
||||
int
|
||||
wmi_ap_set_rateset(struct wmi_t *wmip, u8 rateset);
|
||||
|
||||
int
|
||||
wmi_set_ht_cap_cmd(struct wmi_t *wmip, WMI_SET_HT_CAP_CMD *cmd);
|
||||
|
||||
int
|
||||
wmi_set_ht_op_cmd(struct wmi_t *wmip, u8 sta_chan_width);
|
||||
|
||||
int
|
||||
wmi_send_hci_cmd(struct wmi_t *wmip, u8 *buf, u16 sz);
|
||||
|
||||
int
|
||||
wmi_set_tx_select_rates_cmd(struct wmi_t *wmip, u32 *pMaskArray);
|
||||
|
||||
int
|
||||
wmi_setup_aggr_cmd(struct wmi_t *wmip, u8 tid);
|
||||
|
||||
int
|
||||
wmi_delete_aggr_cmd(struct wmi_t *wmip, u8 tid, bool uplink);
|
||||
|
||||
int
|
||||
wmi_allow_aggr_cmd(struct wmi_t *wmip, u16 tx_tidmask, u16 rx_tidmask);
|
||||
|
||||
int
|
||||
wmi_set_rx_frame_format_cmd(struct wmi_t *wmip, u8 rxMetaVersion, bool rxDot11Hdr, bool defragOnHost);
|
||||
|
||||
int
|
||||
wmi_set_thin_mode_cmd(struct wmi_t *wmip, bool bThinMode);
|
||||
|
||||
int
|
||||
wmi_set_wlan_conn_precedence_cmd(struct wmi_t *wmip, BT_WLAN_CONN_PRECEDENCE precedence);
|
||||
|
||||
int
|
||||
wmi_set_pmk_cmd(struct wmi_t *wmip, u8 *pmk);
|
||||
|
||||
int
|
||||
wmi_set_excess_tx_retry_thres_cmd(struct wmi_t *wmip, WMI_SET_EXCESS_TX_RETRY_THRES_CMD *cmd);
|
||||
|
||||
u16 wmi_ieee2freq (int chan);
|
||||
|
||||
u32 wmi_freq2ieee (u16 freq);
|
||||
|
||||
bss_t *
|
||||
wmi_find_matching_Ssidnode (struct wmi_t *wmip, u8 *pSsid,
|
||||
u32 ssidLength,
|
||||
u32 dot11AuthMode, u32 authMode,
|
||||
u32 pairwiseCryptoType, u32 grpwiseCryptoTyp);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _WMI_API_H_ */
|
|
@ -1,565 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// AR3K configuration implementation
|
||||
//
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#include "a_config.h"
|
||||
#include "athdefs.h"
|
||||
#include "a_osapi.h"
|
||||
#define ATH_MODULE_NAME misc
|
||||
#include "a_debug.h"
|
||||
#include "common_drv.h"
|
||||
#ifdef EXPORT_HCI_BRIDGE_INTERFACE
|
||||
#include "export_hci_transport.h"
|
||||
#else
|
||||
#include "hci_transport_api.h"
|
||||
#endif
|
||||
#include "ar3kconfig.h"
|
||||
#include "tlpm.h"
|
||||
|
||||
#define BAUD_CHANGE_COMMAND_STATUS_OFFSET 5
|
||||
#define HCI_EVENT_RESP_TIMEOUTMS 3000
|
||||
#define HCI_CMD_OPCODE_BYTE_LOW_OFFSET 0
|
||||
#define HCI_CMD_OPCODE_BYTE_HI_OFFSET 1
|
||||
#define HCI_EVENT_OPCODE_BYTE_LOW 3
|
||||
#define HCI_EVENT_OPCODE_BYTE_HI 4
|
||||
#define HCI_CMD_COMPLETE_EVENT_CODE 0xE
|
||||
#define HCI_MAX_EVT_RECV_LENGTH 257
|
||||
#define EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET 5
|
||||
|
||||
int AthPSInitialize(struct ar3k_config_info *hdev);
|
||||
|
||||
static int SendHCICommand(struct ar3k_config_info *pConfig,
|
||||
u8 *pBuffer,
|
||||
int Length)
|
||||
{
|
||||
struct htc_packet *pPacket = NULL;
|
||||
int status = 0;
|
||||
|
||||
do {
|
||||
|
||||
pPacket = (struct htc_packet *)A_MALLOC(sizeof(struct htc_packet));
|
||||
if (NULL == pPacket) {
|
||||
status = A_NO_MEMORY;
|
||||
break;
|
||||
}
|
||||
|
||||
A_MEMZERO(pPacket,sizeof(struct htc_packet));
|
||||
SET_HTC_PACKET_INFO_TX(pPacket,
|
||||
NULL,
|
||||
pBuffer,
|
||||
Length,
|
||||
HCI_COMMAND_TYPE,
|
||||
AR6K_CONTROL_PKT_TAG);
|
||||
|
||||
/* issue synchronously */
|
||||
status = HCI_TransportSendPkt(pConfig->pHCIDev,pPacket,true);
|
||||
|
||||
} while (false);
|
||||
|
||||
if (pPacket != NULL) {
|
||||
kfree(pPacket);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int RecvHCIEvent(struct ar3k_config_info *pConfig,
|
||||
u8 *pBuffer,
|
||||
int *pLength)
|
||||
{
|
||||
int status = 0;
|
||||
struct htc_packet *pRecvPacket = NULL;
|
||||
|
||||
do {
|
||||
|
||||
pRecvPacket = (struct htc_packet *)A_MALLOC(sizeof(struct htc_packet));
|
||||
if (NULL == pRecvPacket) {
|
||||
status = A_NO_MEMORY;
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to alloc HTC struct \n"));
|
||||
break;
|
||||
}
|
||||
|
||||
A_MEMZERO(pRecvPacket,sizeof(struct htc_packet));
|
||||
|
||||
SET_HTC_PACKET_INFO_RX_REFILL(pRecvPacket,NULL,pBuffer,*pLength,HCI_EVENT_TYPE);
|
||||
|
||||
status = HCI_TransportRecvHCIEventSync(pConfig->pHCIDev,
|
||||
pRecvPacket,
|
||||
HCI_EVENT_RESP_TIMEOUTMS);
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
*pLength = pRecvPacket->ActualLength;
|
||||
|
||||
} while (false);
|
||||
|
||||
if (pRecvPacket != NULL) {
|
||||
kfree(pRecvPacket);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int SendHCICommandWaitCommandComplete(struct ar3k_config_info *pConfig,
|
||||
u8 *pHCICommand,
|
||||
int CmdLength,
|
||||
u8 **ppEventBuffer,
|
||||
u8 **ppBufferToFree)
|
||||
{
|
||||
int status = 0;
|
||||
u8 *pBuffer = NULL;
|
||||
u8 *pTemp;
|
||||
int length;
|
||||
bool commandComplete = false;
|
||||
u8 opCodeBytes[2];
|
||||
|
||||
do {
|
||||
|
||||
length = max(HCI_MAX_EVT_RECV_LENGTH,CmdLength);
|
||||
length += pConfig->pHCIProps->HeadRoom + pConfig->pHCIProps->TailRoom;
|
||||
length += pConfig->pHCIProps->IOBlockPad;
|
||||
|
||||
pBuffer = (u8 *)A_MALLOC(length);
|
||||
if (NULL == pBuffer) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Failed to allocate bt buffer \n"));
|
||||
status = A_NO_MEMORY;
|
||||
break;
|
||||
}
|
||||
|
||||
/* get the opcodes to check the command complete event */
|
||||
opCodeBytes[0] = pHCICommand[HCI_CMD_OPCODE_BYTE_LOW_OFFSET];
|
||||
opCodeBytes[1] = pHCICommand[HCI_CMD_OPCODE_BYTE_HI_OFFSET];
|
||||
|
||||
/* copy HCI command */
|
||||
memcpy(pBuffer + pConfig->pHCIProps->HeadRoom,pHCICommand,CmdLength);
|
||||
/* send command */
|
||||
status = SendHCICommand(pConfig,
|
||||
pBuffer + pConfig->pHCIProps->HeadRoom,
|
||||
CmdLength);
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Failed to send HCI Command (%d) \n", status));
|
||||
AR_DEBUG_PRINTBUF(pHCICommand,CmdLength,"HCI Bridge Failed HCI Command");
|
||||
break;
|
||||
}
|
||||
|
||||
/* reuse buffer to capture command complete event */
|
||||
A_MEMZERO(pBuffer,length);
|
||||
status = RecvHCIEvent(pConfig,pBuffer,&length);
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: HCI event recv failed \n"));
|
||||
AR_DEBUG_PRINTBUF(pHCICommand,CmdLength,"HCI Bridge Failed HCI Command");
|
||||
break;
|
||||
}
|
||||
|
||||
pTemp = pBuffer + pConfig->pHCIProps->HeadRoom;
|
||||
if (pTemp[0] == HCI_CMD_COMPLETE_EVENT_CODE) {
|
||||
if ((pTemp[HCI_EVENT_OPCODE_BYTE_LOW] == opCodeBytes[0]) &&
|
||||
(pTemp[HCI_EVENT_OPCODE_BYTE_HI] == opCodeBytes[1])) {
|
||||
commandComplete = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (!commandComplete) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Unexpected HCI event : %d \n",pTemp[0]));
|
||||
AR_DEBUG_PRINTBUF(pTemp,pTemp[1],"Unexpected HCI event");
|
||||
status = A_ECOMM;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ppEventBuffer != NULL) {
|
||||
/* caller wants to look at the event */
|
||||
*ppEventBuffer = pTemp;
|
||||
if (ppBufferToFree == NULL) {
|
||||
status = A_EINVAL;
|
||||
break;
|
||||
}
|
||||
/* caller must free the buffer */
|
||||
*ppBufferToFree = pBuffer;
|
||||
pBuffer = NULL;
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
if (pBuffer != NULL) {
|
||||
kfree(pBuffer);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int AR3KConfigureHCIBaud(struct ar3k_config_info *pConfig)
|
||||
{
|
||||
int status = 0;
|
||||
u8 hciBaudChangeCommand[] = {0x0c,0xfc,0x2,0,0};
|
||||
u16 baudVal;
|
||||
u8 *pEvent = NULL;
|
||||
u8 *pBufferToFree = NULL;
|
||||
|
||||
do {
|
||||
|
||||
if (pConfig->Flags & AR3K_CONFIG_FLAG_SET_AR3K_BAUD) {
|
||||
baudVal = (u16)(pConfig->AR3KBaudRate / 100);
|
||||
hciBaudChangeCommand[3] = (u8)baudVal;
|
||||
hciBaudChangeCommand[4] = (u8)(baudVal >> 8);
|
||||
|
||||
status = SendHCICommandWaitCommandComplete(pConfig,
|
||||
hciBaudChangeCommand,
|
||||
sizeof(hciBaudChangeCommand),
|
||||
&pEvent,
|
||||
&pBufferToFree);
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Baud rate change failed! \n"));
|
||||
break;
|
||||
}
|
||||
|
||||
if (pEvent[BAUD_CHANGE_COMMAND_STATUS_OFFSET] != 0) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
("AR3K Config: Baud change command event status failed: %d \n",
|
||||
pEvent[BAUD_CHANGE_COMMAND_STATUS_OFFSET]));
|
||||
status = A_ECOMM;
|
||||
break;
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
|
||||
("AR3K Config: Baud Changed to %d \n",pConfig->AR3KBaudRate));
|
||||
}
|
||||
|
||||
if (pConfig->Flags & AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY) {
|
||||
/* some versions of AR3K do not switch baud immediately, up to 300MS */
|
||||
A_MDELAY(325);
|
||||
}
|
||||
|
||||
if (pConfig->Flags & AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP) {
|
||||
/* Tell target to change UART baud rate for AR6K */
|
||||
status = HCI_TransportSetBaudRate(pConfig->pHCIDev, pConfig->AR3KBaudRate);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
("AR3K Config: failed to set scale and step values: %d \n", status));
|
||||
break;
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
|
||||
("AR3K Config: Baud changed to %d for AR6K\n", pConfig->AR3KBaudRate));
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
if (pBufferToFree != NULL) {
|
||||
kfree(pBufferToFree);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int AR3KExitMinBoot(struct ar3k_config_info *pConfig)
|
||||
{
|
||||
int status;
|
||||
char exitMinBootCmd[] = {0x25,0xFC,0x0c,0x03,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00};
|
||||
u8 *pEvent = NULL;
|
||||
u8 *pBufferToFree = NULL;
|
||||
|
||||
status = SendHCICommandWaitCommandComplete(pConfig,
|
||||
exitMinBootCmd,
|
||||
sizeof(exitMinBootCmd),
|
||||
&pEvent,
|
||||
&pBufferToFree);
|
||||
|
||||
if (!status) {
|
||||
if (pEvent[EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET] != 0) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
("AR3K Config: MinBoot exit command event status failed: %d \n",
|
||||
pEvent[EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET]));
|
||||
status = A_ECOMM;
|
||||
} else {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
|
||||
("AR3K Config: MinBoot Exit Command Complete (Success) \n"));
|
||||
A_MDELAY(1);
|
||||
}
|
||||
} else {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: MinBoot Exit Failed! \n"));
|
||||
}
|
||||
|
||||
if (pBufferToFree != NULL) {
|
||||
kfree(pBufferToFree);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int AR3KConfigureSendHCIReset(struct ar3k_config_info *pConfig)
|
||||
{
|
||||
int status = 0;
|
||||
u8 hciResetCommand[] = {0x03,0x0c,0x0};
|
||||
u8 *pEvent = NULL;
|
||||
u8 *pBufferToFree = NULL;
|
||||
|
||||
status = SendHCICommandWaitCommandComplete( pConfig,
|
||||
hciResetCommand,
|
||||
sizeof(hciResetCommand),
|
||||
&pEvent,
|
||||
&pBufferToFree );
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: HCI reset failed! \n"));
|
||||
}
|
||||
|
||||
if (pBufferToFree != NULL) {
|
||||
kfree(pBufferToFree);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int AR3KEnableTLPM(struct ar3k_config_info *pConfig)
|
||||
{
|
||||
int status;
|
||||
/* AR3K vendor specific command for Host Wakeup Config */
|
||||
char hostWakeupConfig[] = {0x31,0xFC,0x18,
|
||||
0x02,0x00,0x00,0x00,
|
||||
0x01,0x00,0x00,0x00,
|
||||
TLPM_DEFAULT_IDLE_TIMEOUT_LSB,TLPM_DEFAULT_IDLE_TIMEOUT_MSB,0x00,0x00, //idle timeout in ms
|
||||
0x00,0x00,0x00,0x00,
|
||||
TLPM_DEFAULT_WAKEUP_TIMEOUT_MS,0x00,0x00,0x00, //wakeup timeout in ms
|
||||
0x00,0x00,0x00,0x00};
|
||||
/* AR3K vendor specific command for Target Wakeup Config */
|
||||
char targetWakeupConfig[] = {0x31,0xFC,0x18,
|
||||
0x04,0x00,0x00,0x00,
|
||||
0x01,0x00,0x00,0x00,
|
||||
TLPM_DEFAULT_IDLE_TIMEOUT_LSB,TLPM_DEFAULT_IDLE_TIMEOUT_MSB,0x00,0x00, //idle timeout in ms
|
||||
0x00,0x00,0x00,0x00,
|
||||
TLPM_DEFAULT_WAKEUP_TIMEOUT_MS,0x00,0x00,0x00, //wakeup timeout in ms
|
||||
0x00,0x00,0x00,0x00};
|
||||
/* AR3K vendor specific command for Host Wakeup Enable */
|
||||
char hostWakeupEnable[] = {0x31,0xFC,0x4,
|
||||
0x01,0x00,0x00,0x00};
|
||||
/* AR3K vendor specific command for Target Wakeup Enable */
|
||||
char targetWakeupEnable[] = {0x31,0xFC,0x4,
|
||||
0x06,0x00,0x00,0x00};
|
||||
/* AR3K vendor specific command for Sleep Enable */
|
||||
char sleepEnable[] = {0x4,0xFC,0x1,
|
||||
0x1};
|
||||
u8 *pEvent = NULL;
|
||||
u8 *pBufferToFree = NULL;
|
||||
|
||||
if (0 != pConfig->IdleTimeout) {
|
||||
u8 idle_lsb = pConfig->IdleTimeout & 0xFF;
|
||||
u8 idle_msb = (pConfig->IdleTimeout & 0xFF00) >> 8;
|
||||
hostWakeupConfig[11] = targetWakeupConfig[11] = idle_lsb;
|
||||
hostWakeupConfig[12] = targetWakeupConfig[12] = idle_msb;
|
||||
}
|
||||
|
||||
if (0 != pConfig->WakeupTimeout) {
|
||||
hostWakeupConfig[19] = targetWakeupConfig[19] = (pConfig->WakeupTimeout & 0xFF);
|
||||
}
|
||||
|
||||
status = SendHCICommandWaitCommandComplete(pConfig,
|
||||
hostWakeupConfig,
|
||||
sizeof(hostWakeupConfig),
|
||||
&pEvent,
|
||||
&pBufferToFree);
|
||||
if (pBufferToFree != NULL) {
|
||||
kfree(pBufferToFree);
|
||||
}
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HostWakeup Config Failed! \n"));
|
||||
return status;
|
||||
}
|
||||
|
||||
pEvent = NULL;
|
||||
pBufferToFree = NULL;
|
||||
status = SendHCICommandWaitCommandComplete(pConfig,
|
||||
targetWakeupConfig,
|
||||
sizeof(targetWakeupConfig),
|
||||
&pEvent,
|
||||
&pBufferToFree);
|
||||
if (pBufferToFree != NULL) {
|
||||
kfree(pBufferToFree);
|
||||
}
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Target Wakeup Config Failed! \n"));
|
||||
return status;
|
||||
}
|
||||
|
||||
pEvent = NULL;
|
||||
pBufferToFree = NULL;
|
||||
status = SendHCICommandWaitCommandComplete(pConfig,
|
||||
hostWakeupEnable,
|
||||
sizeof(hostWakeupEnable),
|
||||
&pEvent,
|
||||
&pBufferToFree);
|
||||
if (pBufferToFree != NULL) {
|
||||
kfree(pBufferToFree);
|
||||
}
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HostWakeup Enable Failed! \n"));
|
||||
return status;
|
||||
}
|
||||
|
||||
pEvent = NULL;
|
||||
pBufferToFree = NULL;
|
||||
status = SendHCICommandWaitCommandComplete(pConfig,
|
||||
targetWakeupEnable,
|
||||
sizeof(targetWakeupEnable),
|
||||
&pEvent,
|
||||
&pBufferToFree);
|
||||
if (pBufferToFree != NULL) {
|
||||
kfree(pBufferToFree);
|
||||
}
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Target Wakeup Enable Failed! \n"));
|
||||
return status;
|
||||
}
|
||||
|
||||
pEvent = NULL;
|
||||
pBufferToFree = NULL;
|
||||
status = SendHCICommandWaitCommandComplete(pConfig,
|
||||
sleepEnable,
|
||||
sizeof(sleepEnable),
|
||||
&pEvent,
|
||||
&pBufferToFree);
|
||||
if (pBufferToFree != NULL) {
|
||||
kfree(pBufferToFree);
|
||||
}
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Sleep Enable Failed! \n"));
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Enable TLPM Completed (status = %d) \n",status));
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int AR3KConfigure(struct ar3k_config_info *pConfig)
|
||||
{
|
||||
int status = 0;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Configuring AR3K ...\n"));
|
||||
|
||||
do {
|
||||
|
||||
if ((pConfig->pHCIDev == NULL) || (pConfig->pHCIProps == NULL) || (pConfig->pHIFDevice == NULL)) {
|
||||
status = A_EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
/* disable asynchronous recv while we issue commands and receive events synchronously */
|
||||
status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,false);
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (pConfig->Flags & AR3K_CONFIG_FLAG_FORCE_MINBOOT_EXIT) {
|
||||
status = AR3KExitMinBoot(pConfig);
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Load patching and PST file if available*/
|
||||
if (0 != AthPSInitialize(pConfig)) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Patch Download Failed!\n"));
|
||||
}
|
||||
|
||||
/* Send HCI reset to make PS tags take effect*/
|
||||
AR3KConfigureSendHCIReset(pConfig);
|
||||
|
||||
if (pConfig->Flags &
|
||||
(AR3K_CONFIG_FLAG_SET_AR3K_BAUD | AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP)) {
|
||||
status = AR3KConfigureHCIBaud(pConfig);
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
if (pConfig->PwrMgmtEnabled) {
|
||||
/* the delay is required after the previous HCI reset before further
|
||||
* HCI commands can be issued
|
||||
*/
|
||||
A_MDELAY(200);
|
||||
AR3KEnableTLPM(pConfig);
|
||||
}
|
||||
|
||||
/* re-enable asynchronous recv */
|
||||
status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,true);
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
} while (false);
|
||||
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Configuration Complete (status = %d) \n",status));
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int AR3KConfigureExit(void *config)
|
||||
{
|
||||
int status = 0;
|
||||
struct ar3k_config_info *pConfig = (struct ar3k_config_info *)config;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Cleaning up AR3K ...\n"));
|
||||
|
||||
do {
|
||||
|
||||
if ((pConfig->pHCIDev == NULL) || (pConfig->pHCIProps == NULL) || (pConfig->pHIFDevice == NULL)) {
|
||||
status = A_EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
/* disable asynchronous recv while we issue commands and receive events synchronously */
|
||||
status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,false);
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (pConfig->Flags &
|
||||
(AR3K_CONFIG_FLAG_SET_AR3K_BAUD | AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP)) {
|
||||
status = AR3KConfigureHCIBaud(pConfig);
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable asynchronous recv */
|
||||
status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,true);
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
} while (false);
|
||||
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Cleanup Complete (status = %d) \n",status));
|
||||
|
||||
return status;
|
||||
}
|
||||
|
|
@ -1,572 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2004-2010 Atheros Communications Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This file implements the Atheros PS and patch downloaded for HCI UART Transport driver.
|
||||
* This file can be used for HCI SDIO transport implementation for AR6002 with HCI_TRANSPORT_SDIO
|
||||
* defined.
|
||||
*
|
||||
*
|
||||
* ar3kcpsconfig.c
|
||||
*
|
||||
*
|
||||
*
|
||||
* The software source and binaries included in this development package are
|
||||
* licensed, not sold. You, or your company, received the package under one
|
||||
* or more license agreements. The rights granted to you are specifically
|
||||
* listed in these license agreement(s). All other rights remain with Atheros
|
||||
* Communications, Inc., its subsidiaries, or the respective owner including
|
||||
* those listed on the included copyright notices.. Distribution of any
|
||||
* portion of this package must be in strict compliance with the license
|
||||
* agreement(s) terms.
|
||||
*
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#include "ar3kpsconfig.h"
|
||||
#ifndef HCI_TRANSPORT_SDIO
|
||||
#include "hci_ath.h"
|
||||
#include "hci_uart.h"
|
||||
#endif /* #ifndef HCI_TRANSPORT_SDIO */
|
||||
|
||||
#define MAX_FW_PATH_LEN 50
|
||||
#define MAX_BDADDR_FORMAT_LENGTH 30
|
||||
|
||||
/*
|
||||
* Structure used to send HCI packet, hci packet length and device info
|
||||
* together as parameter to PSThread.
|
||||
*/
|
||||
typedef struct {
|
||||
|
||||
struct ps_cmd_packet *HciCmdList;
|
||||
u32 num_packets;
|
||||
struct ar3k_config_info *dev;
|
||||
}HciCommandListParam;
|
||||
|
||||
int SendHCICommandWaitCommandComplete(struct ar3k_config_info *pConfig,
|
||||
u8 *pHCICommand,
|
||||
int CmdLength,
|
||||
u8 **ppEventBuffer,
|
||||
u8 **ppBufferToFree);
|
||||
|
||||
u32 Rom_Version;
|
||||
u32 Build_Version;
|
||||
extern bool BDADDR;
|
||||
|
||||
int getDeviceType(struct ar3k_config_info *pConfig, u32 *code);
|
||||
int ReadVersionInfo(struct ar3k_config_info *pConfig);
|
||||
#ifndef HCI_TRANSPORT_SDIO
|
||||
|
||||
DECLARE_WAIT_QUEUE_HEAD(PsCompleteEvent);
|
||||
DECLARE_WAIT_QUEUE_HEAD(HciEvent);
|
||||
u8 *HciEventpacket;
|
||||
rwlock_t syncLock;
|
||||
wait_queue_t Eventwait;
|
||||
|
||||
int PSHciWritepacket(struct hci_dev*,u8* Data, u32 len);
|
||||
extern char *bdaddr;
|
||||
#endif /* HCI_TRANSPORT_SDIO */
|
||||
|
||||
int write_bdaddr(struct ar3k_config_info *pConfig,u8 *bdaddr,int type);
|
||||
|
||||
int PSSendOps(void *arg);
|
||||
|
||||
#ifdef BT_PS_DEBUG
|
||||
void Hci_log(u8 * log_string,u8 *data,u32 len)
|
||||
{
|
||||
int i;
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s : ",log_string));
|
||||
for (i = 0; i < len; i++) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("0x%02x ", data[i]));
|
||||
}
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("\n...................................\n"));
|
||||
}
|
||||
#else
|
||||
#define Hci_log(string,data,len)
|
||||
#endif /* BT_PS_DEBUG */
|
||||
|
||||
|
||||
|
||||
|
||||
int AthPSInitialize(struct ar3k_config_info *hdev)
|
||||
{
|
||||
int status = 0;
|
||||
if(hdev == NULL) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Device handle received\n"));
|
||||
return A_ERROR;
|
||||
}
|
||||
|
||||
#ifndef HCI_TRANSPORT_SDIO
|
||||
DECLARE_WAITQUEUE(wait, current);
|
||||
#endif /* HCI_TRANSPORT_SDIO */
|
||||
|
||||
|
||||
#ifdef HCI_TRANSPORT_SDIO
|
||||
status = PSSendOps((void*)hdev);
|
||||
#else
|
||||
if(InitPSState(hdev) == -1) {
|
||||
return A_ERROR;
|
||||
}
|
||||
allow_signal(SIGKILL);
|
||||
add_wait_queue(&PsCompleteEvent,&wait);
|
||||
set_current_state(TASK_INTERRUPTIBLE);
|
||||
if(!kernel_thread(PSSendOps,(void*)hdev,CLONE_FS|CLONE_FILES|CLONE_SIGHAND|SIGCHLD)) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Kthread Failed\n"));
|
||||
remove_wait_queue(&PsCompleteEvent,&wait);
|
||||
return A_ERROR;
|
||||
}
|
||||
wait_event_interruptible(PsCompleteEvent,(PSTagMode == false));
|
||||
set_current_state(TASK_RUNNING);
|
||||
remove_wait_queue(&PsCompleteEvent,&wait);
|
||||
|
||||
#endif /* HCI_TRANSPORT_SDIO */
|
||||
|
||||
|
||||
return status;
|
||||
|
||||
}
|
||||
|
||||
int PSSendOps(void *arg)
|
||||
{
|
||||
int i;
|
||||
int status = 0;
|
||||
struct ps_cmd_packet *HciCmdList; /* List storing the commands */
|
||||
const struct firmware* firmware;
|
||||
u32 numCmds;
|
||||
u8 *event;
|
||||
u8 *bufferToFree;
|
||||
struct hci_dev *device;
|
||||
u8 *buffer;
|
||||
u32 len;
|
||||
u32 DevType;
|
||||
u8 *PsFileName;
|
||||
u8 *patchFileName;
|
||||
u8 *path = NULL;
|
||||
u8 *config_path = NULL;
|
||||
u8 config_bdaddr[MAX_BDADDR_FORMAT_LENGTH];
|
||||
struct ar3k_config_info *hdev = (struct ar3k_config_info*)arg;
|
||||
struct device *firmwareDev = NULL;
|
||||
status = 0;
|
||||
HciCmdList = NULL;
|
||||
#ifdef HCI_TRANSPORT_SDIO
|
||||
device = hdev->pBtStackHCIDev;
|
||||
firmwareDev = device->parent;
|
||||
#else
|
||||
device = hdev;
|
||||
firmwareDev = &device->dev;
|
||||
AthEnableSyncCommandOp(true);
|
||||
#endif /* HCI_TRANSPORT_SDIO */
|
||||
/* First verify if the controller is an FPGA or ASIC, so depending on the device type the PS file to be written will be different.
|
||||
*/
|
||||
|
||||
path =(u8 *)A_MALLOC(MAX_FW_PATH_LEN);
|
||||
if(path == NULL) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Malloc failed to allocate %d bytes for path\n", MAX_FW_PATH_LEN));
|
||||
goto complete;
|
||||
}
|
||||
config_path = (u8 *) A_MALLOC(MAX_FW_PATH_LEN);
|
||||
if(config_path == NULL) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Malloc failed to allocate %d bytes for config_path\n", MAX_FW_PATH_LEN));
|
||||
goto complete;
|
||||
}
|
||||
|
||||
if(A_ERROR == getDeviceType(hdev,&DevType)) {
|
||||
status = 1;
|
||||
goto complete;
|
||||
}
|
||||
if(A_ERROR == ReadVersionInfo(hdev)) {
|
||||
status = 1;
|
||||
goto complete;
|
||||
}
|
||||
|
||||
patchFileName = PATCH_FILE;
|
||||
snprintf(path, MAX_FW_PATH_LEN, "%s/%xcoex/",CONFIG_PATH,Rom_Version);
|
||||
if(DevType){
|
||||
if(DevType == 0xdeadc0de){
|
||||
PsFileName = PS_ASIC_FILE;
|
||||
} else{
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" FPGA Test Image : %x %x \n",Rom_Version,Build_Version));
|
||||
if((Rom_Version == 0x99999999) && (Build_Version == 1)){
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("FPGA Test Image : Skipping Patch File load\n"));
|
||||
patchFileName = NULL;
|
||||
}
|
||||
PsFileName = PS_FPGA_FILE;
|
||||
}
|
||||
}
|
||||
else{
|
||||
PsFileName = PS_ASIC_FILE;
|
||||
}
|
||||
|
||||
snprintf(config_path, MAX_FW_PATH_LEN, "%s%s",path,PsFileName);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%x: FPGA/ASIC PS File Name %s\n", DevType,config_path));
|
||||
/* Read the PS file to a dynamically allocated buffer */
|
||||
if(A_REQUEST_FIRMWARE(&firmware,config_path,firmwareDev) < 0) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ ));
|
||||
status = 1;
|
||||
goto complete;
|
||||
|
||||
}
|
||||
if(NULL == firmware || firmware->size == 0) {
|
||||
status = 1;
|
||||
goto complete;
|
||||
}
|
||||
buffer = (u8 *)A_MALLOC(firmware->size);
|
||||
if(buffer != NULL) {
|
||||
/* Copy the read file to a local Dynamic buffer */
|
||||
memcpy(buffer,firmware->data,firmware->size);
|
||||
len = firmware->size;
|
||||
A_RELEASE_FIRMWARE(firmware);
|
||||
/* Parse the PS buffer to a global variable */
|
||||
status = AthDoParsePS(buffer,len);
|
||||
kfree(buffer);
|
||||
} else {
|
||||
A_RELEASE_FIRMWARE(firmware);
|
||||
}
|
||||
|
||||
|
||||
/* Read the patch file to a dynamically allocated buffer */
|
||||
if(patchFileName != NULL)
|
||||
snprintf(config_path,
|
||||
MAX_FW_PATH_LEN, "%s%s",path,patchFileName);
|
||||
else {
|
||||
status = 0;
|
||||
}
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Patch File Name %s\n", config_path));
|
||||
if((patchFileName == NULL) || (A_REQUEST_FIRMWARE(&firmware,config_path,firmwareDev) < 0)) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ ));
|
||||
/*
|
||||
* It is not necessary that Patch file be available, continue with PS Operations if.
|
||||
* failed.
|
||||
*/
|
||||
status = 0;
|
||||
|
||||
} else {
|
||||
if(NULL == firmware || firmware->size == 0) {
|
||||
status = 0;
|
||||
} else {
|
||||
buffer = (u8 *)A_MALLOC(firmware->size);
|
||||
if(buffer != NULL) {
|
||||
/* Copy the read file to a local Dynamic buffer */
|
||||
memcpy(buffer,firmware->data,firmware->size);
|
||||
len = firmware->size;
|
||||
A_RELEASE_FIRMWARE(firmware);
|
||||
/* parse and store the Patch file contents to a global variables */
|
||||
status = AthDoParsePatch(buffer,len);
|
||||
kfree(buffer);
|
||||
} else {
|
||||
A_RELEASE_FIRMWARE(firmware);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Create an HCI command list from the parsed PS and patch information */
|
||||
AthCreateCommandList(&HciCmdList,&numCmds);
|
||||
|
||||
/* Form the parameter for PSSendOps() API */
|
||||
|
||||
|
||||
/*
|
||||
* First Send the CRC packet,
|
||||
* We have to continue with the PS operations only if the CRC packet has been replied with
|
||||
* a Command complete event with status Error.
|
||||
*/
|
||||
|
||||
if(SendHCICommandWaitCommandComplete
|
||||
(hdev,
|
||||
HciCmdList[0].Hcipacket,
|
||||
HciCmdList[0].packetLen,
|
||||
&event,
|
||||
&bufferToFree) == 0) {
|
||||
if(ReadPSEvent(event) == 0) { /* Exit if the status is success */
|
||||
if(bufferToFree != NULL) {
|
||||
kfree(bufferToFree);
|
||||
}
|
||||
|
||||
#ifndef HCI_TRANSPORT_SDIO
|
||||
if(bdaddr && bdaddr[0] !='\0') {
|
||||
write_bdaddr(hdev,bdaddr,BDADDR_TYPE_STRING);
|
||||
}
|
||||
#endif
|
||||
status = 1;
|
||||
goto complete;
|
||||
}
|
||||
if(bufferToFree != NULL) {
|
||||
kfree(bufferToFree);
|
||||
}
|
||||
} else {
|
||||
status = 0;
|
||||
goto complete;
|
||||
}
|
||||
|
||||
for(i = 1; i <numCmds; i++) {
|
||||
|
||||
if(SendHCICommandWaitCommandComplete
|
||||
(hdev,
|
||||
HciCmdList[i].Hcipacket,
|
||||
HciCmdList[i].packetLen,
|
||||
&event,
|
||||
&bufferToFree) == 0) {
|
||||
if(ReadPSEvent(event) != 0) { /* Exit if the status is success */
|
||||
if(bufferToFree != NULL) {
|
||||
kfree(bufferToFree);
|
||||
}
|
||||
status = 1;
|
||||
goto complete;
|
||||
}
|
||||
if(bufferToFree != NULL) {
|
||||
kfree(bufferToFree);
|
||||
}
|
||||
} else {
|
||||
status = 0;
|
||||
goto complete;
|
||||
}
|
||||
}
|
||||
#ifdef HCI_TRANSPORT_SDIO
|
||||
if(BDADDR == false)
|
||||
if(hdev->bdaddr[0] !=0x00 ||
|
||||
hdev->bdaddr[1] !=0x00 ||
|
||||
hdev->bdaddr[2] !=0x00 ||
|
||||
hdev->bdaddr[3] !=0x00 ||
|
||||
hdev->bdaddr[4] !=0x00 ||
|
||||
hdev->bdaddr[5] !=0x00)
|
||||
write_bdaddr(hdev,hdev->bdaddr,BDADDR_TYPE_HEX);
|
||||
|
||||
#ifndef HCI_TRANSPORT_SDIO
|
||||
|
||||
if(bdaddr && bdaddr[0] != '\0') {
|
||||
write_bdaddr(hdev,bdaddr,BDADDR_TYPE_STRING);
|
||||
} else
|
||||
#endif /* HCI_TRANSPORT_SDIO */
|
||||
/* Write BDADDR Read from OTP here */
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
{
|
||||
/* Read Contents of BDADDR file if user has not provided any option */
|
||||
snprintf(config_path,MAX_FW_PATH_LEN, "%s%s",path,BDADDR_FILE);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Patch File Name %s\n", config_path));
|
||||
if(A_REQUEST_FIRMWARE(&firmware,config_path,firmwareDev) < 0) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ ));
|
||||
status = 1;
|
||||
goto complete;
|
||||
}
|
||||
if(NULL == firmware || firmware->size == 0) {
|
||||
status = 1;
|
||||
goto complete;
|
||||
}
|
||||
len = min_t(size_t, firmware->size, MAX_BDADDR_FORMAT_LENGTH - 1);
|
||||
memcpy(config_bdaddr, firmware->data, len);
|
||||
config_bdaddr[len] = '\0';
|
||||
write_bdaddr(hdev,config_bdaddr,BDADDR_TYPE_STRING);
|
||||
A_RELEASE_FIRMWARE(firmware);
|
||||
}
|
||||
complete:
|
||||
#ifndef HCI_TRANSPORT_SDIO
|
||||
AthEnableSyncCommandOp(false);
|
||||
PSTagMode = false;
|
||||
wake_up_interruptible(&PsCompleteEvent);
|
||||
#endif /* HCI_TRANSPORT_SDIO */
|
||||
if(NULL != HciCmdList) {
|
||||
AthFreeCommandList(&HciCmdList,numCmds);
|
||||
}
|
||||
if(path) {
|
||||
kfree(path);
|
||||
}
|
||||
if(config_path) {
|
||||
kfree(config_path);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
#ifndef HCI_TRANSPORT_SDIO
|
||||
/*
|
||||
* This API is used to send the HCI command to controller and return
|
||||
* with a HCI Command Complete event.
|
||||
* For HCI SDIO transport, this will be internally defined.
|
||||
*/
|
||||
int SendHCICommandWaitCommandComplete(struct ar3k_config_info *pConfig,
|
||||
u8 *pHCICommand,
|
||||
int CmdLength,
|
||||
u8 **ppEventBuffer,
|
||||
u8 **ppBufferToFree)
|
||||
{
|
||||
if(CmdLength == 0) {
|
||||
return A_ERROR;
|
||||
}
|
||||
Hci_log("COM Write -->",pHCICommand,CmdLength);
|
||||
PSAcked = false;
|
||||
if(PSHciWritepacket(pConfig,pHCICommand,CmdLength) == 0) {
|
||||
/* If the controller is not available, return Error */
|
||||
return A_ERROR;
|
||||
}
|
||||
//add_timer(&psCmdTimer);
|
||||
wait_event_interruptible(HciEvent,(PSAcked == true));
|
||||
if(NULL != HciEventpacket) {
|
||||
*ppEventBuffer = HciEventpacket;
|
||||
*ppBufferToFree = HciEventpacket;
|
||||
} else {
|
||||
/* Did not get an event from controller. return error */
|
||||
*ppBufferToFree = NULL;
|
||||
return A_ERROR;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* HCI_TRANSPORT_SDIO */
|
||||
|
||||
int ReadPSEvent(u8* Data){
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" PS Event %x %x %x\n",Data[4],Data[5],Data[3]));
|
||||
|
||||
if(Data[4] == 0xFC && Data[5] == 0x00)
|
||||
{
|
||||
switch(Data[3]){
|
||||
case 0x0B:
|
||||
return 0;
|
||||
break;
|
||||
case 0x0C:
|
||||
/* Change Baudrate */
|
||||
return 0;
|
||||
break;
|
||||
case 0x04:
|
||||
return 0;
|
||||
break;
|
||||
case 0x1E:
|
||||
Rom_Version = Data[9];
|
||||
Rom_Version = ((Rom_Version << 8) |Data[8]);
|
||||
Rom_Version = ((Rom_Version << 8) |Data[7]);
|
||||
Rom_Version = ((Rom_Version << 8) |Data[6]);
|
||||
|
||||
Build_Version = Data[13];
|
||||
Build_Version = ((Build_Version << 8) |Data[12]);
|
||||
Build_Version = ((Build_Version << 8) |Data[11]);
|
||||
Build_Version = ((Build_Version << 8) |Data[10]);
|
||||
return 0;
|
||||
break;
|
||||
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
return A_ERROR;
|
||||
}
|
||||
int str2ba(unsigned char *str_bdaddr,unsigned char *bdaddr)
|
||||
{
|
||||
unsigned char bdbyte[3];
|
||||
unsigned char *str_byte = str_bdaddr;
|
||||
int i,j;
|
||||
unsigned char colon_present = 0;
|
||||
|
||||
if(NULL != strstr(str_bdaddr,":")) {
|
||||
colon_present = 1;
|
||||
}
|
||||
|
||||
|
||||
bdbyte[2] = '\0';
|
||||
|
||||
for( i = 0,j = 5; i < 6; i++, j--) {
|
||||
bdbyte[0] = str_byte[0];
|
||||
bdbyte[1] = str_byte[1];
|
||||
bdaddr[j] = A_STRTOL(bdbyte,NULL,16);
|
||||
if(colon_present == 1) {
|
||||
str_byte+=3;
|
||||
} else {
|
||||
str_byte+=2;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int write_bdaddr(struct ar3k_config_info *pConfig,u8 *bdaddr,int type)
|
||||
{
|
||||
u8 bdaddr_cmd[] = { 0x0B, 0xFC, 0x0A, 0x01, 0x01,
|
||||
0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
|
||||
|
||||
u8 *event;
|
||||
u8 *bufferToFree = NULL;
|
||||
int result = A_ERROR;
|
||||
int inc,outc;
|
||||
|
||||
if (type == BDADDR_TYPE_STRING)
|
||||
str2ba(bdaddr,&bdaddr_cmd[7]);
|
||||
else {
|
||||
/* Bdaddr has to be sent as LAP first */
|
||||
for(inc = 5 ,outc = 7; inc >=0; inc--, outc++)
|
||||
bdaddr_cmd[outc] = bdaddr[inc];
|
||||
}
|
||||
|
||||
if(0 == SendHCICommandWaitCommandComplete(pConfig,bdaddr_cmd,
|
||||
sizeof(bdaddr_cmd),
|
||||
&event,&bufferToFree)) {
|
||||
|
||||
if(event[4] == 0xFC && event[5] == 0x00){
|
||||
if(event[3] == 0x0B){
|
||||
result = 0;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
if(bufferToFree != NULL) {
|
||||
kfree(bufferToFree);
|
||||
}
|
||||
return result;
|
||||
|
||||
}
|
||||
int ReadVersionInfo(struct ar3k_config_info *pConfig)
|
||||
{
|
||||
u8 hciCommand[] = {0x1E,0xfc,0x00};
|
||||
u8 *event;
|
||||
u8 *bufferToFree = NULL;
|
||||
int result = A_ERROR;
|
||||
if(0 == SendHCICommandWaitCommandComplete(pConfig,hciCommand,sizeof(hciCommand),&event,&bufferToFree)) {
|
||||
result = ReadPSEvent(event);
|
||||
|
||||
}
|
||||
if(bufferToFree != NULL) {
|
||||
kfree(bufferToFree);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
int getDeviceType(struct ar3k_config_info *pConfig, u32 *code)
|
||||
{
|
||||
u8 hciCommand[] = {0x05,0xfc,0x05,0x00,0x00,0x00,0x00,0x04};
|
||||
u8 *event;
|
||||
u8 *bufferToFree = NULL;
|
||||
u32 reg;
|
||||
int result = A_ERROR;
|
||||
*code = 0;
|
||||
hciCommand[3] = (u8)(FPGA_REGISTER & 0xFF);
|
||||
hciCommand[4] = (u8)((FPGA_REGISTER >> 8) & 0xFF);
|
||||
hciCommand[5] = (u8)((FPGA_REGISTER >> 16) & 0xFF);
|
||||
hciCommand[6] = (u8)((FPGA_REGISTER >> 24) & 0xFF);
|
||||
if(0 == SendHCICommandWaitCommandComplete(pConfig,hciCommand,sizeof(hciCommand),&event,&bufferToFree)) {
|
||||
|
||||
if(event[4] == 0xFC && event[5] == 0x00){
|
||||
switch(event[3]){
|
||||
case 0x05:
|
||||
reg = event[9];
|
||||
reg = ((reg << 8) |event[8]);
|
||||
reg = ((reg << 8) |event[7]);
|
||||
reg = ((reg << 8) |event[6]);
|
||||
*code = reg;
|
||||
result = 0;
|
||||
|
||||
break;
|
||||
case 0x06:
|
||||
//Sleep(500);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
if(bufferToFree != NULL) {
|
||||
kfree(bufferToFree);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2004-2010 Atheros Communications Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This file defines the symbols exported by Atheros PS and patch download module.
|
||||
* define the constant HCI_TRANSPORT_SDIO if the module is being used for HCI SDIO transport.
|
||||
* defined.
|
||||
*
|
||||
*
|
||||
* ar3kcpsconfig.h
|
||||
*
|
||||
*
|
||||
*
|
||||
* The software source and binaries included in this development package are
|
||||
* licensed, not sold. You, or your company, received the package under one
|
||||
* or more license agreements. The rights granted to you are specifically
|
||||
* listed in these license agreement(s). All other rights remain with Atheros
|
||||
* Communications, Inc., its subsidiaries, or the respective owner including
|
||||
* those listed on the included copyright notices.. Distribution of any
|
||||
* portion of this package must be in strict compliance with the license
|
||||
* agreement(s) terms.
|
||||
*
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef __AR3KPSCONFIG_H
|
||||
#define __AR3KPSCONFIG_H
|
||||
|
||||
/*
|
||||
* Define the flag HCI_TRANSPORT_SDIO and undefine HCI_TRANSPORT_UART if the transport being used is SDIO.
|
||||
*/
|
||||
#undef HCI_TRANSPORT_UART
|
||||
|
||||
#include <linux/fs.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/signal.h>
|
||||
|
||||
|
||||
#include <linux/ioctl.h>
|
||||
#include <linux/firmware.h>
|
||||
|
||||
|
||||
#include <net/bluetooth/bluetooth.h>
|
||||
#include <net/bluetooth/hci_core.h>
|
||||
|
||||
#include "ar3kpsparser.h"
|
||||
|
||||
#define FPGA_REGISTER 0x4FFC
|
||||
#define BDADDR_TYPE_STRING 0
|
||||
#define BDADDR_TYPE_HEX 1
|
||||
#define CONFIG_PATH "ar3k"
|
||||
|
||||
#define PS_ASIC_FILE "PS_ASIC.pst"
|
||||
#define PS_FPGA_FILE "PS_FPGA.pst"
|
||||
|
||||
#define PATCH_FILE "RamPatch.txt"
|
||||
#define BDADDR_FILE "ar3kbdaddr.pst"
|
||||
|
||||
#define ROM_VER_AR3001_3_1_0 30000
|
||||
#define ROM_VER_AR3001_3_1_1 30101
|
||||
|
||||
|
||||
#ifndef HCI_TRANSPORT_SDIO
|
||||
#define struct ar3k_config_info struct hci_dev
|
||||
extern wait_queue_head_t HciEvent;
|
||||
extern wait_queue_t Eventwait;
|
||||
extern u8 *HciEventpacket;
|
||||
#endif /* #ifndef HCI_TRANSPORT_SDIO */
|
||||
|
||||
int AthPSInitialize(struct ar3k_config_info *hdev);
|
||||
int ReadPSEvent(u8* Data);
|
||||
#endif /* __AR3KPSCONFIG_H */
|
|
@ -1,969 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2004-2010 Atheros Communications Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This file implements the Atheros PS and patch parser.
|
||||
* It implements APIs to parse data buffer with patch and PS information and convert it to HCI commands.
|
||||
*
|
||||
*
|
||||
*
|
||||
* ar3kpsparser.c
|
||||
*
|
||||
*
|
||||
*
|
||||
* The software source and binaries included in this development package are
|
||||
* licensed, not sold. You, or your company, received the package under one
|
||||
* or more license agreements. The rights granted to you are specifically
|
||||
* listed in these license agreement(s). All other rights remain with Atheros
|
||||
* Communications, Inc., its subsidiaries, or the respective owner including
|
||||
* those listed on the included copyright notices.. Distribution of any
|
||||
* portion of this package must be in strict compliance with the license
|
||||
* agreement(s) terms.
|
||||
*
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#include "ar3kpsparser.h"
|
||||
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#define BD_ADDR_SIZE 6
|
||||
#define WRITE_PATCH 8
|
||||
#define ENABLE_PATCH 11
|
||||
#define PS_RESET 2
|
||||
#define PS_WRITE 1
|
||||
#define PS_VERIFY_CRC 9
|
||||
#define CHANGE_BDADDR 15
|
||||
|
||||
#define HCI_COMMAND_HEADER 7
|
||||
|
||||
#define HCI_EVENT_SIZE 7
|
||||
|
||||
#define WRITE_PATCH_COMMAND_STATUS_OFFSET 5
|
||||
|
||||
#define PS_RAM_SIZE 2048
|
||||
|
||||
#define RAM_PS_REGION (1<<0)
|
||||
#define RAM_PATCH_REGION (1<<1)
|
||||
#define RAMPS_MAX_PS_DATA_PER_TAG 20000
|
||||
#define MAX_RADIO_CFG_TABLE_SIZE 244
|
||||
#define RAMPS_MAX_PS_TAGS_PER_FILE 50
|
||||
|
||||
#define PS_MAX_LEN 500
|
||||
#define LINE_SIZE_MAX (PS_MAX_LEN *2)
|
||||
|
||||
/* Constant values used by parser */
|
||||
#define BYTES_OF_PS_DATA_PER_LINE 16
|
||||
#define RAMPS_MAX_PS_DATA_PER_TAG 20000
|
||||
|
||||
|
||||
/* Number pf PS/Patch entries in an HCI packet */
|
||||
#define MAX_BYTE_LENGTH 244
|
||||
|
||||
#define SKIP_BLANKS(str) while (*str == ' ') str++
|
||||
|
||||
enum MinBootFileFormatE
|
||||
{
|
||||
MB_FILEFORMAT_RADIOTBL,
|
||||
MB_FILEFORMAT_PATCH,
|
||||
MB_FILEFORMAT_COEXCONFIG
|
||||
};
|
||||
|
||||
enum RamPsSection
|
||||
{
|
||||
RAM_PS_SECTION,
|
||||
RAM_PATCH_SECTION,
|
||||
RAM_DYN_MEM_SECTION
|
||||
};
|
||||
|
||||
enum eType {
|
||||
eHex,
|
||||
edecimal
|
||||
};
|
||||
|
||||
|
||||
typedef struct tPsTagEntry
|
||||
{
|
||||
u32 TagId;
|
||||
u32 TagLen;
|
||||
u8 *TagData;
|
||||
} tPsTagEntry, *tpPsTagEntry;
|
||||
|
||||
typedef struct tRamPatch
|
||||
{
|
||||
u16 Len;
|
||||
u8 *Data;
|
||||
} tRamPatch, *ptRamPatch;
|
||||
|
||||
|
||||
|
||||
struct st_ps_data_format {
|
||||
enum eType eDataType;
|
||||
bool bIsArray;
|
||||
};
|
||||
|
||||
struct st_read_status {
|
||||
unsigned uTagID;
|
||||
unsigned uSection;
|
||||
unsigned uLineCount;
|
||||
unsigned uCharCount;
|
||||
unsigned uByteCount;
|
||||
};
|
||||
|
||||
|
||||
/* Stores the number of PS Tags */
|
||||
static u32 Tag_Count = 0;
|
||||
|
||||
/* Stores the number of patch commands */
|
||||
static u32 Patch_Count = 0;
|
||||
static u32 Total_tag_lenght = 0;
|
||||
bool BDADDR = false;
|
||||
u32 StartTagId;
|
||||
|
||||
tPsTagEntry PsTagEntry[RAMPS_MAX_PS_TAGS_PER_FILE];
|
||||
tRamPatch RamPatch[MAX_NUM_PATCH_ENTRY];
|
||||
|
||||
|
||||
int AthParseFilesUnified(u8 *srcbuffer,u32 srclen, int FileFormat);
|
||||
char AthReadChar(u8 *buffer, u32 len,u32 *pos);
|
||||
char *AthGetLine(char *buffer, int maxlen, u8 *srcbuffer,u32 len,u32 *pos);
|
||||
static int AthPSCreateHCICommand(u8 Opcode, u32 Param1,struct ps_cmd_packet *PSPatchPacket,u32 *index);
|
||||
|
||||
/* Function to reads the next character from the input buffer */
|
||||
char AthReadChar(u8 *buffer, u32 len,u32 *pos)
|
||||
{
|
||||
char Ch;
|
||||
if(buffer == NULL || *pos >=len )
|
||||
{
|
||||
return '\0';
|
||||
} else {
|
||||
Ch = buffer[*pos];
|
||||
(*pos)++;
|
||||
return Ch;
|
||||
}
|
||||
}
|
||||
/* PS parser helper function */
|
||||
unsigned int uGetInputDataFormat(char *pCharLine, struct st_ps_data_format *pstFormat)
|
||||
{
|
||||
if(pCharLine[0] != '[') {
|
||||
pstFormat->eDataType = eHex;
|
||||
pstFormat->bIsArray = true;
|
||||
return 0;
|
||||
}
|
||||
switch(pCharLine[1]) {
|
||||
case 'H':
|
||||
case 'h':
|
||||
if(pCharLine[2]==':') {
|
||||
if((pCharLine[3]== 'a') || (pCharLine[3]== 'A')) {
|
||||
if(pCharLine[4] == ']') {
|
||||
pstFormat->eDataType = eHex;
|
||||
pstFormat->bIsArray = true;
|
||||
pCharLine += 5;
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n")); //[H:A
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
if((pCharLine[3]== 'S') || (pCharLine[3]== 's')) {
|
||||
if(pCharLine[4] == ']') {
|
||||
pstFormat->eDataType = eHex;
|
||||
pstFormat->bIsArray = false;
|
||||
pCharLine += 5;
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n")); //[H:A
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
else if(pCharLine[3] == ']') { //[H:]
|
||||
pstFormat->eDataType = eHex;
|
||||
pstFormat->bIsArray = true;
|
||||
pCharLine += 4;
|
||||
return 0;
|
||||
}
|
||||
else { //[H:
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n"));
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
else if(pCharLine[2]==']') { //[H]
|
||||
pstFormat->eDataType = eHex;
|
||||
pstFormat->bIsArray = true;
|
||||
pCharLine += 3;
|
||||
return 0;
|
||||
}
|
||||
else { //[H
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n"));
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case 'A':
|
||||
case 'a':
|
||||
if(pCharLine[2]==':') {
|
||||
if((pCharLine[3]== 'h') || (pCharLine[3]== 'H')) {
|
||||
if(pCharLine[4] == ']') {
|
||||
pstFormat->eDataType = eHex;
|
||||
pstFormat->bIsArray = true;
|
||||
pCharLine += 5;
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 1\n")); //[A:H
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
else if(pCharLine[3]== ']') { //[A:]
|
||||
pstFormat->eDataType = eHex;
|
||||
pstFormat->bIsArray = true;
|
||||
pCharLine += 4;
|
||||
return 0;
|
||||
}
|
||||
else { //[A:
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 2\n"));
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
else if(pCharLine[2]==']') { //[H]
|
||||
pstFormat->eDataType = eHex;
|
||||
pstFormat->bIsArray = true;
|
||||
pCharLine += 3;
|
||||
return 0;
|
||||
}
|
||||
else { //[H
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 3\n"));
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case 'S':
|
||||
case 's':
|
||||
if(pCharLine[2]==':') {
|
||||
if((pCharLine[3]== 'h') || (pCharLine[3]== 'H')) {
|
||||
if(pCharLine[4] == ']') {
|
||||
pstFormat->eDataType = eHex;
|
||||
pstFormat->bIsArray = true;
|
||||
pCharLine += 5;
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 5\n")); //[A:H
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
else if(pCharLine[3]== ']') { //[A:]
|
||||
pstFormat->eDataType = eHex;
|
||||
pstFormat->bIsArray = true;
|
||||
pCharLine += 4;
|
||||
return 0;
|
||||
}
|
||||
else { //[A:
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 6\n"));
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
else if(pCharLine[2]==']') { //[H]
|
||||
pstFormat->eDataType = eHex;
|
||||
pstFormat->bIsArray = true;
|
||||
pCharLine += 3;
|
||||
return 0;
|
||||
}
|
||||
else { //[H
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 7\n"));
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 8\n"));
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned int uReadDataInSection(char *pCharLine, struct st_ps_data_format stPS_DataFormat)
|
||||
{
|
||||
char *pTokenPtr = pCharLine;
|
||||
|
||||
if(pTokenPtr[0] == '[') {
|
||||
while(pTokenPtr[0] != ']' && pTokenPtr[0] != '\0') {
|
||||
pTokenPtr++;
|
||||
}
|
||||
if(pTokenPtr[0] == '\0') {
|
||||
return (0x0FFF);
|
||||
}
|
||||
pTokenPtr++;
|
||||
|
||||
|
||||
}
|
||||
if(stPS_DataFormat.eDataType == eHex) {
|
||||
if(stPS_DataFormat.bIsArray == true) {
|
||||
//Not implemented
|
||||
return (0x0FFF);
|
||||
}
|
||||
else {
|
||||
return (A_STRTOL(pTokenPtr, NULL, 16));
|
||||
}
|
||||
}
|
||||
else {
|
||||
//Not implemented
|
||||
return (0x0FFF);
|
||||
}
|
||||
}
|
||||
int AthParseFilesUnified(u8 *srcbuffer,u32 srclen, int FileFormat)
|
||||
{
|
||||
char *Buffer;
|
||||
char *pCharLine;
|
||||
u8 TagCount;
|
||||
u16 ByteCount;
|
||||
u8 ParseSection=RAM_PS_SECTION;
|
||||
u32 pos;
|
||||
|
||||
|
||||
|
||||
int uReadCount;
|
||||
struct st_ps_data_format stPS_DataFormat;
|
||||
struct st_read_status stReadStatus = {0, 0, 0,0};
|
||||
pos = 0;
|
||||
Buffer = NULL;
|
||||
|
||||
if (srcbuffer == NULL || srclen == 0)
|
||||
{
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Could not open .\n"));
|
||||
return A_ERROR;
|
||||
}
|
||||
TagCount = 0;
|
||||
ByteCount = 0;
|
||||
Buffer = A_MALLOC(LINE_SIZE_MAX + 1);
|
||||
if(NULL == Buffer) {
|
||||
return A_ERROR;
|
||||
}
|
||||
if (FileFormat == MB_FILEFORMAT_PATCH)
|
||||
{
|
||||
int LineRead = 0;
|
||||
while((pCharLine = AthGetLine(Buffer, LINE_SIZE_MAX, srcbuffer,srclen,&pos)) != NULL)
|
||||
{
|
||||
|
||||
SKIP_BLANKS(pCharLine);
|
||||
|
||||
// Comment line or empty line
|
||||
if ((pCharLine[0] == '/') && (pCharLine[1] == '/'))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
if ((pCharLine[0] == '#')) {
|
||||
if (stReadStatus.uSection != 0)
|
||||
{
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("error\n"));
|
||||
if(Buffer != NULL) {
|
||||
kfree(Buffer);
|
||||
}
|
||||
return A_ERROR;
|
||||
}
|
||||
else {
|
||||
stReadStatus.uSection = 1;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
if ((pCharLine[0] == '/') && (pCharLine[1] == '*'))
|
||||
{
|
||||
pCharLine+=2;
|
||||
SKIP_BLANKS(pCharLine);
|
||||
|
||||
if(!strncmp(pCharLine,"PA",2)||!strncmp(pCharLine,"Pa",2)||!strncmp(pCharLine,"pa",2))
|
||||
ParseSection=RAM_PATCH_SECTION;
|
||||
|
||||
if(!strncmp(pCharLine,"DY",2)||!strncmp(pCharLine,"Dy",2)||!strncmp(pCharLine,"dy",2))
|
||||
ParseSection=RAM_DYN_MEM_SECTION;
|
||||
|
||||
if(!strncmp(pCharLine,"PS",2)||!strncmp(pCharLine,"Ps",2)||!strncmp(pCharLine,"ps",2))
|
||||
ParseSection=RAM_PS_SECTION;
|
||||
|
||||
LineRead = 0;
|
||||
stReadStatus.uSection = 0;
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
switch(ParseSection)
|
||||
{
|
||||
case RAM_PS_SECTION:
|
||||
{
|
||||
if (stReadStatus.uSection == 1) //TagID
|
||||
{
|
||||
SKIP_BLANKS(pCharLine);
|
||||
if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail\n"));
|
||||
if(Buffer != NULL) {
|
||||
kfree(Buffer);
|
||||
}
|
||||
return A_ERROR;
|
||||
}
|
||||
//pCharLine +=5;
|
||||
PsTagEntry[TagCount].TagId = uReadDataInSection(pCharLine, stPS_DataFormat);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" TAG ID %d \n",PsTagEntry[TagCount].TagId));
|
||||
|
||||
//AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("tag # %x\n", PsTagEntry[TagCount].TagId);
|
||||
if (TagCount == 0)
|
||||
{
|
||||
StartTagId = PsTagEntry[TagCount].TagId;
|
||||
}
|
||||
stReadStatus.uSection = 2;
|
||||
}
|
||||
else if (stReadStatus.uSection == 2) //TagLength
|
||||
{
|
||||
|
||||
if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail \n"));
|
||||
if(Buffer != NULL) {
|
||||
kfree(Buffer);
|
||||
}
|
||||
return A_ERROR;
|
||||
}
|
||||
//pCharLine +=5;
|
||||
ByteCount = uReadDataInSection(pCharLine, stPS_DataFormat);
|
||||
|
||||
//AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("tag length %x\n", ByteCount));
|
||||
if (ByteCount > LINE_SIZE_MAX/2)
|
||||
{
|
||||
if(Buffer != NULL) {
|
||||
kfree(Buffer);
|
||||
}
|
||||
return A_ERROR;
|
||||
}
|
||||
PsTagEntry[TagCount].TagLen = ByteCount;
|
||||
PsTagEntry[TagCount].TagData = (u8 *)A_MALLOC(ByteCount);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" TAG Length %d Tag Index %d \n",PsTagEntry[TagCount].TagLen,TagCount));
|
||||
stReadStatus.uSection = 3;
|
||||
stReadStatus.uLineCount = 0;
|
||||
}
|
||||
else if( stReadStatus.uSection == 3) { //Data
|
||||
|
||||
if(stReadStatus.uLineCount == 0) {
|
||||
if(uGetInputDataFormat(pCharLine,&stPS_DataFormat)) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat Fail\n"));
|
||||
if(Buffer != NULL) {
|
||||
kfree(Buffer);
|
||||
}
|
||||
return A_ERROR;
|
||||
}
|
||||
//pCharLine +=5;
|
||||
}
|
||||
SKIP_BLANKS(pCharLine);
|
||||
stReadStatus.uCharCount = 0;
|
||||
if(pCharLine[stReadStatus.uCharCount] == '[') {
|
||||
while(pCharLine[stReadStatus.uCharCount] != ']' && pCharLine[stReadStatus.uCharCount] != '\0' ) {
|
||||
stReadStatus.uCharCount++;
|
||||
}
|
||||
if(pCharLine[stReadStatus.uCharCount] == ']' ) {
|
||||
stReadStatus.uCharCount++;
|
||||
} else {
|
||||
stReadStatus.uCharCount = 0;
|
||||
}
|
||||
}
|
||||
uReadCount = (ByteCount > BYTES_OF_PS_DATA_PER_LINE)? BYTES_OF_PS_DATA_PER_LINE: ByteCount;
|
||||
//AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" "));
|
||||
if((stPS_DataFormat.eDataType == eHex) && stPS_DataFormat.bIsArray == true) {
|
||||
while(uReadCount > 0) {
|
||||
PsTagEntry[TagCount].TagData[stReadStatus.uByteCount] =
|
||||
(u8)(hex_to_bin(pCharLine[stReadStatus.uCharCount]) << 4)
|
||||
| (u8)(hex_to_bin(pCharLine[stReadStatus.uCharCount + 1]));
|
||||
|
||||
PsTagEntry[TagCount].TagData[stReadStatus.uByteCount+1] =
|
||||
(u8)(hex_to_bin(pCharLine[stReadStatus.uCharCount + 3]) << 4)
|
||||
| (u8)(hex_to_bin(pCharLine[stReadStatus.uCharCount + 4]));
|
||||
|
||||
stReadStatus.uCharCount += 6; // read two bytes, plus a space;
|
||||
stReadStatus.uByteCount += 2;
|
||||
uReadCount -= 2;
|
||||
}
|
||||
if(ByteCount > BYTES_OF_PS_DATA_PER_LINE) {
|
||||
ByteCount -= BYTES_OF_PS_DATA_PER_LINE;
|
||||
}
|
||||
else {
|
||||
ByteCount = 0;
|
||||
}
|
||||
}
|
||||
else {
|
||||
//to be implemented
|
||||
}
|
||||
|
||||
stReadStatus.uLineCount++;
|
||||
|
||||
if(ByteCount == 0) {
|
||||
stReadStatus.uSection = 0;
|
||||
stReadStatus.uCharCount = 0;
|
||||
stReadStatus.uLineCount = 0;
|
||||
stReadStatus.uByteCount = 0;
|
||||
}
|
||||
else {
|
||||
stReadStatus.uCharCount = 0;
|
||||
}
|
||||
|
||||
if((stReadStatus.uSection == 0)&&(++TagCount == RAMPS_MAX_PS_TAGS_PER_FILE))
|
||||
{
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("\n Buffer over flow PS File too big!!!"));
|
||||
if(Buffer != NULL) {
|
||||
kfree(Buffer);
|
||||
}
|
||||
return A_ERROR;
|
||||
//Sleep (3000);
|
||||
//exit(1);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
{
|
||||
if(Buffer != NULL) {
|
||||
kfree(Buffer);
|
||||
}
|
||||
return A_ERROR;
|
||||
}
|
||||
break;
|
||||
}
|
||||
LineRead++;
|
||||
}
|
||||
Tag_Count = TagCount;
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Number of Tags %d\n", Tag_Count));
|
||||
}
|
||||
|
||||
|
||||
if (TagCount > RAMPS_MAX_PS_TAGS_PER_FILE)
|
||||
{
|
||||
|
||||
if(Buffer != NULL) {
|
||||
kfree(Buffer);
|
||||
}
|
||||
return A_ERROR;
|
||||
}
|
||||
|
||||
if(Buffer != NULL) {
|
||||
kfree(Buffer);
|
||||
}
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
/********************/
|
||||
|
||||
|
||||
int GetNextTwoChar(u8 *srcbuffer,u32 len, u32 *pos, char *buffer)
|
||||
{
|
||||
unsigned char ch;
|
||||
|
||||
ch = AthReadChar(srcbuffer,len,pos);
|
||||
if(ch != '\0' && isxdigit(ch)) {
|
||||
buffer[0] = ch;
|
||||
} else
|
||||
{
|
||||
return A_ERROR;
|
||||
}
|
||||
ch = AthReadChar(srcbuffer,len,pos);
|
||||
if(ch != '\0' && isxdigit(ch)) {
|
||||
buffer[1] = ch;
|
||||
} else
|
||||
{
|
||||
return A_ERROR;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int AthDoParsePatch(u8 *patchbuffer, u32 patchlen)
|
||||
{
|
||||
|
||||
char Byte[3];
|
||||
char Line[MAX_BYTE_LENGTH + 1];
|
||||
int ByteCount,ByteCount_Org;
|
||||
int count;
|
||||
int i,j,k;
|
||||
int data;
|
||||
u32 filepos;
|
||||
Byte[2] = '\0';
|
||||
j = 0;
|
||||
filepos = 0;
|
||||
Patch_Count = 0;
|
||||
|
||||
while(NULL != AthGetLine(Line,MAX_BYTE_LENGTH,patchbuffer,patchlen,&filepos)) {
|
||||
if(strlen(Line) <= 1 || !isxdigit(Line[0])) {
|
||||
continue;
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
ByteCount = A_STRTOL(Line, NULL, 16);
|
||||
ByteCount_Org = ByteCount;
|
||||
|
||||
while(ByteCount > MAX_BYTE_LENGTH){
|
||||
|
||||
/* Handle case when the number of patch buffer is more than the 20K */
|
||||
if(MAX_NUM_PATCH_ENTRY == Patch_Count) {
|
||||
for(i = 0; i < Patch_Count; i++) {
|
||||
kfree(RamPatch[i].Data);
|
||||
}
|
||||
return A_ERROR;
|
||||
}
|
||||
RamPatch[Patch_Count].Len= MAX_BYTE_LENGTH;
|
||||
RamPatch[Patch_Count].Data = (u8 *)A_MALLOC(MAX_BYTE_LENGTH);
|
||||
Patch_Count ++;
|
||||
|
||||
|
||||
ByteCount= ByteCount - MAX_BYTE_LENGTH;
|
||||
}
|
||||
|
||||
RamPatch[Patch_Count].Len= (ByteCount & 0xFF);
|
||||
if(ByteCount != 0) {
|
||||
RamPatch[Patch_Count].Data = (u8 *)A_MALLOC(ByteCount);
|
||||
Patch_Count ++;
|
||||
}
|
||||
count = 0;
|
||||
while(ByteCount_Org > MAX_BYTE_LENGTH){
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Index [%d]\n",j));
|
||||
for (i = 0,k=0; i < MAX_BYTE_LENGTH*2; i += 2,k++,count +=2) {
|
||||
if(GetNextTwoChar(patchbuffer,patchlen,&filepos,Byte) == A_ERROR) {
|
||||
return A_ERROR;
|
||||
}
|
||||
data = A_STRTOUL(&Byte[0], NULL, 16);
|
||||
RamPatch[j].Data[k] = (data & 0xFF);
|
||||
|
||||
|
||||
}
|
||||
j++;
|
||||
ByteCount_Org = ByteCount_Org - MAX_BYTE_LENGTH;
|
||||
}
|
||||
if(j == 0){
|
||||
j++;
|
||||
}
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Index [%d]\n",j));
|
||||
for (k=0; k < ByteCount_Org; i += 2,k++,count+=2) {
|
||||
if(GetNextTwoChar(patchbuffer,patchlen,&filepos,Byte) == A_ERROR) {
|
||||
return A_ERROR;
|
||||
}
|
||||
data = A_STRTOUL(Byte, NULL, 16);
|
||||
RamPatch[j].Data[k] = (data & 0xFF);
|
||||
|
||||
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/********************/
|
||||
int AthDoParsePS(u8 *srcbuffer, u32 srclen)
|
||||
{
|
||||
int status;
|
||||
int i;
|
||||
bool BDADDR_Present = false;
|
||||
|
||||
Tag_Count = 0;
|
||||
|
||||
Total_tag_lenght = 0;
|
||||
BDADDR = false;
|
||||
|
||||
|
||||
status = A_ERROR;
|
||||
|
||||
if(NULL != srcbuffer && srclen != 0)
|
||||
{
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("File Open Operation Successful\n"));
|
||||
|
||||
status = AthParseFilesUnified(srcbuffer,srclen,MB_FILEFORMAT_PATCH);
|
||||
}
|
||||
|
||||
|
||||
|
||||
if(Tag_Count == 0){
|
||||
Total_tag_lenght = 10;
|
||||
|
||||
}
|
||||
else{
|
||||
for(i=0; i<Tag_Count; i++){
|
||||
if(PsTagEntry[i].TagId == 1){
|
||||
BDADDR_Present = true;
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR is present in Patch File \r\n"));
|
||||
|
||||
}
|
||||
if(PsTagEntry[i].TagLen % 2 == 1){
|
||||
Total_tag_lenght = Total_tag_lenght + PsTagEntry[i].TagLen + 1;
|
||||
}
|
||||
else{
|
||||
Total_tag_lenght = Total_tag_lenght + PsTagEntry[i].TagLen;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
if(Tag_Count > 0 && !BDADDR_Present){
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR is not present adding 10 extra bytes \r\n"));
|
||||
Total_tag_lenght=Total_tag_lenght + 10;
|
||||
}
|
||||
Total_tag_lenght = Total_tag_lenght+ 10 + (Tag_Count*4);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** Total Length %d\n",Total_tag_lenght));
|
||||
|
||||
|
||||
return status;
|
||||
}
|
||||
char *AthGetLine(char *buffer, int maxlen, u8 *srcbuffer,u32 len,u32 *pos)
|
||||
{
|
||||
|
||||
int count;
|
||||
static short flag;
|
||||
char CharRead;
|
||||
count = 0;
|
||||
flag = A_ERROR;
|
||||
|
||||
do
|
||||
{
|
||||
CharRead = AthReadChar(srcbuffer,len,pos);
|
||||
if( CharRead == '\0' ) {
|
||||
buffer[count+1] = '\0';
|
||||
if(count == 0) {
|
||||
return NULL;
|
||||
}
|
||||
else {
|
||||
return buffer;
|
||||
}
|
||||
}
|
||||
|
||||
if(CharRead == 13) {
|
||||
} else if(CharRead == 10) {
|
||||
buffer[count] ='\0';
|
||||
flag = A_ERROR;
|
||||
return buffer;
|
||||
}else {
|
||||
buffer[count++] = CharRead;
|
||||
}
|
||||
|
||||
}
|
||||
while(count < maxlen-1 && CharRead != '\0');
|
||||
buffer[count] = '\0';
|
||||
|
||||
return buffer;
|
||||
}
|
||||
|
||||
static void LoadHeader(u8 *HCI_PS_Command,u8 opcode,int length,int index){
|
||||
|
||||
HCI_PS_Command[0]= 0x0B;
|
||||
HCI_PS_Command[1]= 0xFC;
|
||||
HCI_PS_Command[2]= length + 4;
|
||||
HCI_PS_Command[3]= opcode;
|
||||
HCI_PS_Command[4]= (index & 0xFF);
|
||||
HCI_PS_Command[5]= ((index>>8) & 0xFF);
|
||||
HCI_PS_Command[6]= length;
|
||||
}
|
||||
|
||||
/////////////////////////
|
||||
//
|
||||
int AthCreateCommandList(struct ps_cmd_packet **HciPacketList, u32 *numPackets)
|
||||
{
|
||||
|
||||
u8 count;
|
||||
u32 NumcmdEntry = 0;
|
||||
|
||||
u32 Crc = 0;
|
||||
*numPackets = 0;
|
||||
|
||||
|
||||
if(Patch_Count > 0)
|
||||
Crc |= RAM_PATCH_REGION;
|
||||
if(Tag_Count > 0)
|
||||
Crc |= RAM_PS_REGION;
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("PS Thread Started CRC %x Patch Count %d Tag Count %d \n",Crc,Patch_Count,Tag_Count));
|
||||
|
||||
if(Patch_Count || Tag_Count ){
|
||||
NumcmdEntry+=(2 + Patch_Count + Tag_Count); /* CRC Packet + PS Reset Packet + Patch List + PS List*/
|
||||
if(Patch_Count > 0) {
|
||||
NumcmdEntry++; /* Patch Enable Command */
|
||||
}
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Num Cmd Entries %d Size %d \r\n",NumcmdEntry,(u32)sizeof(struct ps_cmd_packet) * NumcmdEntry));
|
||||
(*HciPacketList) = A_MALLOC(sizeof(struct ps_cmd_packet) * NumcmdEntry);
|
||||
if(NULL == *HciPacketList) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("memory allocation failed \r\n"));
|
||||
}
|
||||
AthPSCreateHCICommand(PS_VERIFY_CRC,Crc,*HciPacketList,numPackets);
|
||||
if(Patch_Count > 0){
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** Write Patch**** \r\n"));
|
||||
AthPSCreateHCICommand(WRITE_PATCH,Patch_Count,*HciPacketList,numPackets);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** Enable Patch**** \r\n"));
|
||||
AthPSCreateHCICommand(ENABLE_PATCH,0,*HciPacketList,numPackets);
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** PS Reset**** %d[0x%x] \r\n",PS_RAM_SIZE,PS_RAM_SIZE));
|
||||
AthPSCreateHCICommand(PS_RESET,PS_RAM_SIZE,*HciPacketList,numPackets);
|
||||
if(Tag_Count > 0){
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** PS Write**** \r\n"));
|
||||
AthPSCreateHCICommand(PS_WRITE,Tag_Count,*HciPacketList,numPackets);
|
||||
}
|
||||
}
|
||||
if(!BDADDR){
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR not present \r\n"));
|
||||
|
||||
}
|
||||
for(count = 0; count < Patch_Count; count++) {
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing Patch Buffer %d \r\n",count));
|
||||
kfree(RamPatch[count].Data);
|
||||
}
|
||||
|
||||
for(count = 0; count < Tag_Count; count++) {
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing PS Buffer %d \r\n",count));
|
||||
kfree(PsTagEntry[count].TagData);
|
||||
}
|
||||
|
||||
/*
|
||||
* SDIO Transport uses synchronous mode of data transfer
|
||||
* So, AthPSOperations() call returns only after receiving the
|
||||
* command complete event.
|
||||
*/
|
||||
return *numPackets;
|
||||
}
|
||||
|
||||
|
||||
////////////////////////
|
||||
|
||||
/////////////
|
||||
static int AthPSCreateHCICommand(u8 Opcode, u32 Param1,struct ps_cmd_packet *PSPatchPacket,u32 *index)
|
||||
{
|
||||
u8 *HCI_PS_Command;
|
||||
u32 Length;
|
||||
int i,j;
|
||||
|
||||
switch(Opcode)
|
||||
{
|
||||
case WRITE_PATCH:
|
||||
|
||||
|
||||
for(i=0;i< Param1;i++){
|
||||
|
||||
HCI_PS_Command = (u8 *) A_MALLOC(RamPatch[i].Len+HCI_COMMAND_HEADER);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Allocated Buffer Size %d\n",RamPatch[i].Len+HCI_COMMAND_HEADER));
|
||||
if(HCI_PS_Command == NULL){
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
|
||||
return A_ERROR;
|
||||
}
|
||||
memset (HCI_PS_Command, 0, RamPatch[i].Len+HCI_COMMAND_HEADER);
|
||||
LoadHeader(HCI_PS_Command,Opcode,RamPatch[i].Len,i);
|
||||
for(j=0;j<RamPatch[i].Len;j++){
|
||||
HCI_PS_Command[HCI_COMMAND_HEADER+j]=RamPatch[i].Data[j];
|
||||
}
|
||||
PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
|
||||
PSPatchPacket[*index].packetLen = RamPatch[i].Len+HCI_COMMAND_HEADER;
|
||||
(*index)++;
|
||||
|
||||
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case ENABLE_PATCH:
|
||||
|
||||
|
||||
Length = 0;
|
||||
i= 0;
|
||||
HCI_PS_Command = (u8 *) A_MALLOC(Length+HCI_COMMAND_HEADER);
|
||||
if(HCI_PS_Command == NULL){
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
|
||||
return A_ERROR;
|
||||
}
|
||||
|
||||
memset (HCI_PS_Command, 0, Length+HCI_COMMAND_HEADER);
|
||||
LoadHeader(HCI_PS_Command,Opcode,Length,i);
|
||||
PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
|
||||
PSPatchPacket[*index].packetLen = Length+HCI_COMMAND_HEADER;
|
||||
(*index)++;
|
||||
|
||||
break;
|
||||
|
||||
case PS_RESET:
|
||||
Length = 0x06;
|
||||
i=0;
|
||||
HCI_PS_Command = (u8 *) A_MALLOC(Length+HCI_COMMAND_HEADER);
|
||||
if(HCI_PS_Command == NULL){
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
|
||||
return A_ERROR;
|
||||
}
|
||||
memset (HCI_PS_Command, 0, Length+HCI_COMMAND_HEADER);
|
||||
LoadHeader(HCI_PS_Command,Opcode,Length,i);
|
||||
HCI_PS_Command[7]= 0x00;
|
||||
HCI_PS_Command[Length+HCI_COMMAND_HEADER -2]= (Param1 & 0xFF);
|
||||
HCI_PS_Command[Length+HCI_COMMAND_HEADER -1]= ((Param1 >> 8) & 0xFF);
|
||||
PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
|
||||
PSPatchPacket[*index].packetLen = Length+HCI_COMMAND_HEADER;
|
||||
(*index)++;
|
||||
|
||||
break;
|
||||
|
||||
case PS_WRITE:
|
||||
for(i=0;i< Param1;i++){
|
||||
if(PsTagEntry[i].TagId ==1)
|
||||
BDADDR = true;
|
||||
|
||||
HCI_PS_Command = (u8 *) A_MALLOC(PsTagEntry[i].TagLen+HCI_COMMAND_HEADER);
|
||||
if(HCI_PS_Command == NULL){
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
|
||||
return A_ERROR;
|
||||
}
|
||||
|
||||
memset (HCI_PS_Command, 0, PsTagEntry[i].TagLen+HCI_COMMAND_HEADER);
|
||||
LoadHeader(HCI_PS_Command,Opcode,PsTagEntry[i].TagLen,PsTagEntry[i].TagId);
|
||||
|
||||
for(j=0;j<PsTagEntry[i].TagLen;j++){
|
||||
HCI_PS_Command[HCI_COMMAND_HEADER+j]=PsTagEntry[i].TagData[j];
|
||||
}
|
||||
|
||||
PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
|
||||
PSPatchPacket[*index].packetLen = PsTagEntry[i].TagLen+HCI_COMMAND_HEADER;
|
||||
(*index)++;
|
||||
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
|
||||
case PS_VERIFY_CRC:
|
||||
Length = 0x0;
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("VALUE of CRC:%d At index %d\r\n",Param1,*index));
|
||||
|
||||
HCI_PS_Command = (u8 *) A_MALLOC(Length+HCI_COMMAND_HEADER);
|
||||
if(HCI_PS_Command == NULL){
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
|
||||
return A_ERROR;
|
||||
}
|
||||
memset (HCI_PS_Command, 0, Length+HCI_COMMAND_HEADER);
|
||||
LoadHeader(HCI_PS_Command,Opcode,Length,Param1);
|
||||
|
||||
PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
|
||||
PSPatchPacket[*index].packetLen = Length+HCI_COMMAND_HEADER;
|
||||
(*index)++;
|
||||
|
||||
break;
|
||||
|
||||
case CHANGE_BDADDR:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
int AthFreeCommandList(struct ps_cmd_packet **HciPacketList, u32 numPackets)
|
||||
{
|
||||
int i;
|
||||
if(*HciPacketList == NULL) {
|
||||
return A_ERROR;
|
||||
}
|
||||
for(i = 0; i < numPackets;i++) {
|
||||
kfree((*HciPacketList)[i].Hcipacket);
|
||||
}
|
||||
kfree(*HciPacketList);
|
||||
return 0;
|
||||
}
|
|
@ -1,113 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// This file is the include file for Atheros PS and patch parser.
|
||||
// It implements APIs to parse data buffer with patch and PS information and convert it to HCI commands.
|
||||
//
|
||||
|
||||
#ifndef __AR3KPSPARSER_H
|
||||
#define __AR3KPSPARSER_H
|
||||
|
||||
|
||||
|
||||
|
||||
#include <linux/fs.h>
|
||||
#include <linux/slab.h>
|
||||
#include "athdefs.h"
|
||||
#ifdef HCI_TRANSPORT_SDIO
|
||||
#include "a_config.h"
|
||||
#include "a_osapi.h"
|
||||
#define ATH_MODULE_NAME misc
|
||||
#include "a_debug.h"
|
||||
#include "common_drv.h"
|
||||
#include "hci_transport_api.h"
|
||||
#include "ar3kconfig.h"
|
||||
#else
|
||||
#ifndef A_PRINTF
|
||||
#define A_PRINTF(args...) printk(KERN_ALERT args)
|
||||
#endif /* A_PRINTF */
|
||||
#include "debug_linux.h"
|
||||
|
||||
/* Helper data type declaration */
|
||||
|
||||
#define ATH_DEBUG_ERR (1 << 0)
|
||||
#define ATH_DEBUG_WARN (1 << 1)
|
||||
#define ATH_DEBUG_INFO (1 << 2)
|
||||
|
||||
|
||||
|
||||
#define false 0
|
||||
#define true 1
|
||||
|
||||
#ifndef A_MALLOC
|
||||
#define A_MALLOC(size) kmalloc((size),GFP_KERNEL)
|
||||
#endif /* A_MALLOC */
|
||||
#endif /* HCI_TRANSPORT_UART */
|
||||
|
||||
/* String manipulation APIs */
|
||||
#ifndef A_STRTOUL
|
||||
#define A_STRTOUL simple_strtoul
|
||||
#endif /* A_STRTOL */
|
||||
|
||||
#ifndef A_STRTOL
|
||||
#define A_STRTOL simple_strtol
|
||||
#endif /* A_STRTOL */
|
||||
|
||||
|
||||
/* The maximum number of bytes possible in a patch entry */
|
||||
#define MAX_PATCH_SIZE 20000
|
||||
|
||||
/* Maximum HCI packets that will be formed from the Patch file */
|
||||
#define MAX_NUM_PATCH_ENTRY (MAX_PATCH_SIZE/MAX_BYTE_LENGTH) + 1
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
struct ps_cmd_packet
|
||||
{
|
||||
u8 *Hcipacket;
|
||||
int packetLen;
|
||||
};
|
||||
|
||||
/* Parses a Patch information buffer and store it in global structure */
|
||||
int AthDoParsePatch(u8 *, u32 );
|
||||
|
||||
/* parses a PS information buffer and stores it in a global structure */
|
||||
int AthDoParsePS(u8 *, u32 );
|
||||
|
||||
/*
|
||||
* Uses the output of Both AthDoParsePS and AthDoParsePatch APIs to form HCI command array with
|
||||
* all the PS and patch commands.
|
||||
* The list will have the below mentioned commands in order.
|
||||
* CRC command packet
|
||||
* Download patch command(s)
|
||||
* Enable patch Command
|
||||
* PS Reset Command
|
||||
* PS Tag Command(s)
|
||||
*
|
||||
*/
|
||||
int AthCreateCommandList(struct ps_cmd_packet **, u32 *);
|
||||
|
||||
/* Cleanup the dynamically allicated HCI command list */
|
||||
int AthFreeCommandList(struct ps_cmd_packet **HciPacketList, u32 numPackets);
|
||||
#endif /* __AR3KPSPARSER_H */
|
|
@ -1,910 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="common_drv.c" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#include "a_config.h"
|
||||
#include "athdefs.h"
|
||||
|
||||
#include "hw/mbox_host_reg.h"
|
||||
#include "gpio_reg.h"
|
||||
#include "hw/rtc_reg.h"
|
||||
#include "hw/mbox_reg.h"
|
||||
#include "hw/apb_map.h"
|
||||
|
||||
#include "a_osapi.h"
|
||||
#include "targaddrs.h"
|
||||
#include "hif.h"
|
||||
#include "htc_api.h"
|
||||
#include "wmi.h"
|
||||
#include "bmi.h"
|
||||
#include "bmi_msg.h"
|
||||
#include "common_drv.h"
|
||||
#define ATH_MODULE_NAME misc
|
||||
#include "a_debug.h"
|
||||
#include "ar6000_diag.h"
|
||||
|
||||
static ATH_DEBUG_MODULE_DBG_INFO *g_pModuleInfoHead = NULL;
|
||||
static A_MUTEX_T g_ModuleListLock;
|
||||
static bool g_ModuleDebugInit = false;
|
||||
|
||||
#ifdef ATH_DEBUG_MODULE
|
||||
|
||||
ATH_DEBUG_INSTANTIATE_MODULE_VAR(misc,
|
||||
"misc",
|
||||
"Common and misc APIs",
|
||||
ATH_DEBUG_MASK_DEFAULTS,
|
||||
0,
|
||||
NULL);
|
||||
|
||||
#endif
|
||||
|
||||
#define HOST_INTEREST_ITEM_ADDRESS(target, item) \
|
||||
((((target) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
|
||||
(((target) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0)))
|
||||
|
||||
|
||||
#define AR6001_LOCAL_COUNT_ADDRESS 0x0c014080
|
||||
#define AR6002_LOCAL_COUNT_ADDRESS 0x00018080
|
||||
#define AR6003_LOCAL_COUNT_ADDRESS 0x00018080
|
||||
#define CPU_DBG_SEL_ADDRESS 0x00000483
|
||||
#define CPU_DBG_ADDRESS 0x00000484
|
||||
|
||||
static u8 custDataAR6002[AR6002_CUST_DATA_SIZE];
|
||||
static u8 custDataAR6003[AR6003_CUST_DATA_SIZE];
|
||||
|
||||
/* Compile the 4BYTE version of the window register setup routine,
|
||||
* This mitigates host interconnect issues with non-4byte aligned bus requests, some
|
||||
* interconnects use bus adapters that impose strict limitations.
|
||||
* Since diag window access is not intended for performance critical operations, the 4byte mode should
|
||||
* be satisfactory even though it generates 4X the bus activity. */
|
||||
|
||||
#ifdef USE_4BYTE_REGISTER_ACCESS
|
||||
|
||||
/* set the window address register (using 4-byte register access ). */
|
||||
int ar6000_SetAddressWindowRegister(struct hif_device *hifDevice, u32 RegisterAddr, u32 Address)
|
||||
{
|
||||
int status;
|
||||
u8 addrValue[4];
|
||||
s32 i;
|
||||
|
||||
/* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
|
||||
* last to initiate the access cycle */
|
||||
|
||||
for (i = 1; i <= 3; i++) {
|
||||
/* fill the buffer with the address byte value we want to hit 4 times*/
|
||||
addrValue[0] = ((u8 *)&Address)[i];
|
||||
addrValue[1] = addrValue[0];
|
||||
addrValue[2] = addrValue[0];
|
||||
addrValue[3] = addrValue[0];
|
||||
|
||||
/* hit each byte of the register address with a 4-byte write operation to the same address,
|
||||
* this is a harmless operation */
|
||||
status = HIFReadWrite(hifDevice,
|
||||
RegisterAddr+i,
|
||||
addrValue,
|
||||
4,
|
||||
HIF_WR_SYNC_BYTE_FIX,
|
||||
NULL);
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
|
||||
Address, RegisterAddr));
|
||||
return status;
|
||||
}
|
||||
|
||||
/* write the address register again, this time write the whole 4-byte value.
|
||||
* The effect here is that the LSB write causes the cycle to start, the extra
|
||||
* 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */
|
||||
status = HIFReadWrite(hifDevice,
|
||||
RegisterAddr,
|
||||
(u8 *)(&Address),
|
||||
4,
|
||||
HIF_WR_SYNC_BYTE_INC,
|
||||
NULL);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
|
||||
Address, RegisterAddr));
|
||||
return status;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
#else
|
||||
|
||||
/* set the window address register */
|
||||
int ar6000_SetAddressWindowRegister(struct hif_device *hifDevice, u32 RegisterAddr, u32 Address)
|
||||
{
|
||||
int status;
|
||||
|
||||
/* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
|
||||
* last to initiate the access cycle */
|
||||
status = HIFReadWrite(hifDevice,
|
||||
RegisterAddr+1, /* write upper 3 bytes */
|
||||
((u8 *)(&Address))+1,
|
||||
sizeof(u32)-1,
|
||||
HIF_WR_SYNC_BYTE_INC,
|
||||
NULL);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
|
||||
RegisterAddr, Address));
|
||||
return status;
|
||||
}
|
||||
|
||||
/* write the LSB of the register, this initiates the operation */
|
||||
status = HIFReadWrite(hifDevice,
|
||||
RegisterAddr,
|
||||
(u8 *)(&Address),
|
||||
sizeof(u8),
|
||||
HIF_WR_SYNC_BYTE_INC,
|
||||
NULL);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
|
||||
RegisterAddr, Address));
|
||||
return status;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Read from the AR6000 through its diagnostic window.
|
||||
* No cooperation from the Target is required for this.
|
||||
*/
|
||||
int
|
||||
ar6000_ReadRegDiag(struct hif_device *hifDevice, u32 *address, u32 *data)
|
||||
{
|
||||
int status;
|
||||
|
||||
/* set window register to start read cycle */
|
||||
status = ar6000_SetAddressWindowRegister(hifDevice,
|
||||
WINDOW_READ_ADDR_ADDRESS,
|
||||
*address);
|
||||
|
||||
if (status) {
|
||||
return status;
|
||||
}
|
||||
|
||||
/* read the data */
|
||||
status = HIFReadWrite(hifDevice,
|
||||
WINDOW_DATA_ADDRESS,
|
||||
(u8 *)data,
|
||||
sizeof(u32),
|
||||
HIF_RD_SYNC_BYTE_INC,
|
||||
NULL);
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n"));
|
||||
return status;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Write to the AR6000 through its diagnostic window.
|
||||
* No cooperation from the Target is required for this.
|
||||
*/
|
||||
int
|
||||
ar6000_WriteRegDiag(struct hif_device *hifDevice, u32 *address, u32 *data)
|
||||
{
|
||||
int status;
|
||||
|
||||
/* set write data */
|
||||
status = HIFReadWrite(hifDevice,
|
||||
WINDOW_DATA_ADDRESS,
|
||||
(u8 *)data,
|
||||
sizeof(u32),
|
||||
HIF_WR_SYNC_BYTE_INC,
|
||||
NULL);
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data));
|
||||
return status;
|
||||
}
|
||||
|
||||
/* set window register, which starts the write cycle */
|
||||
return ar6000_SetAddressWindowRegister(hifDevice,
|
||||
WINDOW_WRITE_ADDR_ADDRESS,
|
||||
*address);
|
||||
}
|
||||
|
||||
int
|
||||
ar6000_ReadDataDiag(struct hif_device *hifDevice, u32 address,
|
||||
u8 *data, u32 length)
|
||||
{
|
||||
u32 count;
|
||||
int status = 0;
|
||||
|
||||
for (count = 0; count < length; count += 4, address += 4) {
|
||||
if ((status = ar6000_ReadRegDiag(hifDevice, &address,
|
||||
(u32 *)&data[count])) != 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int
|
||||
ar6000_WriteDataDiag(struct hif_device *hifDevice, u32 address,
|
||||
u8 *data, u32 length)
|
||||
{
|
||||
u32 count;
|
||||
int status = 0;
|
||||
|
||||
for (count = 0; count < length; count += 4, address += 4) {
|
||||
if ((status = ar6000_WriteRegDiag(hifDevice, &address,
|
||||
(u32 *)&data[count])) != 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int
|
||||
ar6k_ReadTargetRegister(struct hif_device *hifDevice, int regsel, u32 *regval)
|
||||
{
|
||||
int status;
|
||||
u8 vals[4];
|
||||
u8 register_selection[4];
|
||||
|
||||
register_selection[0] = register_selection[1] = register_selection[2] = register_selection[3] = (regsel & 0xff);
|
||||
status = HIFReadWrite(hifDevice,
|
||||
CPU_DBG_SEL_ADDRESS,
|
||||
register_selection,
|
||||
4,
|
||||
HIF_WR_SYNC_BYTE_FIX,
|
||||
NULL);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write CPU_DBG_SEL (%d)\n", regsel));
|
||||
return status;
|
||||
}
|
||||
|
||||
status = HIFReadWrite(hifDevice,
|
||||
CPU_DBG_ADDRESS,
|
||||
(u8 *)vals,
|
||||
sizeof(vals),
|
||||
HIF_RD_SYNC_BYTE_INC,
|
||||
NULL);
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from CPU_DBG_ADDRESS\n"));
|
||||
return status;
|
||||
}
|
||||
|
||||
*regval = vals[0]<<0 | vals[1]<<8 | vals[2]<<16 | vals[3]<<24;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
void
|
||||
ar6k_FetchTargetRegs(struct hif_device *hifDevice, u32 *targregs)
|
||||
{
|
||||
int i;
|
||||
u32 val;
|
||||
|
||||
for (i=0; i<AR6003_FETCH_TARG_REGS_COUNT; i++) {
|
||||
val=0xffffffff;
|
||||
(void)ar6k_ReadTargetRegister(hifDevice, i, &val);
|
||||
targregs[i] = val;
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
static int
|
||||
_do_write_diag(struct hif_device *hifDevice, u32 addr, u32 value)
|
||||
{
|
||||
int status;
|
||||
|
||||
status = ar6000_WriteRegDiag(hifDevice, &addr, &value);
|
||||
if (status)
|
||||
{
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n"));
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Delay up to wait_msecs millisecs to allow Target to enter BMI phase,
|
||||
* which is a good sign that it's alive and well. This is used after
|
||||
* explicitly forcing the Target to reset.
|
||||
*
|
||||
* The wait_msecs time should be sufficiently long to cover any reasonable
|
||||
* boot-time delay. For instance, AR6001 firmware allow one second for a
|
||||
* low frequency crystal to settle before it calibrates the refclk frequency.
|
||||
*
|
||||
* TBD: Might want to add special handling for AR6K_OPTION_BMI_DISABLE.
|
||||
*/
|
||||
#if 0
|
||||
static int
|
||||
_delay_until_target_alive(struct hif_device *hifDevice, s32 wait_msecs, u32 TargetType)
|
||||
{
|
||||
s32 actual_wait;
|
||||
s32 i;
|
||||
u32 address;
|
||||
|
||||
actual_wait = 0;
|
||||
|
||||
/* Hardcode the address of LOCAL_COUNT_ADDRESS based on the target type */
|
||||
if (TargetType == TARGET_TYPE_AR6002) {
|
||||
address = AR6002_LOCAL_COUNT_ADDRESS;
|
||||
} else if (TargetType == TARGET_TYPE_AR6003) {
|
||||
address = AR6003_LOCAL_COUNT_ADDRESS;
|
||||
} else {
|
||||
A_ASSERT(0);
|
||||
}
|
||||
address += 0x10;
|
||||
for (i=0; actual_wait < wait_msecs; i++) {
|
||||
u32 data;
|
||||
|
||||
A_MDELAY(100);
|
||||
actual_wait += 100;
|
||||
|
||||
data = 0;
|
||||
if (ar6000_ReadRegDiag(hifDevice, &address, &data) != 0) {
|
||||
return A_ERROR;
|
||||
}
|
||||
|
||||
if (data != 0) {
|
||||
/* No need to wait longer -- we have a BMI credit */
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return A_ERROR; /* timed out */
|
||||
}
|
||||
#endif
|
||||
|
||||
#define AR6001_RESET_CONTROL_ADDRESS 0x0C000000
|
||||
#define AR6002_RESET_CONTROL_ADDRESS 0x00004000
|
||||
#define AR6003_RESET_CONTROL_ADDRESS 0x00004000
|
||||
/* reset device */
|
||||
int ar6000_reset_device(struct hif_device *hifDevice, u32 TargetType, bool waitForCompletion, bool coldReset)
|
||||
{
|
||||
int status = 0;
|
||||
u32 address;
|
||||
u32 data;
|
||||
|
||||
do {
|
||||
// Workaround BEGIN
|
||||
// address = RESET_CONTROL_ADDRESS;
|
||||
|
||||
if (coldReset) {
|
||||
data = RESET_CONTROL_COLD_RST_MASK;
|
||||
}
|
||||
else {
|
||||
data = RESET_CONTROL_MBOX_RST_MASK;
|
||||
}
|
||||
|
||||
/* Hardcode the address of RESET_CONTROL_ADDRESS based on the target type */
|
||||
if (TargetType == TARGET_TYPE_AR6002) {
|
||||
address = AR6002_RESET_CONTROL_ADDRESS;
|
||||
} else if (TargetType == TARGET_TYPE_AR6003) {
|
||||
address = AR6003_RESET_CONTROL_ADDRESS;
|
||||
} else {
|
||||
A_ASSERT(0);
|
||||
}
|
||||
|
||||
|
||||
status = ar6000_WriteRegDiag(hifDevice, &address, &data);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (!waitForCompletion) {
|
||||
break;
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* Up to 2 second delay to allow things to settle down */
|
||||
(void)_delay_until_target_alive(hifDevice, 2000, TargetType);
|
||||
|
||||
/*
|
||||
* Read back the RESET CAUSE register to ensure that the cold reset
|
||||
* went through.
|
||||
*/
|
||||
|
||||
// address = RESET_CAUSE_ADDRESS;
|
||||
/* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type */
|
||||
if (TargetType == TARGET_TYPE_AR6002) {
|
||||
address = 0x000040C0;
|
||||
} else if (TargetType == TARGET_TYPE_AR6003) {
|
||||
address = 0x000040C0;
|
||||
} else {
|
||||
A_ASSERT(0);
|
||||
}
|
||||
|
||||
data = 0;
|
||||
status = ar6000_ReadRegDiag(hifDevice, &address, &data);
|
||||
|
||||
if (status) {
|
||||
break;
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Reset Cause readback: 0x%X \n",data));
|
||||
data &= RESET_CAUSE_LAST_MASK;
|
||||
if (data != 2) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Unable to cold reset the target \n"));
|
||||
}
|
||||
#endif
|
||||
// Workaroud END
|
||||
|
||||
} while (false);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Failed to reset target \n"));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This should be called in BMI phase after firmware is downloaded */
|
||||
void
|
||||
ar6000_copy_cust_data_from_target(struct hif_device *hifDevice, u32 TargetType)
|
||||
{
|
||||
u32 eepHeaderAddr;
|
||||
u8 AR6003CustDataShadow[AR6003_CUST_DATA_SIZE+4];
|
||||
s32 i;
|
||||
|
||||
if (BMIReadMemory(hifDevice,
|
||||
HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_board_data),
|
||||
(u8 *)&eepHeaderAddr,
|
||||
4)!= 0)
|
||||
{
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadMemory for reading board data address failed \n"));
|
||||
return;
|
||||
}
|
||||
|
||||
if (TargetType == TARGET_TYPE_AR6003) {
|
||||
eepHeaderAddr += 36; /* AR6003 customer data section offset is 37 */
|
||||
|
||||
for (i=0; i<AR6003_CUST_DATA_SIZE+4; i+=4){
|
||||
if (BMIReadSOCRegister(hifDevice, eepHeaderAddr, (u32 *)&AR6003CustDataShadow[i])!= 0) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
|
||||
return ;
|
||||
}
|
||||
eepHeaderAddr +=4;
|
||||
}
|
||||
|
||||
memcpy(custDataAR6003, AR6003CustDataShadow+1, AR6003_CUST_DATA_SIZE);
|
||||
}
|
||||
|
||||
if (TargetType == TARGET_TYPE_AR6002) {
|
||||
eepHeaderAddr += 64; /* AR6002 customer data sectioin offset is 64 */
|
||||
|
||||
for (i=0; i<AR6002_CUST_DATA_SIZE; i+=4){
|
||||
if (BMIReadSOCRegister(hifDevice, eepHeaderAddr, (u32 *)&custDataAR6002[i])!= 0) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
|
||||
return ;
|
||||
}
|
||||
eepHeaderAddr +=4;
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* This is the function to call when need to use the cust data */
|
||||
u8 *ar6000_get_cust_data_buffer(u32 TargetType)
|
||||
{
|
||||
if (TargetType == TARGET_TYPE_AR6003)
|
||||
return custDataAR6003;
|
||||
|
||||
if (TargetType == TARGET_TYPE_AR6002)
|
||||
return custDataAR6002;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#define REG_DUMP_COUNT_AR6001 38 /* WORDs, derived from AR600x_regdump.h */
|
||||
#define REG_DUMP_COUNT_AR6002 60
|
||||
#define REG_DUMP_COUNT_AR6003 60
|
||||
#define REGISTER_DUMP_LEN_MAX 60
|
||||
#if REG_DUMP_COUNT_AR6001 > REGISTER_DUMP_LEN_MAX
|
||||
#error "REG_DUMP_COUNT_AR6001 too large"
|
||||
#endif
|
||||
#if REG_DUMP_COUNT_AR6002 > REGISTER_DUMP_LEN_MAX
|
||||
#error "REG_DUMP_COUNT_AR6002 too large"
|
||||
#endif
|
||||
#if REG_DUMP_COUNT_AR6003 > REGISTER_DUMP_LEN_MAX
|
||||
#error "REG_DUMP_COUNT_AR6003 too large"
|
||||
#endif
|
||||
|
||||
|
||||
void ar6000_dump_target_assert_info(struct hif_device *hifDevice, u32 TargetType)
|
||||
{
|
||||
u32 address;
|
||||
u32 regDumpArea = 0;
|
||||
int status;
|
||||
u32 regDumpValues[REGISTER_DUMP_LEN_MAX];
|
||||
u32 regDumpCount = 0;
|
||||
u32 i;
|
||||
|
||||
do {
|
||||
|
||||
/* the reg dump pointer is copied to the host interest area */
|
||||
address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state);
|
||||
address = TARG_VTOP(TargetType, address);
|
||||
|
||||
if (TargetType == TARGET_TYPE_AR6002) {
|
||||
regDumpCount = REG_DUMP_COUNT_AR6002;
|
||||
} else if (TargetType == TARGET_TYPE_AR6003) {
|
||||
regDumpCount = REG_DUMP_COUNT_AR6003;
|
||||
} else {
|
||||
A_ASSERT(0);
|
||||
}
|
||||
|
||||
/* read RAM location through diagnostic window */
|
||||
status = ar6000_ReadRegDiag(hifDevice, &address, ®DumpArea);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get ptr to register dump area \n"));
|
||||
break;
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Location of register dump data: 0x%X \n",regDumpArea));
|
||||
|
||||
if (regDumpArea == 0) {
|
||||
/* no reg dump */
|
||||
break;
|
||||
}
|
||||
|
||||
regDumpArea = TARG_VTOP(TargetType, regDumpArea);
|
||||
|
||||
/* fetch register dump data */
|
||||
status = ar6000_ReadDataDiag(hifDevice,
|
||||
regDumpArea,
|
||||
(u8 *)®DumpValues[0],
|
||||
regDumpCount * (sizeof(u32)));
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get register dump \n"));
|
||||
break;
|
||||
}
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Register Dump: \n"));
|
||||
|
||||
for (i = 0; i < regDumpCount; i++) {
|
||||
//ATHR_DISPLAY_MSG (_T(" %d : 0x%8.8X \n"), i, regDumpValues[i]);
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" %d : 0x%8.8X \n",i, regDumpValues[i]));
|
||||
|
||||
#ifdef UNDER_CE
|
||||
/*
|
||||
* For Every logPrintf() Open the File so that in case of Crashes
|
||||
* We will have until the Last Message Flushed on to the File
|
||||
* So use logPrintf Sparingly..!!
|
||||
*/
|
||||
tgtassertPrintf (ATH_DEBUG_TRC," %d: 0x%8.8X \n",i, regDumpValues[i]);
|
||||
#endif
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
}
|
||||
|
||||
/* set HTC/Mbox operational parameters, this can only be called when the target is in the
|
||||
* BMI phase */
|
||||
int ar6000_set_htc_params(struct hif_device *hifDevice,
|
||||
u32 TargetType,
|
||||
u32 MboxIsrYieldValue,
|
||||
u8 HtcControlBuffers)
|
||||
{
|
||||
int status;
|
||||
u32 blocksizes[HTC_MAILBOX_NUM_MAX];
|
||||
|
||||
do {
|
||||
/* get the block sizes */
|
||||
status = HIFConfigureDevice(hifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
|
||||
blocksizes, sizeof(blocksizes));
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR,("Failed to get block size info from HIF layer...\n"));
|
||||
break;
|
||||
}
|
||||
/* note: we actually get the block size for mailbox 1, for SDIO the block
|
||||
* size on mailbox 0 is artificially set to 1 */
|
||||
/* must be a power of 2 */
|
||||
A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0);
|
||||
|
||||
if (HtcControlBuffers != 0) {
|
||||
/* set override for number of control buffers to use */
|
||||
blocksizes[1] |= ((u32)HtcControlBuffers) << 16;
|
||||
}
|
||||
|
||||
/* set the host interest area for the block size */
|
||||
status = BMIWriteMemory(hifDevice,
|
||||
HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz),
|
||||
(u8 *)&blocksizes[1],
|
||||
4);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for IO block size failed \n"));
|
||||
break;
|
||||
}
|
||||
|
||||
AR_DEBUG_PRINTF(ATH_LOG_INF,("Block Size Set: %d (target address:0x%X)\n",
|
||||
blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz)));
|
||||
|
||||
if (MboxIsrYieldValue != 0) {
|
||||
/* set the host interest area for the mbox ISR yield limit */
|
||||
status = BMIWriteMemory(hifDevice,
|
||||
HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_isr_yield_limit),
|
||||
(u8 *)&MboxIsrYieldValue,
|
||||
4);
|
||||
|
||||
if (status) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for yield limit failed \n"));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
} while (false);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
void DebugDumpBytes(u8 *buffer, u16 length, char *pDescription)
|
||||
{
|
||||
char stream[60];
|
||||
char byteOffsetStr[10];
|
||||
u32 i;
|
||||
u16 offset, count, byteOffset;
|
||||
|
||||
A_PRINTF("<---------Dumping %d Bytes : %s ------>\n", length, pDescription);
|
||||
|
||||
count = 0;
|
||||
offset = 0;
|
||||
byteOffset = 0;
|
||||
for(i = 0; i < length; i++) {
|
||||
A_SPRINTF(stream + offset, "%2.2X ", buffer[i]);
|
||||
count ++;
|
||||
offset += 3;
|
||||
|
||||
if(count == 16) {
|
||||
count = 0;
|
||||
offset = 0;
|
||||
A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset);
|
||||
A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
|
||||
A_MEMZERO(stream, 60);
|
||||
byteOffset += 16;
|
||||
}
|
||||
}
|
||||
|
||||
if(offset != 0) {
|
||||
A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset);
|
||||
A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
|
||||
}
|
||||
|
||||
A_PRINTF("<------------------------------------------------->\n");
|
||||
}
|
||||
|
||||
void a_dump_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo)
|
||||
{
|
||||
int i;
|
||||
struct ath_debug_mask_description *pDesc;
|
||||
|
||||
if (pInfo == NULL) {
|
||||
return;
|
||||
}
|
||||
|
||||
pDesc = pInfo->pMaskDescriptions;
|
||||
|
||||
A_PRINTF("========================================================\n\n");
|
||||
A_PRINTF("Module Debug Info => Name : %s \n", pInfo->ModuleName);
|
||||
A_PRINTF(" => Descr. : %s \n", pInfo->ModuleDescription);
|
||||
A_PRINTF("\n Current mask => 0x%8.8X \n", pInfo->CurrentMask);
|
||||
A_PRINTF("\n Avail. Debug Masks :\n\n");
|
||||
|
||||
for (i = 0; i < pInfo->MaxDescriptions; i++,pDesc++) {
|
||||
A_PRINTF(" => 0x%8.8X -- %s \n", pDesc->Mask, pDesc->Description);
|
||||
}
|
||||
|
||||
if (0 == i) {
|
||||
A_PRINTF(" => * none defined * \n");
|
||||
}
|
||||
|
||||
A_PRINTF("\n Standard Debug Masks :\n\n");
|
||||
/* print standard masks */
|
||||
A_PRINTF(" => 0x%8.8X -- Errors \n", ATH_DEBUG_ERR);
|
||||
A_PRINTF(" => 0x%8.8X -- Warnings \n", ATH_DEBUG_WARN);
|
||||
A_PRINTF(" => 0x%8.8X -- Informational \n", ATH_DEBUG_INFO);
|
||||
A_PRINTF(" => 0x%8.8X -- Tracing \n", ATH_DEBUG_TRC);
|
||||
A_PRINTF("\n========================================================\n");
|
||||
|
||||
}
|
||||
|
||||
|
||||
static ATH_DEBUG_MODULE_DBG_INFO *FindModule(char *module_name)
|
||||
{
|
||||
ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
|
||||
|
||||
if (!g_ModuleDebugInit) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
while (pInfo != NULL) {
|
||||
/* TODO: need to use something other than strlen */
|
||||
if (memcmp(pInfo->ModuleName,module_name,strlen(module_name)) == 0) {
|
||||
break;
|
||||
}
|
||||
pInfo = pInfo->pNext;
|
||||
}
|
||||
|
||||
return pInfo;
|
||||
}
|
||||
|
||||
|
||||
void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo)
|
||||
{
|
||||
if (!g_ModuleDebugInit) {
|
||||
return;
|
||||
}
|
||||
|
||||
A_MUTEX_LOCK(&g_ModuleListLock);
|
||||
|
||||
if (!(pInfo->Flags & ATH_DEBUG_INFO_FLAGS_REGISTERED)) {
|
||||
if (g_pModuleInfoHead == NULL) {
|
||||
g_pModuleInfoHead = pInfo;
|
||||
} else {
|
||||
pInfo->pNext = g_pModuleInfoHead;
|
||||
g_pModuleInfoHead = pInfo;
|
||||
}
|
||||
pInfo->Flags |= ATH_DEBUG_INFO_FLAGS_REGISTERED;
|
||||
}
|
||||
|
||||
A_MUTEX_UNLOCK(&g_ModuleListLock);
|
||||
}
|
||||
|
||||
void a_dump_module_debug_info_by_name(char *module_name)
|
||||
{
|
||||
ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
|
||||
|
||||
if (!g_ModuleDebugInit) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (memcmp(module_name,"all",3) == 0) {
|
||||
/* dump all */
|
||||
while (pInfo != NULL) {
|
||||
a_dump_module_debug_info(pInfo);
|
||||
pInfo = pInfo->pNext;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
pInfo = FindModule(module_name);
|
||||
|
||||
if (pInfo != NULL) {
|
||||
a_dump_module_debug_info(pInfo);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
int a_get_module_mask(char *module_name, u32 *pMask)
|
||||
{
|
||||
ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name);
|
||||
|
||||
if (NULL == pInfo) {
|
||||
return A_ERROR;
|
||||
}
|
||||
|
||||
*pMask = pInfo->CurrentMask;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int a_set_module_mask(char *module_name, u32 Mask)
|
||||
{
|
||||
ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name);
|
||||
|
||||
if (NULL == pInfo) {
|
||||
return A_ERROR;
|
||||
}
|
||||
|
||||
pInfo->CurrentMask = Mask;
|
||||
A_PRINTF("Module %s, new mask: 0x%8.8X \n",module_name,pInfo->CurrentMask);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void a_module_debug_support_init(void)
|
||||
{
|
||||
if (g_ModuleDebugInit) {
|
||||
return;
|
||||
}
|
||||
A_MUTEX_INIT(&g_ModuleListLock);
|
||||
g_pModuleInfoHead = NULL;
|
||||
g_ModuleDebugInit = true;
|
||||
A_REGISTER_MODULE_DEBUG_INFO(misc);
|
||||
}
|
||||
|
||||
void a_module_debug_support_cleanup(void)
|
||||
{
|
||||
ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
|
||||
ATH_DEBUG_MODULE_DBG_INFO *pCur;
|
||||
|
||||
if (!g_ModuleDebugInit) {
|
||||
return;
|
||||
}
|
||||
|
||||
g_ModuleDebugInit = false;
|
||||
|
||||
A_MUTEX_LOCK(&g_ModuleListLock);
|
||||
|
||||
while (pInfo != NULL) {
|
||||
pCur = pInfo;
|
||||
pInfo = pInfo->pNext;
|
||||
pCur->pNext = NULL;
|
||||
/* clear registered flag */
|
||||
pCur->Flags &= ~ATH_DEBUG_INFO_FLAGS_REGISTERED;
|
||||
}
|
||||
|
||||
A_MUTEX_UNLOCK(&g_ModuleListLock);
|
||||
|
||||
A_MUTEX_DELETE(&g_ModuleListLock);
|
||||
g_pModuleInfoHead = NULL;
|
||||
}
|
||||
|
||||
/* can only be called during bmi init stage */
|
||||
int ar6000_set_hci_bridge_flags(struct hif_device *hifDevice,
|
||||
u32 TargetType,
|
||||
u32 Flags)
|
||||
{
|
||||
int status = 0;
|
||||
|
||||
do {
|
||||
|
||||
if (TargetType != TARGET_TYPE_AR6003) {
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Target Type:%d, does not support HCI bridging! \n",
|
||||
TargetType));
|
||||
break;
|
||||
}
|
||||
|
||||
/* set hci bridge flags */
|
||||
status = BMIWriteMemory(hifDevice,
|
||||
HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_hci_bridge_flags),
|
||||
(u8 *)&Flags,
|
||||
4);
|
||||
|
||||
|
||||
} while (false);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
|
@ -1,417 +0,0 @@
|
|||
//------------------------------------------------------------------------------
|
||||
// <copyright file="credit_dist.c" company="Atheros">
|
||||
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Permission to use, copy, modify, and/or distribute this software for any
|
||||
// purpose with or without fee is hereby granted, provided that the above
|
||||
// copyright notice and this permission notice appear in all copies.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
//==============================================================================
|
||||
// Author(s): ="Atheros"
|
||||
//==============================================================================
|
||||
|
||||
#include "a_config.h"
|
||||
#include "athdefs.h"
|
||||
#include "a_osapi.h"
|
||||
#define ATH_MODULE_NAME misc
|
||||
#include "a_debug.h"
|
||||
#include "htc_api.h"
|
||||
#include "common_drv.h"
|
||||
|
||||
/********* CREDIT DISTRIBUTION FUNCTIONS ******************************************/
|
||||
|
||||
#define NO_VO_SERVICE 1 /* currently WMI only uses 3 data streams, so we leave VO service inactive */
|
||||
#define CONFIG_GIVE_LOW_PRIORITY_STREAMS_MIN_CREDITS 1
|
||||
|
||||
#ifdef NO_VO_SERVICE
|
||||
#define DATA_SVCS_USED 3
|
||||
#else
|
||||
#define DATA_SVCS_USED 4
|
||||
#endif
|
||||
|
||||
static void RedistributeCredits(struct common_credit_state_info *pCredInfo,
|
||||
struct htc_endpoint_credit_dist *pEPDistList);
|
||||
|
||||
static void SeekCredits(struct common_credit_state_info *pCredInfo,
|
||||
struct htc_endpoint_credit_dist *pEPDistList);
|
||||
|
||||
/* reduce an ep's credits back to a set limit */
|
||||
static INLINE void ReduceCredits(struct common_credit_state_info *pCredInfo,
|
||||
struct htc_endpoint_credit_dist *pEpDist,
|
||||
int Limit)
|
||||
{
|
||||
int credits;
|
||||
|
||||
/* set the new limit */
|
||||
pEpDist->TxCreditsAssigned = Limit;
|
||||
|
||||
if (pEpDist->TxCredits <= Limit) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* figure out how much to take away */
|
||||
credits = pEpDist->TxCredits - Limit;
|
||||
/* take them away */
|
||||
pEpDist->TxCredits -= credits;
|
||||
pCredInfo->CurrentFreeCredits += credits;
|
||||
}
|
||||
|
||||
/* give an endpoint some credits from the free credit pool */
|
||||
#define GiveCredits(pCredInfo,pEpDist,credits) \
|
||||
{ \
|
||||
(pEpDist)->TxCredits += (credits); \
|
||||
(pEpDist)->TxCreditsAssigned += (credits); \
|
||||
(pCredInfo)->CurrentFreeCredits -= (credits); \
|
||||
}
|
||||
|
||||
|
||||
/* default credit init callback.
|
||||
* This function is called in the context of HTCStart() to setup initial (application-specific)
|
||||
* credit distributions */
|
||||
static void ar6000_credit_init(void *Context,
|
||||
struct htc_endpoint_credit_dist *pEPList,
|
||||
int TotalCredits)
|
||||
{
|
||||
struct htc_endpoint_credit_dist *pCurEpDist;
|
||||
int count;
|
||||
struct common_credit_state_info *pCredInfo = (struct common_credit_state_info *)Context;
|
||||
|
||||
pCredInfo->CurrentFreeCredits = TotalCredits;
|
||||
pCredInfo->TotalAvailableCredits = TotalCredits;
|
||||
|
||||
pCurEpDist = pEPList;
|
||||
|
||||
/* run through the list and initialize */
|
||||
while (pCurEpDist != NULL) {
|
||||
|
||||
/* set minimums for each endpoint */
|
||||
pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
|
||||
|
||||
#ifdef CONFIG_GIVE_LOW_PRIORITY_STREAMS_MIN_CREDITS
|
||||
|
||||
if (TotalCredits > 4)
|
||||
{
|
||||
if ((pCurEpDist->ServiceID == WMI_DATA_BK_SVC) || (pCurEpDist->ServiceID == WMI_DATA_BE_SVC)){
|
||||
/* assign at least min credits to lower than VO priority services */
|
||||
GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin);
|
||||
/* force active */
|
||||
SET_EP_ACTIVE(pCurEpDist);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
|
||||
/* give control service some credits */
|
||||
GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin);
|
||||
/* control service is always marked active, it never goes inactive EVER */
|
||||
SET_EP_ACTIVE(pCurEpDist);
|
||||
} else if (pCurEpDist->ServiceID == WMI_DATA_BK_SVC) {
|
||||
/* this is the lowest priority data endpoint, save this off for easy access */
|
||||
pCredInfo->pLowestPriEpDist = pCurEpDist;
|
||||
}
|
||||
|
||||
/* Streams have to be created (explicit | implicit)for all kinds
|
||||
* of traffic. BE endpoints are also inactive in the beginning.
|
||||
* When BE traffic starts it creates implicit streams that
|
||||
* redistributes credits.
|
||||
*/
|
||||
|
||||
/* note, all other endpoints have minimums set but are initially given NO credits.
|
||||
* Credits will be distributed as traffic activity demands */
|
||||
pCurEpDist = pCurEpDist->pNext;
|
||||
}
|
||||
|
||||
if (pCredInfo->CurrentFreeCredits <= 0) {
|
||||
AR_DEBUG_PRINTF(ATH_LOG_INF, ("Not enough credits (%d) to do credit distributions \n", TotalCredits));
|
||||
A_ASSERT(false);
|
||||
return;
|
||||
}
|
||||
|
||||
/* reset list */
|
||||
pCurEpDist = pEPList;
|
||||
/* now run through the list and set max operating credit limits for everyone */
|
||||
while (pCurEpDist != NULL) {
|
||||
if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
|
||||
/* control service max is just 1 max message */
|
||||
pCurEpDist->TxCreditsNorm = pCurEpDist->TxCreditsPerMaxMsg;
|
||||
} else {
|
||||
/* for the remaining data endpoints, we assume that each TxCreditsPerMaxMsg are
|
||||
* the same.
|
||||
* We use a simple calculation here, we take the remaining credits and
|
||||
* determine how many max messages this can cover and then set each endpoint's
|
||||
* normal value equal to 3/4 this amount.
|
||||
* */
|
||||
count = (pCredInfo->CurrentFreeCredits/pCurEpDist->TxCreditsPerMaxMsg) * pCurEpDist->TxCreditsPerMaxMsg;
|
||||
count = (count * 3) >> 2;
|
||||
count = max(count,pCurEpDist->TxCreditsPerMaxMsg);
|
||||
/* set normal */
|
||||
pCurEpDist->TxCreditsNorm = count;
|
||||
|
||||
}
|
||||
pCurEpDist = pCurEpDist->pNext;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* default credit distribution callback
|
||||
* This callback is invoked whenever endpoints require credit distributions.
|
||||
* A lock is held while this function is invoked, this function shall NOT block.
|
||||
* The pEPDistList is a list of distribution structures in prioritized order as
|
||||
* defined by the call to the HTCSetCreditDistribution() api.
|
||||
*
|
||||
*/
|
||||
static void ar6000_credit_distribute(void *Context,
|
||||
struct htc_endpoint_credit_dist *pEPDistList,
|
||||
HTC_CREDIT_DIST_REASON Reason)
|
||||
{
|
||||
struct htc_endpoint_credit_dist *pCurEpDist;
|
||||
struct common_credit_state_info *pCredInfo = (struct common_credit_state_info *)Context;
|
||||
|
||||
switch (Reason) {
|
||||
case HTC_CREDIT_DIST_SEND_COMPLETE :
|
||||
pCurEpDist = pEPDistList;
|
||||
/* we are given the start of the endpoint distribution list.
|
||||
* There may be one or more endpoints to service.
|
||||
* Run through the list and distribute credits */
|
||||
while (pCurEpDist != NULL) {
|
||||
|
||||
if (pCurEpDist->TxCreditsToDist > 0) {
|
||||
/* return the credits back to the endpoint */
|
||||
pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
|
||||
/* always zero out when we are done */
|
||||
pCurEpDist->TxCreditsToDist = 0;
|
||||
|
||||
if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsAssigned) {
|
||||
/* reduce to the assigned limit, previous credit reductions
|
||||
* could have caused the limit to change */
|
||||
ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsAssigned);
|
||||
}
|
||||
|
||||
if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsNorm) {
|
||||
/* oversubscribed endpoints need to reduce back to normal */
|
||||
ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsNorm);
|
||||
}
|
||||
|
||||
if (!IS_EP_ACTIVE(pCurEpDist)) {
|
||||
/* endpoint is inactive, now check for messages waiting for credits */
|
||||
if (pCurEpDist->TxQueueDepth == 0) {
|
||||
/* EP is inactive and there are no pending messages,
|
||||
* reduce credits back to zero to recover credits */
|
||||
ReduceCredits(pCredInfo, pCurEpDist, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pCurEpDist = pCurEpDist->pNext;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case HTC_CREDIT_DIST_ACTIVITY_CHANGE :
|
||||
RedistributeCredits(pCredInfo,pEPDistList);
|
||||
break;
|
||||
case HTC_CREDIT_DIST_SEEK_CREDITS :
|
||||
SeekCredits(pCredInfo,pEPDistList);
|
||||
break;
|
||||
case HTC_DUMP_CREDIT_STATE :
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Credit Distribution, total : %d, free : %d\n",
|
||||
pCredInfo->TotalAvailableCredits, pCredInfo->CurrentFreeCredits));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
/* sanity checks done after each distribution action */
|
||||
A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits);
|
||||
A_ASSERT(pCredInfo->CurrentFreeCredits >= 0);
|
||||
|
||||
}
|
||||
|
||||
/* redistribute credits based on activity change */
|
||||
static void RedistributeCredits(struct common_credit_state_info *pCredInfo,
|
||||
struct htc_endpoint_credit_dist *pEPDistList)
|
||||
{
|
||||
struct htc_endpoint_credit_dist *pCurEpDist = pEPDistList;
|
||||
|
||||
/* walk through the list and remove credits from inactive endpoints */
|
||||
while (pCurEpDist != NULL) {
|
||||
|
||||
#ifdef CONFIG_GIVE_LOW_PRIORITY_STREAMS_MIN_CREDITS
|
||||
|
||||
if ((pCurEpDist->ServiceID == WMI_DATA_BK_SVC) || (pCurEpDist->ServiceID == WMI_DATA_BE_SVC)) {
|
||||
/* force low priority streams to always be active to retain their minimum credit distribution */
|
||||
SET_EP_ACTIVE(pCurEpDist);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (pCurEpDist->ServiceID != WMI_CONTROL_SVC) {
|
||||
if (!IS_EP_ACTIVE(pCurEpDist)) {
|
||||
if (pCurEpDist->TxQueueDepth == 0) {
|
||||
/* EP is inactive and there are no pending messages, reduce credits back to zero */
|
||||
ReduceCredits(pCredInfo, pCurEpDist, 0);
|
||||
} else {
|
||||
/* we cannot zero the credits assigned to this EP, but to keep
|
||||
* the credits available for these leftover packets, reduce to
|
||||
* a minimum */
|
||||
ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsMin);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* NOTE in the active case, we do not need to do anything further,
|
||||
* when an EP goes active and needs credits, HTC will call into
|
||||
* our distribution function using a reason code of HTC_CREDIT_DIST_SEEK_CREDITS */
|
||||
|
||||
pCurEpDist = pCurEpDist->pNext;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* HTC has an endpoint that needs credits, pEPDist is the endpoint in question */
|
||||
static void SeekCredits(struct common_credit_state_info *pCredInfo,
|
||||
struct htc_endpoint_credit_dist *pEPDist)
|
||||
{
|
||||
struct htc_endpoint_credit_dist *pCurEpDist;
|
||||
int credits = 0;
|
||||
int need;
|
||||
|
||||
do {
|
||||
|
||||
if (pEPDist->ServiceID == WMI_CONTROL_SVC) {
|
||||
/* we never oversubscribe on the control service, this is not
|
||||
* a high performance path and the target never holds onto control
|
||||
* credits for too long */
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GIVE_LOW_PRIORITY_STREAMS_MIN_CREDITS
|
||||
if (pEPDist->ServiceID == WMI_DATA_VI_SVC) {
|
||||
if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm)) {
|
||||
/* limit VI service from oversubscribing */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (pEPDist->ServiceID == WMI_DATA_VO_SVC) {
|
||||
if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm)) {
|
||||
/* limit VO service from oversubscribing */
|
||||
break;
|
||||
}
|
||||
}
|
||||
#else
|
||||
if (pEPDist->ServiceID == WMI_DATA_VI_SVC) {
|
||||
if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) ||
|
||||
(pCredInfo->CurrentFreeCredits <= pEPDist->TxCreditsPerMaxMsg)) {
|
||||
/* limit VI service from oversubscribing */
|
||||
/* at least one free credit will not be used by VI */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (pEPDist->ServiceID == WMI_DATA_VO_SVC) {
|
||||
if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) ||
|
||||
(pCredInfo->CurrentFreeCredits <= pEPDist->TxCreditsPerMaxMsg)) {
|
||||
/* limit VO service from oversubscribing */
|
||||
/* at least one free credit will not be used by VO */
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* for all other services, we follow a simple algorithm of
|
||||
* 1. checking the free pool for credits
|
||||
* 2. checking lower priority endpoints for credits to take */
|
||||
|
||||
/* give what we can */
|
||||
credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
|
||||
|
||||
if (credits >= pEPDist->TxCreditsSeek) {
|
||||
/* we found some to fulfill the seek request */
|
||||
break;
|
||||
}
|
||||
|
||||
/* we don't have enough in the free pool, try taking away from lower priority services
|
||||
*
|
||||
* The rule for taking away credits:
|
||||
* 1. Only take from lower priority endpoints
|
||||
* 2. Only take what is allocated above the minimum (never starve an endpoint completely)
|
||||
* 3. Only take what you need.
|
||||
*
|
||||
* */
|
||||
|
||||
/* starting at the lowest priority */
|
||||
pCurEpDist = pCredInfo->pLowestPriEpDist;
|
||||
|
||||
/* work backwards until we hit the endpoint again */
|
||||
while (pCurEpDist != pEPDist) {
|
||||
/* calculate how many we need so far */
|
||||
need = pEPDist->TxCreditsSeek - pCredInfo->CurrentFreeCredits;
|
||||
|
||||
if ((pCurEpDist->TxCreditsAssigned - need) >= pCurEpDist->TxCreditsMin) {
|
||||
/* the current one has been allocated more than it's minimum and it
|
||||
* has enough credits assigned above it's minimum to fulfill our need
|
||||
* try to take away just enough to fulfill our need */
|
||||
ReduceCredits(pCredInfo,
|
||||
pCurEpDist,
|
||||
pCurEpDist->TxCreditsAssigned - need);
|
||||
|
||||
if (pCredInfo->CurrentFreeCredits >= pEPDist->TxCreditsSeek) {
|
||||
/* we have enough */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
pCurEpDist = pCurEpDist->pPrev;
|
||||
}
|
||||
|
||||
/* return what we can get */
|
||||
credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
|
||||
|
||||
} while (false);
|
||||
|
||||
/* did we find some credits? */
|
||||
if (credits) {
|
||||
/* give what we can */
|
||||
GiveCredits(pCredInfo, pEPDist, credits);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* initialize and setup credit distribution */
|
||||
int ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, struct common_credit_state_info *pCredInfo)
|
||||
{
|
||||
HTC_SERVICE_ID servicepriority[5];
|
||||
|
||||
A_MEMZERO(pCredInfo,sizeof(struct common_credit_state_info));
|
||||
|
||||
servicepriority[0] = WMI_CONTROL_SVC; /* highest */
|
||||
servicepriority[1] = WMI_DATA_VO_SVC;
|
||||
servicepriority[2] = WMI_DATA_VI_SVC;
|
||||
servicepriority[3] = WMI_DATA_BE_SVC;
|
||||
servicepriority[4] = WMI_DATA_BK_SVC; /* lowest */
|
||||
|
||||
/* set callbacks and priority list */
|
||||
HTCSetCreditDistribution(HTCHandle,
|
||||
pCredInfo,
|
||||
ar6000_credit_distribute,
|
||||
ar6000_credit_init,
|
||||
servicepriority,
|
||||
5);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
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Add table
Reference in a new issue